From nobody Thu Oct 9 13:20:02 2025 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E532F284B5A for ; Wed, 18 Jun 2025 09:41:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=170.10.133.124 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750239687; cv=none; b=OmAs06CtkiECyCa64m9reH8Tufqmj/Jti06AQuqy8AsRt2kLtu6rrhYuQhjGUweiWPqmlS63IX43dGM3K9OuqwnkSl5BJ6xtclIeACZPcxuFj4SAE6I2dDx841D7gZ0kzXW9pD40NMeiMdV2rabT/STYqNrTCV0gk/AfmE4ITpo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750239687; c=relaxed/simple; bh=/+JfV5Ks6zTLfAhNu5TTB9LCzWZQnp8C2/Sai6URYU8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=aiygqC2YimkZjDCeXrP1BG5g6BOCTVft+N3h6OlG0cAQZJMUuceHQrdUCr/8P7YhVcU9Z2hh+bWRlkG3W7KXtMQRb/Ls60ET4fFt2N7+dNjjUneUINwrQtgoYgABOAJe+qlxCLHbrfw8RVyqclsnXI94z8GayO9AIZ6r5lc5IQk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com; spf=pass smtp.mailfrom=redhat.com; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b=A+tovlZh; arc=none smtp.client-ip=170.10.133.124 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=redhat.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="A+tovlZh" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1750239685; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=wCh2D6joaySNbJXE1hejgkSYr1Lc6oM3ACPnz1eIPwY=; b=A+tovlZhRryyOnSeLrY02YuKlu87GT9K8JVALj1YE3js7GLq9BLZ+YVt4Nc8NWnW1SeeRw kY8TbmKI+c7j4kQ+m9W3+p6Inj9BDyCp+qz2dUorDj8Zwsj7kT1BsRl8KdqEwk73vlsSAk I/1BqTaonUywZff+M5kBTDGYgbBDTE8= Received: from mx-prod-mc-08.mail-002.prod.us-west-2.aws.redhat.com (ec2-35-165-154-97.us-west-2.compute.amazonaws.com [35.165.154.97]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-588-6g6f8BYlObKpbmgZKWN-9g-1; Wed, 18 Jun 2025 05:41:21 -0400 X-MC-Unique: 6g6f8BYlObKpbmgZKWN-9g-1 X-Mimecast-MFC-AGG-ID: 6g6f8BYlObKpbmgZKWN-9g_1750239679 Received: from mx-prod-int-04.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-04.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.40]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-08.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 51AB11800C25; Wed, 18 Jun 2025 09:41:19 +0000 (UTC) Received: from hydra.redhat.com (unknown [10.45.225.137]) by mx-prod-int-04.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id A7BEE19560A3; Wed, 18 Jun 2025 09:41:13 +0000 (UTC) From: Jocelyn Falempe To: Maarten Lankhorst , Jani Nikula , Rodrigo Vivi , Joonas Lahtinen , Tvrtko Ursulin , =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= , David Airlie , Simona Vetter , Christian Koenig , Huang Rui , Matthew Auld , Matthew Brost , Maxime Ripard , Thomas Zimmermann , intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: Jocelyn Falempe Subject: [PATCH v10 08/10] drm/i915/display: Add drm_panic support for Y-tiling with DPT Date: Wed, 18 Jun 2025 11:31:26 +0200 Message-ID: <20250618094011.238154-9-jfalempe@redhat.com> In-Reply-To: <20250618094011.238154-1-jfalempe@redhat.com> References: <20250618094011.238154-1-jfalempe@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.40 Content-Type: text/plain; charset="utf-8" On Alder Lake and later, it's not possible to disable tiling when DPT is enabled. So this commit implements Y-Tiling support, to still be able to draw the panic screen. Signed-off-by: Jocelyn Falempe --- v8: * Pass the tiling function to intel_bo_panic_setup() .../gpu/drm/i915/display/intel_atomic_plane.c | 64 ++++++++++++++++++- .../drm/i915/display/intel_display_types.h | 1 + .../drm/i915/display/skl_universal_plane.c | 15 +++-- drivers/gpu/drm/i915/gem/i915_gem_pages.c | 16 ++++- drivers/gpu/drm/xe/display/intel_bo.c | 5 +- 5 files changed, 93 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gp= u/drm/i915/display/intel_atomic_plane.c index 9e1c9d1e015f..044328d83df9 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c @@ -1271,6 +1271,32 @@ intel_cleanup_plane_fb(struct drm_plane *plane, intel_plane_unpin_fb(old_plane_state); } =20 +/* Handle Y-tiling, only if DPT is enabled (otherwise disabling tiling is = easier) + * All DPT hardware have 128-bytes width tiling, so Y-tile dimension is 32= x32 + * pixels for 32bits pixels. + */ +#define YTILE_WIDTH 32 +#define YTILE_HEIGHT 32 +#define YTILE_SIZE (YTILE_WIDTH * YTILE_HEIGHT * 4) + +static unsigned int intel_ytile_get_offset(unsigned int width, unsigned in= t x, unsigned int y) +{ + u32 offset; + unsigned int swizzle; + unsigned int width_in_blocks =3D DIV_ROUND_UP(width, 32); + + /* Block offset */ + offset =3D ((y / YTILE_HEIGHT) * width_in_blocks + (x / YTILE_WIDTH)) * Y= TILE_SIZE; + + x =3D x % YTILE_WIDTH; + y =3D y % YTILE_HEIGHT; + + /* bit order inside a block is x4 x3 x2 y4 y3 y2 y1 y0 x1 x0 */ + swizzle =3D (x & 3) | ((y & 0x1f) << 2) | ((x & 0x1c) << 5); + offset +=3D swizzle * 4; + return offset; +} + static void intel_panic_flush(struct drm_plane *plane) { struct intel_plane_state *plane_state =3D to_intel_plane_state(plane->sta= te); @@ -1294,6 +1320,35 @@ static void intel_panic_flush(struct drm_plane *plan= e) iplane->disable_tiling(iplane); } =20 +static unsigned int (*intel_get_tiling_func(u64 fb_modifier))(unsigned int= width, + unsigned int x, + unsigned int y) +{ + switch (fb_modifier) { + case I915_FORMAT_MOD_Y_TILED: + case I915_FORMAT_MOD_Y_TILED_CCS: + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: + case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: + return intel_ytile_get_offset; + case I915_FORMAT_MOD_4_TILED: + case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS: + case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS: + case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC: + case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS: + case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC: + case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS: + case I915_FORMAT_MOD_4_TILED_BMG_CCS: + case I915_FORMAT_MOD_4_TILED_LNL_CCS: + case I915_FORMAT_MOD_X_TILED: + case I915_FORMAT_MOD_Yf_TILED: + case I915_FORMAT_MOD_Yf_TILED_CCS: + default: + /* Not supported yet */ + return NULL; + } +} + static int intel_get_scanout_buffer(struct drm_plane *plane, struct drm_scanout_buffer *sb) { @@ -1319,8 +1374,13 @@ static int intel_get_scanout_buffer(struct drm_plane= *plane, } else { int ret; /* Can't disable tiling if DPT is in use */ - if (intel_fb_uses_dpt(fb)) - return -EOPNOTSUPP; + if (intel_fb_uses_dpt(fb)) { + if (fb->format->cpp[0] !=3D 4) + return -EOPNOTSUPP; + intel_fb->panic.tiling =3D intel_get_tiling_func(fb->modifier); + if (!intel_fb->panic.tiling) + return -EOPNOTSUPP; + } sb->private =3D intel_fb; ret =3D intel_bo_panic_setup(sb); if (ret) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/g= pu/drm/i915/display/intel_display_types.h index 6d6d2d948886..8db6a8c0686c 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -134,6 +134,7 @@ struct intel_panic_data { struct page **pages; int page; void *vaddr; + unsigned int (*tiling)(unsigned int x, unsigned int y, unsigned int width= ); }; =20 struct intel_framebuffer { diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/g= pu/drm/i915/display/skl_universal_plane.c index ef09ef7b101f..623eff23d9bc 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -2796,15 +2796,22 @@ static void skl_disable_tiling(struct intel_plane *= plane) { struct intel_plane_state *state =3D to_intel_plane_state(plane->base.stat= e); struct intel_display *display =3D to_intel_display(plane); - u32 stride =3D state->view.color_plane[0].scanout_stride / 64; + const struct drm_framebuffer *fb =3D state->hw.fb; u32 plane_ctl; =20 plane_ctl =3D intel_de_read(display, PLANE_CTL(plane->pipe, plane->id)); - plane_ctl &=3D ~PLANE_CTL_TILED_MASK; =20 - intel_de_write_fw(display, PLANE_STRIDE(plane->pipe, plane->id), - PLANE_STRIDE_(stride)); + if (intel_fb_uses_dpt(fb)) { + /* if DPT is enabled, keep tiling, but disable compression */ + plane_ctl &=3D ~PLANE_CTL_RENDER_DECOMPRESSION_ENABLE; + } else { + /* if DPT is not supported, disable tiling, and update stride */ + u32 stride =3D state->view.color_plane[0].scanout_stride / 64; =20 + plane_ctl &=3D ~PLANE_CTL_TILED_MASK; + intel_de_write_fw(display, PLANE_STRIDE(plane->pipe, plane->id), + PLANE_STRIDE_(stride)); + } intel_de_write_fw(display, PLANE_CTL(plane->pipe, plane->id), plane_ctl); =20 intel_de_write_fw(display, PLANE_SURF(plane->pipe, plane->id), diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c b/drivers/gpu/drm/i9= 15/gem/i915_gem_pages.c index 0bcf4647a2a0..bf7cd7555777 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c @@ -384,6 +384,15 @@ static struct page **i915_gem_object_panic_pages(struc= t drm_i915_gem_object *obj return pages; } =20 +static void i915_gem_object_panic_map_set_pixel(struct drm_scanout_buffer = *sb, unsigned int x, + unsigned int y, u32 color) +{ + struct intel_framebuffer *fb =3D (struct intel_framebuffer *)sb->private; + unsigned int offset =3D fb->panic.tiling(sb->width, x, y); + + iosys_map_wr(&sb->map[0], offset, u32, color); +} + /* * The scanout buffer pages are not mapped, so for each pixel, * use kmap_local_page_try_from_panic() to map the page, and write the pix= el. @@ -396,7 +405,10 @@ static void i915_gem_object_panic_page_set_pixel(struc= t drm_scanout_buffer *sb, unsigned int offset; struct intel_framebuffer *fb =3D (struct intel_framebuffer *)sb->private; =20 - offset =3D y * sb->pitch[0] + x * sb->format->cpp[0]; + if (fb->panic.tiling) + offset =3D fb->panic.tiling(sb->width, x, y); + else + offset =3D y * sb->pitch[0] + x * sb->format->cpp[0]; =20 new_page =3D offset >> PAGE_SHIFT; offset =3D offset % PAGE_SIZE; @@ -431,6 +443,8 @@ int i915_gem_object_panic_setup(struct drm_scanout_buff= er *sb) else iosys_map_set_vaddr(&sb->map[0], ptr); =20 + if (fb->panic.tiling) + sb->set_pixel =3D i915_gem_object_panic_map_set_pixel; return 0; } if (i915_gem_object_has_struct_page(obj)) { diff --git a/drivers/gpu/drm/xe/display/intel_bo.c b/drivers/gpu/drm/xe/dis= play/intel_bo.c index 8a6de2dda88c..26db10fc2f48 100644 --- a/drivers/gpu/drm/xe/display/intel_bo.c +++ b/drivers/gpu/drm/xe/display/intel_bo.c @@ -87,7 +87,10 @@ static void xe_panic_page_set_pixel(struct drm_scanout_b= uffer *sb, unsigned int unsigned int new_page; unsigned int offset; =20 - offset =3D y * sb->pitch[0] + x * sb->format->cpp[0]; + if (fb->panic.tiling) + offset =3D fb->panic.tiling(sb->width, x, y); + else + offset =3D y * sb->pitch[0] + x * sb->format->cpp[0]; =20 new_page =3D offset >> PAGE_SHIFT; offset =3D offset % PAGE_SIZE; --=20 2.49.0