From nobody Thu Oct 9 13:19:08 2025 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 51308281362 for ; Wed, 18 Jun 2025 09:40:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=170.10.129.124 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750239658; cv=none; b=XW1DAtlt7nqm84ZLy37k2BEiKmaqb9w5mxunItnVc6bGeJ+Ls4BSoz+qXLrrq3vG9xRFVXDdfdnG8vWD96QzjaOxdbHQ+VgOWUlJixKsS3kLHxM3y7vLkdyb3A31RTvflcRojl/ZMFto2Li5cCXhZKhpySAiavFfJgaK4N18EN8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750239658; c=relaxed/simple; bh=ArJz8+MlwzbkE2d5x1YhLJFLS0/eIvBqRo5lii+JH18=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Kd6WJgIvP+dlLu8g7TPETFV/q99kapqsBRgAvGPevrJfYou4/m59y6R1HUkzCmKZHKFwqOid3HC7ER+vk3K2FYyItlMUl6w/xY5dK2rAkfubb+FJQgj1HhhvEcAl/046stvc7UFkFRTNHMHXvTLxEj6Iejk2QJTOxzWE5R5ljoc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com; spf=pass smtp.mailfrom=redhat.com; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b=ZgK5jpBB; arc=none smtp.client-ip=170.10.129.124 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=redhat.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="ZgK5jpBB" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1750239655; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Ruh4yShbGYxTQcS0IX/LLG1eKJz1aqA/CDzZndRlDrI=; b=ZgK5jpBBAfnskcRjB94nsBi6P5eI5+bWKaE0d2lAKdEr7EAe/2CIrEK9NKCrnigJchNWXO D5vqQZtAZ6P/KK9PBmOQb/pGkLkZU6h0zxApAEvfBVdyYxa2DRQZNJnktT2el2OLQKOm50 GGhlzduzLzkTfElg0x2RxxV6n39jM1k= Received: from mx-prod-mc-08.mail-002.prod.us-west-2.aws.redhat.com (ec2-35-165-154-97.us-west-2.compute.amazonaws.com [35.165.154.97]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-543-WCU3sOzrMsGgEnt8GVX_1w-1; Wed, 18 Jun 2025 05:40:51 -0400 X-MC-Unique: WCU3sOzrMsGgEnt8GVX_1w-1 X-Mimecast-MFC-AGG-ID: WCU3sOzrMsGgEnt8GVX_1w_1750239648 Received: from mx-prod-int-04.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-04.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.40]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-08.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id A65E818002EC; Wed, 18 Jun 2025 09:40:48 +0000 (UTC) Received: from hydra.redhat.com (unknown [10.45.225.137]) by mx-prod-int-04.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id BD10D19560A3; Wed, 18 Jun 2025 09:40:42 +0000 (UTC) From: Jocelyn Falempe To: Maarten Lankhorst , Jani Nikula , Rodrigo Vivi , Joonas Lahtinen , Tvrtko Ursulin , =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= , David Airlie , Simona Vetter , Christian Koenig , Huang Rui , Matthew Auld , Matthew Brost , Maxime Ripard , Thomas Zimmermann , intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: Jocelyn Falempe Subject: [PATCH v10 03/10] drm/i915/display/i9xx: Add a disable_tiling() for i9xx planes Date: Wed, 18 Jun 2025 11:31:21 +0200 Message-ID: <20250618094011.238154-4-jfalempe@redhat.com> In-Reply-To: <20250618094011.238154-1-jfalempe@redhat.com> References: <20250618094011.238154-1-jfalempe@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.40 drm_panic draws in linear framebuffer, so it's easier to re-use the current framebuffer, and disable tiling in the panic handler, to show the panic screen. This assumes that the alignment restriction is always smaller in linear than in tiled. It also assumes that the linear framebuffer size is always smaller than the tiled. Signed-off-by: Jocelyn Falempe --- v7: * Reword commit message about alignment/size when disabling tiling (Ville = Syrj=C3=A4l=C3=A4) drivers/gpu/drm/i915/display/i9xx_plane.c | 23 +++++++++++++++++++ .../drm/i915/display/intel_display_types.h | 2 ++ 2 files changed, 25 insertions(+) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i9= 15/display/i9xx_plane.c index 8f15333a4b07..0807fae12450 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -905,6 +905,27 @@ static const struct drm_plane_funcs i8xx_plane_funcs = =3D { .format_mod_supported_async =3D intel_plane_format_mod_supported_async, }; =20 +static void i9xx_disable_tiling(struct intel_plane *plane) +{ + struct intel_display *display =3D to_intel_display(plane); + enum i9xx_plane_id i9xx_plane =3D plane->i9xx_plane; + u32 dspcntr; + u32 reg; + + dspcntr =3D intel_de_read_fw(display, DSPCNTR(display, i9xx_plane)); + dspcntr &=3D ~DISP_TILED; + intel_de_write_fw(display, DSPCNTR(display, i9xx_plane), dspcntr); + + if (DISPLAY_VER(display) >=3D 4) { + reg =3D intel_de_read_fw(display, DSPSURF(display, i9xx_plane)); + intel_de_write_fw(display, DSPSURF(display, i9xx_plane), reg); + + } else { + reg =3D intel_de_read_fw(display, DSPADDR(display, i9xx_plane)); + intel_de_write_fw(display, DSPADDR(display, i9xx_plane), reg); + } +} + struct intel_plane * intel_primary_plane_create(struct intel_display *display, enum pipe pipe) { @@ -1047,6 +1068,8 @@ intel_primary_plane_create(struct intel_display *disp= lay, enum pipe pipe) } } =20 + plane->disable_tiling =3D i9xx_disable_tiling; + modifiers =3D intel_fb_plane_get_modifiers(display, INTEL_PLANE_CAP_TILIN= G_X); =20 if (DISPLAY_VER(display) >=3D 5 || display->platform.g4x) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/g= pu/drm/i915/display/intel_display_types.h index ed4d743fc7c5..3654d88e9c5f 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1517,6 +1517,8 @@ struct intel_plane { bool async_flip); void (*enable_flip_done)(struct intel_plane *plane); void (*disable_flip_done)(struct intel_plane *plane); + /* For drm_panic */ + void (*disable_tiling)(struct intel_plane *plane); }; =20 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state= , base) --=20 2.49.0