From nobody Thu Oct 9 10:06:08 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id A6ECE28541B for ; Wed, 18 Jun 2025 09:30:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750239008; cv=none; b=n/HdjmHDY0KfFb7TTcCkz+gWR0Fsk/DeDNFAgFq/6CKGNOKjjcRsyBymq9UrcZUQjduYJkQAWT0bbDY9LSRAM2rffxxBcKMBsOWIAL1GhsnfG9e+bv9l9zcyNSHgGqbsnPAxjfivJlGqHmtYVq/nOaANrdHAJd1FZhsa1YIBM34= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750239008; c=relaxed/simple; bh=qMejaXAfIC9Z7sPH8SsEMoMJooInN9ADYgwuly+55io=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=LC/83F05VIXWWB81SuZYI5VP5BdLEXhhhLPJ6riidGT+eOGlvIYPyDcjclG36IWyHArpAdXauHYIdrTyiYUEIOOuYt6ol9S3iBrYwgr17RLgqxQRQTyZWaPm4tylQYbGQJNkjUDn5/bY4q8BoV02faS9ktG5xQlR36OCQc7yFKc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 539881BC0; Wed, 18 Jun 2025 02:29:45 -0700 (PDT) Received: from e129823.cambridge.arm.com (e129823.arm.com [10.1.197.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id A68CE3F58B; Wed, 18 Jun 2025 02:30:02 -0700 (PDT) From: Yeoreum Yun To: catalin.marinas@arm.com, pcc@google.com, will@kernel.org, broonie@kernel.org, anshuman.khandual@arm.com, joey.gouly@arm.com, maz@kernel.org, oliver.upton@linux.dev, frederic@kernel.org, hardevsinh.palaniya@siliconsignals.io, samuel.holland@sifive.com, palmer@rivosinc.com, charlie@rivosinc.com, thiago.bauermann@linaro.org, bgray@linux.ibm.com, tglx@linutronix.de, puranjay@kernel.org, david@redhat.com, yang@os.amperecomputing.com, mbenes@suse.cz, joel.granados@kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Yeoreum Yun Subject: [PATCH v7 1/8] arm64/cpufeature: add MTE_STORE_ONLY feature Date: Wed, 18 Jun 2025 10:29:50 +0100 Message-Id: <20250618092957.2069907-2-yeoreum.yun@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250618092957.2069907-1-yeoreum.yun@arm.com> References: <20250618092957.2069907-1-yeoreum.yun@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Since ARMv8.9, FEAT_MTE_STORE_ONLY can be used to restrict raise of tag check fault on store operation only. add MTE_STORE_ONLY feature. Signed-off-by: Yeoreum Yun Reviewed-by: Mark Brown --- arch/arm64/kernel/cpufeature.c | 8 ++++++++ arch/arm64/tools/cpucaps | 1 + 2 files changed, 9 insertions(+) diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 8a5284c733b7..fdc48aa1f0e2 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -321,6 +321,7 @@ static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = =3D { static const struct arm64_ftr_bits ftr_id_aa64pfr2[] =3D { ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL1_F= PMR_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL= 1_MTEFAR_SHIFT, 4, ID_AA64PFR2_EL1_MTEFAR_NI), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL= 1_MTESTOREONLY_SHIFT, 4, ID_AA64PFR2_EL1_MTESTOREONLY_NI), ARM64_FTR_END, }; =20 @@ -2882,6 +2883,13 @@ static const struct arm64_cpu_capabilities arm64_fea= tures[] =3D { .matches =3D has_cpuid_feature, ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, MTEFAR, IMP) }, + { + .desc =3D "Store Only MTE Tag Check", + .capability =3D ARM64_MTE_STORE_ONLY, + .type =3D ARM64_CPUCAP_SYSTEM_FEATURE, + .matches =3D has_cpuid_feature, + ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, MTESTOREONLY, IMP) + }, #endif /* CONFIG_ARM64_MTE */ { .desc =3D "RCpc load-acquire (LDAPR)", diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps index fe8f4f8ce95c..b96cb6d6bcaa 100644 --- a/arch/arm64/tools/cpucaps +++ b/arch/arm64/tools/cpucaps @@ -69,6 +69,7 @@ MPAM_HCR MTE MTE_ASYMM MTE_FAR +MTE_STORE_ONLY SME SME_FA64 SME2 --=20 LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7} From nobody Thu Oct 9 10:06:08 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 2235628541B for ; Wed, 18 Jun 2025 09:30:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750239011; cv=none; b=lDhhlNNwwXKyIxujx4IbEky216A6v4dB+Oi+/GmXYRKT8b+j9YHdb4RZrJ5I+VrQuyPrP4OKQodWpT1tCvmShdIxvjrKEHtiJkhRQZgDsufMKeyHaRoEaOA1jSGfTJphHKdzLrtzgksaSIgwz59ip8jZWOSWtITAOwG8osUqJ8s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750239011; c=relaxed/simple; bh=qWDgYU9GjYEy2tejugw8ZczCVa9XsBOTxffWoLLYfZk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=nh+7UBGifNXc/iR/7BqIdnzAYLBVmmcv4NaRAaYoGx1wwtOYA6USjpCogJnzbTqkDHfEtkxD9vkbUPW2Dx6iD5khfTVjbZqKK1huHIhL/tpeTqTLbJRymh+9q6ouD/6xoieDwsoQIrU/nQ9Juf9XvhZrilwTWlRoZHAEINlqzyw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E57441D13; Wed, 18 Jun 2025 02:29:48 -0700 (PDT) Received: from e129823.cambridge.arm.com (e129823.arm.com [10.1.197.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 3B2513F58B; Wed, 18 Jun 2025 02:30:06 -0700 (PDT) From: Yeoreum Yun To: catalin.marinas@arm.com, pcc@google.com, will@kernel.org, broonie@kernel.org, anshuman.khandual@arm.com, joey.gouly@arm.com, maz@kernel.org, oliver.upton@linux.dev, frederic@kernel.org, hardevsinh.palaniya@siliconsignals.io, samuel.holland@sifive.com, palmer@rivosinc.com, charlie@rivosinc.com, thiago.bauermann@linaro.org, bgray@linux.ibm.com, tglx@linutronix.de, puranjay@kernel.org, david@redhat.com, yang@os.amperecomputing.com, mbenes@suse.cz, joel.granados@kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Yeoreum Yun Subject: [PATCH v7 2/8] prctl: introduce PR_MTE_STORE_ONLY Date: Wed, 18 Jun 2025 10:29:51 +0100 Message-Id: <20250618092957.2069907-3-yeoreum.yun@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250618092957.2069907-1-yeoreum.yun@arm.com> References: <20250618092957.2069907-1-yeoreum.yun@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" PR_MTE_STORE_ONLY is used to restrict the MTE tag check for store opeartion only. Signed-off-by: Yeoreum Yun Reviewed-by: Mark Brown --- include/uapi/linux/prctl.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/uapi/linux/prctl.h b/include/uapi/linux/prctl.h index 43dec6eed559..f6fb137c407f 100644 --- a/include/uapi/linux/prctl.h +++ b/include/uapi/linux/prctl.h @@ -244,6 +244,8 @@ struct prctl_mm_map { # define PR_MTE_TAG_MASK (0xffffUL << PR_MTE_TAG_SHIFT) /* Unused; kept only for source compatibility */ # define PR_MTE_TCF_SHIFT 1 +/* MTE tag check store only */ +# define PR_MTE_STORE_ONLY (1UL << 19) /* RISC-V pointer masking tag length */ # define PR_PMLEN_SHIFT 24 # define PR_PMLEN_MASK (0x7fUL << PR_PMLEN_SHIFT) --=20 LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7} From nobody Thu Oct 9 10:06:08 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id B9B522874FD for ; Wed, 18 Jun 2025 09:30:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750239015; cv=none; b=ne2kTnLUtGo/W7HDNKFlJFwAZiQNRHGUSajVDu/rvl6seC3H+8aRkPZr4MmYnni3M0Z7NS0KX/FJfb2et6/BCnnke4e9AJ7RuP6BVnbrM9jGhRxp5usEcA28nxG9gX5/K+1853ESqMXTfKdAFjgUAngv6wXJKSNZ0M2J2vmqJWA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750239015; c=relaxed/simple; bh=OvoYifwEu2fBfkD0FjsApyBqsUv2Po5f7uUa/yrPNr8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Cww0bbz1jZinTtQsSoo/M6O+fxt88nzuDtSz7ykI0XX2BMVrFXxlX95bxlVcaUL+hbycEVLkf+Q00RYYT7AAC5AlLgBHAkomvJsbxMSXWplDRvAbKN3fz6Hk3VX67fQe1ufLWv91kFnODeIsytHpTeurAQgGs24S7EUuIZ5lpQI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 79D161D15; Wed, 18 Jun 2025 02:29:52 -0700 (PDT) Received: from e129823.cambridge.arm.com (e129823.arm.com [10.1.197.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id CCF123F58B; Wed, 18 Jun 2025 02:30:09 -0700 (PDT) From: Yeoreum Yun To: catalin.marinas@arm.com, pcc@google.com, will@kernel.org, broonie@kernel.org, anshuman.khandual@arm.com, joey.gouly@arm.com, maz@kernel.org, oliver.upton@linux.dev, frederic@kernel.org, hardevsinh.palaniya@siliconsignals.io, samuel.holland@sifive.com, palmer@rivosinc.com, charlie@rivosinc.com, thiago.bauermann@linaro.org, bgray@linux.ibm.com, tglx@linutronix.de, puranjay@kernel.org, david@redhat.com, yang@os.amperecomputing.com, mbenes@suse.cz, joel.granados@kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Yeoreum Yun Subject: [PATCH v7 3/8] arm64/kernel: support store-only mte tag check Date: Wed, 18 Jun 2025 10:29:52 +0100 Message-Id: <20250618092957.2069907-4-yeoreum.yun@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250618092957.2069907-1-yeoreum.yun@arm.com> References: <20250618092957.2069907-1-yeoreum.yun@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Introduce new flag -- MTE_CTRL_STORE_ONLY used to set store-only tag check. This flag isn't overridden by prefered tcf flag setting but set together with prefered setting of way to report tag check fault. Signed-off-by: Yeoreum Yun Reviewed-by: Mark Brown --- arch/arm64/include/asm/processor.h | 2 ++ arch/arm64/kernel/mte.c | 11 ++++++++++- arch/arm64/kernel/process.c | 6 +++++- 3 files changed, 17 insertions(+), 2 deletions(-) diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/pr= ocessor.h index 1bf1a3b16e88..61d62bfd5a7b 100644 --- a/arch/arm64/include/asm/processor.h +++ b/arch/arm64/include/asm/processor.h @@ -23,6 +23,8 @@ #define MTE_CTRL_TCF_ASYNC (1UL << 17) #define MTE_CTRL_TCF_ASYMM (1UL << 18) =20 +#define MTE_CTRL_STORE_ONLY (1UL << 19) + #ifndef __ASSEMBLY__ =20 #include diff --git a/arch/arm64/kernel/mte.c b/arch/arm64/kernel/mte.c index 2fbfd27ff5f2..e5e773844889 100644 --- a/arch/arm64/kernel/mte.c +++ b/arch/arm64/kernel/mte.c @@ -200,7 +200,7 @@ static void mte_update_sctlr_user(struct task_struct *t= ask) * program requested values go with what was requested. */ resolved_mte_tcf =3D (mte_ctrl & pref) ? pref : mte_ctrl; - sctlr &=3D ~SCTLR_EL1_TCF0_MASK; + sctlr &=3D ~(SCTLR_EL1_TCF0_MASK | SCTLR_EL1_TCSO0_MASK); /* * Pick an actual setting. The order in which we check for * set bits and map into register values determines our @@ -212,6 +212,10 @@ static void mte_update_sctlr_user(struct task_struct *= task) sctlr |=3D SYS_FIELD_PREP_ENUM(SCTLR_EL1, TCF0, ASYNC); else if (resolved_mte_tcf & MTE_CTRL_TCF_SYNC) sctlr |=3D SYS_FIELD_PREP_ENUM(SCTLR_EL1, TCF0, SYNC); + + if (mte_ctrl & MTE_CTRL_STORE_ONLY) + sctlr |=3D SYS_FIELD_PREP(SCTLR_EL1, TCSO0, 1); + task->thread.sctlr_user =3D sctlr; } =20 @@ -371,6 +375,9 @@ long set_mte_ctrl(struct task_struct *task, unsigned lo= ng arg) (arg & PR_MTE_TCF_SYNC)) mte_ctrl |=3D MTE_CTRL_TCF_ASYMM; =20 + if (arg & PR_MTE_STORE_ONLY) + mte_ctrl |=3D MTE_CTRL_STORE_ONLY; + task->thread.mte_ctrl =3D mte_ctrl; if (task =3D=3D current) { preempt_disable(); @@ -398,6 +405,8 @@ long get_mte_ctrl(struct task_struct *task) ret |=3D PR_MTE_TCF_ASYNC; if (mte_ctrl & MTE_CTRL_TCF_SYNC) ret |=3D PR_MTE_TCF_SYNC; + if (mte_ctrl & MTE_CTRL_STORE_ONLY) + ret |=3D PR_MTE_STORE_ONLY; =20 return ret; } diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c index a5ca15daeb8a..fc49f2b3ded1 100644 --- a/arch/arm64/kernel/process.c +++ b/arch/arm64/kernel/process.c @@ -849,10 +849,14 @@ long set_tagged_addr_ctrl(struct task_struct *task, u= nsigned long arg) if (is_compat_thread(ti)) return -EINVAL; =20 - if (system_supports_mte()) + if (system_supports_mte()) { valid_mask |=3D PR_MTE_TCF_SYNC | PR_MTE_TCF_ASYNC \ | PR_MTE_TAG_MASK; =20 + if (cpus_have_cap(ARM64_MTE_STORE_ONLY)) + valid_mask |=3D PR_MTE_STORE_ONLY; + } + if (arg & ~valid_mask) return -EINVAL; =20 --=20 LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7} From nobody Thu Oct 9 10:06:08 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 60A88283C9E for ; Wed, 18 Jun 2025 09:30:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750239019; cv=none; b=XC842JpHLTKi4QerG4d+q/YtNbls9W/aGRcsY3aOJQr81hxQbFHwi2tGeYO94N8Oe9x9Fc/xCBQskLwKrNy+TufvcJVcFW4wboBWkC7tfHGJJEWVFd/zjiEerzgo4VZbPtRtZEgpq3jSkeVhBpV7yJgzc/d/LNX2tH8i3nMo+c8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750239019; c=relaxed/simple; bh=qCJRytY2Rh8MyFpXTAnJ/gmOwtp7GF6QWpIP55oYvSE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=pxtcP61gl1ft6cnkQc9FuNgEyqctbo3FqE9RAv8BN+6t49B0abMQY5XenYQWjGw9bMHddj4zLvf+XvgEpIBP/8eIVxdG4dXFU7vb8OjO01nt4GDJMKfehIaawIjJoayjFlH5BE53aVu9HC+nPOtpHE3PI9Wx8yirmpXl9iHbQpE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1054B1D31; Wed, 18 Jun 2025 02:29:56 -0700 (PDT) Received: from e129823.cambridge.arm.com (e129823.arm.com [10.1.197.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 61AD63F58B; Wed, 18 Jun 2025 02:30:13 -0700 (PDT) From: Yeoreum Yun To: catalin.marinas@arm.com, pcc@google.com, will@kernel.org, broonie@kernel.org, anshuman.khandual@arm.com, joey.gouly@arm.com, maz@kernel.org, oliver.upton@linux.dev, frederic@kernel.org, hardevsinh.palaniya@siliconsignals.io, samuel.holland@sifive.com, palmer@rivosinc.com, charlie@rivosinc.com, thiago.bauermann@linaro.org, bgray@linux.ibm.com, tglx@linutronix.de, puranjay@kernel.org, david@redhat.com, yang@os.amperecomputing.com, mbenes@suse.cz, joel.granados@kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Yeoreum Yun Subject: [PATCH v7 4/8] arm64/hwcaps: add MTE_STORE_ONLY hwcaps Date: Wed, 18 Jun 2025 10:29:53 +0100 Message-Id: <20250618092957.2069907-5-yeoreum.yun@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250618092957.2069907-1-yeoreum.yun@arm.com> References: <20250618092957.2069907-1-yeoreum.yun@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Since ARMv8.9, FEAT_MTE_STORE_ONLY can be used to restrict raise of tag check fault on store operation only. add MTE_STORE_ONLY hwcaps so that user can use this feature. Signed-off-by: Yeoreum Yun --- Documentation/arch/arm64/elf_hwcaps.rst | 3 +++ arch/arm64/include/asm/hwcap.h | 1 + arch/arm64/include/uapi/asm/hwcap.h | 1 + arch/arm64/kernel/cpufeature.c | 1 + arch/arm64/kernel/cpuinfo.c | 1 + 5 files changed, 7 insertions(+) diff --git a/Documentation/arch/arm64/elf_hwcaps.rst b/Documentation/arch/a= rm64/elf_hwcaps.rst index 358f5af035ff..f58ada4d6cb2 100644 --- a/Documentation/arch/arm64/elf_hwcaps.rst +++ b/Documentation/arch/arm64/elf_hwcaps.rst @@ -438,6 +438,9 @@ HWCAP2_POE HWCAP3_MTE_FAR Functionality implied by ID_AA64PFR2_EL1.MTEFAR =3D=3D 0b0001. =20 +HWCAP3_MTE_STORE_ONLY + Functionality implied by ID_AA64PFR2_EL1.MTESTOREONLY =3D=3D 0b0001. + 4. Unused AT_HWCAP bits ----------------------- =20 diff --git a/arch/arm64/include/asm/hwcap.h b/arch/arm64/include/asm/hwcap.h index 28dd1ac29ecc..13f94c8ddfc0 100644 --- a/arch/arm64/include/asm/hwcap.h +++ b/arch/arm64/include/asm/hwcap.h @@ -177,6 +177,7 @@ =20 #define __khwcap3_feature(x) (const_ilog2(HWCAP3_ ## x) + 128) #define KERNEL_HWCAP_MTE_FAR __khwcap3_feature(MTE_FAR) +#define KERNEL_HWCAP_MTE_STORE_ONLY __khwcap3_feature(MTE_STORE_ONLY) =20 /* * This yields a mask that user programs can use to figure out what diff --git a/arch/arm64/include/uapi/asm/hwcap.h b/arch/arm64/include/uapi/= asm/hwcap.h index 7d22527a7975..72c78468b806 100644 --- a/arch/arm64/include/uapi/asm/hwcap.h +++ b/arch/arm64/include/uapi/asm/hwcap.h @@ -144,5 +144,6 @@ * HWCAP3 flags - for AT_HWCAP3 */ #define HWCAP3_MTE_FAR (1UL << 0) +#define HWCAP3_MTE_STORE_ONLY (1UL << 1) =20 #endif /* _UAPI__ASM_HWCAP_H */ diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index fdc48aa1f0e2..b4204fa743f0 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -3228,6 +3228,7 @@ static const struct arm64_cpu_capabilities arm64_elf_= hwcaps[] =3D { HWCAP_CAP(ID_AA64PFR1_EL1, MTE, MTE2, CAP_HWCAP, KERNEL_HWCAP_MTE), HWCAP_CAP(ID_AA64PFR1_EL1, MTE, MTE3, CAP_HWCAP, KERNEL_HWCAP_MTE3), HWCAP_CAP(ID_AA64PFR2_EL1, MTEFAR, IMP, CAP_HWCAP, KERNEL_HWCAP_MTE_FAR), + HWCAP_CAP(ID_AA64PFR2_EL1, MTESTOREONLY, IMP, CAP_HWCAP , KERNEL_HWCAP_MT= E_STORE_ONLY), #endif /* CONFIG_ARM64_MTE */ HWCAP_CAP(ID_AA64MMFR0_EL1, ECV, IMP, CAP_HWCAP, KERNEL_HWCAP_ECV), HWCAP_CAP(ID_AA64MMFR1_EL1, AFP, IMP, CAP_HWCAP, KERNEL_HWCAP_AFP), diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c index e552cb305641..ba834909a28b 100644 --- a/arch/arm64/kernel/cpuinfo.c +++ b/arch/arm64/kernel/cpuinfo.c @@ -161,6 +161,7 @@ static const char *const hwcap_str[] =3D { [KERNEL_HWCAP_SME_STMOP] =3D "smestmop", [KERNEL_HWCAP_SME_SMOP4] =3D "smesmop4", [KERNEL_HWCAP_MTE_FAR] =3D "mtefar", + [KERNEL_HWCAP_MTE_STORE_ONLY] =3D "mtestoreonly", }; =20 #ifdef CONFIG_COMPAT --=20 LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7} From nobody Thu Oct 9 10:06:08 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id DF8802874E0 for ; Wed, 18 Jun 2025 09:30:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750239022; cv=none; b=r1cTsCL9NFymrkldNDpVXREDUFgVITdsEbA6x6JZ4BLbBXpPEYFy3AjUd+IWNZwy+DWMBEOhjfK005jnFXW+p/Irc6Y9o2qDUA4zdYnEqqveDFhKk3AJmtIP6ZOphjErR4sF9xYKvbUe5kJ6FEwoXP2yPUSu/+m/eOiz66yRD9g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750239022; c=relaxed/simple; bh=4k2LEfIzPWBG4ppJbbhrLU0DESX0vB4ItYaBtVsmIQQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=AcqxbqKbUVkTA/HI7DlDliyh//EMnvpDVuKu2dlCW21LX5sPIPGzqjkGrsnKqb07Uv+U1cWHhgaVYssKQSWiGTacvY3d/Az8a7URNsPELXUzDt/oC00a+qX1nQSJwP2k5ZyHvGIcTCkv32/3Pe5cOc06Bcp/iTdLiBzPAbePH0Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A01151D34; Wed, 18 Jun 2025 02:29:59 -0700 (PDT) Received: from e129823.cambridge.arm.com (e129823.arm.com [10.1.197.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id EA2303F58B; Wed, 18 Jun 2025 02:30:16 -0700 (PDT) From: Yeoreum Yun To: catalin.marinas@arm.com, pcc@google.com, will@kernel.org, broonie@kernel.org, anshuman.khandual@arm.com, joey.gouly@arm.com, maz@kernel.org, oliver.upton@linux.dev, frederic@kernel.org, hardevsinh.palaniya@siliconsignals.io, samuel.holland@sifive.com, palmer@rivosinc.com, charlie@rivosinc.com, thiago.bauermann@linaro.org, bgray@linux.ibm.com, tglx@linutronix.de, puranjay@kernel.org, david@redhat.com, yang@os.amperecomputing.com, mbenes@suse.cz, joel.granados@kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Yeoreum Yun Subject: [PATCH v7 5/8] arm64/kvm: expose MTE_STORE_ONLY feature to guest Date: Wed, 18 Jun 2025 10:29:54 +0100 Message-Id: <20250618092957.2069907-6-yeoreum.yun@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250618092957.2069907-1-yeoreum.yun@arm.com> References: <20250618092957.2069907-1-yeoreum.yun@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" expose MTE_STORE_ONLY feature to guest. Signed-off-by: Yeoreum Yun --- arch/arm64/kvm/sys_regs.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index c8c92cb9da01..7bc99ed201eb 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1620,7 +1620,8 @@ static u64 __kvm_read_sanitised_id_reg(const struct k= vm_vcpu *vcpu, mask =3D ID_AA64PFR2_EL1_FPMR; =20 if (kvm_has_mte(vcpu->kvm)) - mask |=3D ID_AA64PFR2_EL1_MTEFAR; + mask |=3D ID_AA64PFR2_EL1_MTEFAR | + ID_AA64PFR2_EL1_MTESTOREONLY; =20 val &=3D mask; break; @@ -2884,7 +2885,8 @@ static const struct sys_reg_desc sys_reg_descs[] =3D { ID_AA64PFR1_EL1_MTE)), ID_WRITABLE(ID_AA64PFR2_EL1, ID_AA64PFR2_EL1_FPMR | - ID_AA64PFR2_EL1_MTEFAR), + ID_AA64PFR2_EL1_MTEFAR | + ID_AA64PFR2_EL1_MTESTOREONLY), ID_UNALLOCATED(4,3), ID_WRITABLE(ID_AA64ZFR0_EL1, ~ID_AA64ZFR0_EL1_RES0), ID_HIDDEN(ID_AA64SMFR0_EL1), --=20 LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7} From nobody Thu Oct 9 10:06:08 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 77C56280330 for ; Wed, 18 Jun 2025 09:30:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750239025; cv=none; b=JCbFq1L20Bf6uS5vhrRzTWRa2+N3XFpEPHYayTNKfBz7DfMNABTdCSaH9pXdz6A/6ypM2sAm5qGdrTmVRWZpJUc/MxrVEeXBaUyrvX6kY8R5iEbB/pAAfBZy3Wejtq+UzQfem9Jm8eO6M7O+buLbQWzN9gPP56Q01zS6nrQgjuQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750239025; c=relaxed/simple; bh=/MdH+7ST7aOwqAS6gtG4n/fMsoPz47C1sds1az0EVrE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=GOjUEsSMOQ/GBw1sKTiOfNJzk87+2bHTpzw4/TfYmPlh/DtLWOkhPOikr2KDvZwV9LOfs8XwVrHYhXOHYhuDj9lObqBdFGH7QFeOKT2XTlQG5JbcsZckfjwOY30viFLQOnMX/NxIiRMDfNUBkadk5tOgBrkTRVHiX3/J7zCOys8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3D20114BF; Wed, 18 Jun 2025 02:30:03 -0700 (PDT) Received: from e129823.cambridge.arm.com (e129823.arm.com [10.1.197.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 8774F3F58B; Wed, 18 Jun 2025 02:30:20 -0700 (PDT) From: Yeoreum Yun To: catalin.marinas@arm.com, pcc@google.com, will@kernel.org, broonie@kernel.org, anshuman.khandual@arm.com, joey.gouly@arm.com, maz@kernel.org, oliver.upton@linux.dev, frederic@kernel.org, hardevsinh.palaniya@siliconsignals.io, samuel.holland@sifive.com, palmer@rivosinc.com, charlie@rivosinc.com, thiago.bauermann@linaro.org, bgray@linux.ibm.com, tglx@linutronix.de, puranjay@kernel.org, david@redhat.com, yang@os.amperecomputing.com, mbenes@suse.cz, joel.granados@kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Yeoreum Yun Subject: [PATCH v7 6/8] kselftest/arm64/abi: add MTE_STORE_ONLY feature hwcap test Date: Wed, 18 Jun 2025 10:29:55 +0100 Message-Id: <20250618092957.2069907-7-yeoreum.yun@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250618092957.2069907-1-yeoreum.yun@arm.com> References: <20250618092957.2069907-1-yeoreum.yun@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" add MTE_STORE_ONLY feature hwcap test. Signed-off-by: Yeoreum Yun Reviewed-by: Mark Brown --- tools/testing/selftests/arm64/abi/hwcap.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/tools/testing/selftests/arm64/abi/hwcap.c b/tools/testing/self= tests/arm64/abi/hwcap.c index e60bfb798ba2..42b59a994bd0 100644 --- a/tools/testing/selftests/arm64/abi/hwcap.c +++ b/tools/testing/selftests/arm64/abi/hwcap.c @@ -1104,6 +1104,12 @@ static const struct hwcap_data { .hwcap_bit =3D HWCAP3_MTE_FAR, .cpuinfo =3D "mtefar", }, + { + .name =3D "MTE_STOREONLY", + .at_hwcap =3D AT_HWCAP3, + .hwcap_bit =3D HWCAP3_MTE_STORE_ONLY, + .cpuinfo =3D "mtestoreonly", + }, }; =20 typedef void (*sighandler_fn)(int, siginfo_t *, void *); --=20 LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7} From nobody Thu Oct 9 10:06:08 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 19B66285043 for ; Wed, 18 Jun 2025 09:30:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750239029; cv=none; b=co3b8LO3RWnx8Zz+qaiXOZOiDuidpVmEovamcCzgL/8KLBfSB1XCFaYtFUT1So6dmYtK+OQzGgFI18WdxwRZ5SOgv2NYfNkXHMJPsB19kXrlKC2woJtM3dUGbloKVUet49I9WTC2jq/QuKhVDKTp5KfLoEAKxB6MufeDIjLsHkQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750239029; c=relaxed/simple; bh=sUJgID6wiHDWZzlQnWjqNCHUlK2uzTjuGEe7nZnYh1A=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Xz3ScdCqjPV3P86rww+nUh7Q4/JkTwDn5HJt/e4jsXEzKh6637Y8KnWSwG8INZjZTGX1tAO4FcexWa7ktsC6HGGV4oQWcJHX0myExFaAmCT/eagFlu+CXhxTIjKLR4/YKI5egnRJ3XEarF0adVE5Z4GBOpo0mejpyj9WXXdPwXY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C5A641BC0; Wed, 18 Jun 2025 02:30:06 -0700 (PDT) Received: from e129823.cambridge.arm.com (e129823.arm.com [10.1.197.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 252493F58B; Wed, 18 Jun 2025 02:30:24 -0700 (PDT) From: Yeoreum Yun To: catalin.marinas@arm.com, pcc@google.com, will@kernel.org, broonie@kernel.org, anshuman.khandual@arm.com, joey.gouly@arm.com, maz@kernel.org, oliver.upton@linux.dev, frederic@kernel.org, hardevsinh.palaniya@siliconsignals.io, samuel.holland@sifive.com, palmer@rivosinc.com, charlie@rivosinc.com, thiago.bauermann@linaro.org, bgray@linux.ibm.com, tglx@linutronix.de, puranjay@kernel.org, david@redhat.com, yang@os.amperecomputing.com, mbenes@suse.cz, joel.granados@kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Yeoreum Yun Subject: [PATCH v7 7/8] kselftest/arm64/mte: preparation for mte store only test Date: Wed, 18 Jun 2025 10:29:56 +0100 Message-Id: <20250618092957.2069907-8-yeoreum.yun@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250618092957.2069907-1-yeoreum.yun@arm.com> References: <20250618092957.2069907-1-yeoreum.yun@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Since ARMv8.9, FEAT_MTE_STORE_ONLY can be used to restrict raise of tag check fault on store operation only. This patch is preparation for testing FEAT_MTE_STORE_ONLY It shouldn't change test result. Signed-off-by: Yeoreum Yun Reviewed-by: Mark Brown --- .../selftests/arm64/mte/check_buffer_fill.c | 10 +++++----- .../selftests/arm64/mte/check_child_memory.c | 4 ++-- .../selftests/arm64/mte/check_hugetlb_options.c | 6 +++--- .../selftests/arm64/mte/check_ksm_options.c | 2 +- .../selftests/arm64/mte/check_mmap_options.c | 6 +++--- .../selftests/arm64/mte/check_tags_inclusion.c | 8 ++++---- tools/testing/selftests/arm64/mte/check_user_mem.c | 2 +- .../testing/selftests/arm64/mte/mte_common_util.c | 14 ++++++++++++-- .../testing/selftests/arm64/mte/mte_common_util.h | 3 ++- 9 files changed, 33 insertions(+), 22 deletions(-) diff --git a/tools/testing/selftests/arm64/mte/check_buffer_fill.c b/tools/= testing/selftests/arm64/mte/check_buffer_fill.c index 5248b5265aa4..ff4e07503349 100644 --- a/tools/testing/selftests/arm64/mte/check_buffer_fill.c +++ b/tools/testing/selftests/arm64/mte/check_buffer_fill.c @@ -31,7 +31,7 @@ static int check_buffer_by_byte(int mem_type, int mode) int i, j, item; bool err; =20 - mte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TAG); + mte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TAG, false); item =3D ARRAY_SIZE(sizes); =20 for (i =3D 0; i < item; i++) { @@ -68,7 +68,7 @@ static int check_buffer_underflow_by_byte(int mem_type, i= nt mode, bool err; char *und_ptr =3D NULL; =20 - mte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TAG); + mte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TAG, false); item =3D ARRAY_SIZE(sizes); for (i =3D 0; i < item; i++) { ptr =3D (char *)mte_allocate_memory_tag_range(sizes[i], mem_type, 0, @@ -164,7 +164,7 @@ static int check_buffer_overflow_by_byte(int mem_type, = int mode, size_t tagged_size, overflow_size; char *over_ptr =3D NULL; =20 - mte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TAG); + mte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TAG, false); item =3D ARRAY_SIZE(sizes); for (i =3D 0; i < item; i++) { ptr =3D (char *)mte_allocate_memory_tag_range(sizes[i], mem_type, 0, @@ -337,7 +337,7 @@ static int check_buffer_by_block(int mem_type, int mode) { int i, item, result =3D KSFT_PASS; =20 - mte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TAG); + mte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TAG, false); item =3D ARRAY_SIZE(sizes); cur_mte_cxt.fault_valid =3D false; for (i =3D 0; i < item; i++) { @@ -368,7 +368,7 @@ static int check_memory_initial_tags(int mem_type, int = mode, int mapping) int run, fd; int total =3D ARRAY_SIZE(sizes); =20 - mte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TAG); + mte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TAG, false); for (run =3D 0; run < total; run++) { /* check initial tags for anonymous mmap */ ptr =3D (char *)mte_allocate_memory(sizes[run], mem_type, mapping, false= ); diff --git a/tools/testing/selftests/arm64/mte/check_child_memory.c b/tools= /testing/selftests/arm64/mte/check_child_memory.c index b97ea3981c21..5e97ee792e4d 100644 --- a/tools/testing/selftests/arm64/mte/check_child_memory.c +++ b/tools/testing/selftests/arm64/mte/check_child_memory.c @@ -88,7 +88,7 @@ static int check_child_memory_mapping(int mem_type, int m= ode, int mapping) int item =3D ARRAY_SIZE(sizes); =20 item =3D ARRAY_SIZE(sizes); - mte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TAG); + mte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TAG, false); for (run =3D 0; run < item; run++) { ptr =3D (char *)mte_allocate_memory_tag_range(sizes[run], mem_type, mapp= ing, UNDERFLOW, OVERFLOW); @@ -109,7 +109,7 @@ static int check_child_file_mapping(int mem_type, int m= ode, int mapping) int run, fd, map_size, result =3D KSFT_PASS; int total =3D ARRAY_SIZE(sizes); =20 - mte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TAG); + mte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TAG, false); for (run =3D 0; run < total; run++) { fd =3D create_temp_file(); if (fd =3D=3D -1) diff --git a/tools/testing/selftests/arm64/mte/check_hugetlb_options.c b/to= ols/testing/selftests/arm64/mte/check_hugetlb_options.c index 4e644a606394..aad1234c7e0f 100644 --- a/tools/testing/selftests/arm64/mte/check_hugetlb_options.c +++ b/tools/testing/selftests/arm64/mte/check_hugetlb_options.c @@ -151,7 +151,7 @@ static int check_hugetlb_memory_mapping(int mem_type, i= nt mode, int mapping, int =20 map_size =3D default_huge_page_size(); =20 - mte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TAG); + mte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TAG, false); map_ptr =3D (char *)mte_allocate_memory(map_size, mem_type, mapping, fals= e); if (check_allocated_memory(map_ptr, map_size, mem_type, false) !=3D KSFT_= PASS) return KSFT_FAIL; @@ -180,7 +180,7 @@ static int check_clear_prot_mte_flag(int mem_type, int = mode, int mapping) unsigned long map_size; =20 prot_flag =3D PROT_READ | PROT_WRITE; - mte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TAG); + mte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TAG, false); map_size =3D default_huge_page_size(); map_ptr =3D (char *)mte_allocate_memory_tag_range(map_size, mem_type, map= ping, 0, 0); @@ -210,7 +210,7 @@ static int check_child_hugetlb_memory_mapping(int mem_t= ype, int mode, int mappin =20 map_size =3D default_huge_page_size(); =20 - mte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TAG); + mte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TAG, false); ptr =3D (char *)mte_allocate_memory_tag_range(map_size, mem_type, mapping, 0, 0); if (check_allocated_memory_range(ptr, map_size, mem_type, diff --git a/tools/testing/selftests/arm64/mte/check_ksm_options.c b/tools/= testing/selftests/arm64/mte/check_ksm_options.c index afea4e381862..0cf5faef1724 100644 --- a/tools/testing/selftests/arm64/mte/check_ksm_options.c +++ b/tools/testing/selftests/arm64/mte/check_ksm_options.c @@ -106,7 +106,7 @@ static int check_madvise_options(int mem_type, int mode= , int mapping) return err; } =20 - mte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TAG); + mte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TAG, false); ptr =3D mte_allocate_memory(TEST_UNIT * page_sz, mem_type, mapping, true); if (check_allocated_memory(ptr, TEST_UNIT * page_sz, mem_type, false) != =3D KSFT_PASS) return KSFT_FAIL; diff --git a/tools/testing/selftests/arm64/mte/check_mmap_options.c b/tools= /testing/selftests/arm64/mte/check_mmap_options.c index 91a81b4a9bfa..447c0ef25f71 100644 --- a/tools/testing/selftests/arm64/mte/check_mmap_options.c +++ b/tools/testing/selftests/arm64/mte/check_mmap_options.c @@ -90,7 +90,7 @@ static int check_anonymous_memory_mapping(int mem_type, i= nt mode, int mapping, i int run, result, map_size; int item =3D ARRAY_SIZE(sizes); =20 - mte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TAG); + mte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TAG, false); for (run =3D 0; run < item; run++) { map_size =3D sizes[run] + OVERFLOW + UNDERFLOW; map_ptr =3D (char *)mte_allocate_memory(map_size, mem_type, mapping, fal= se); @@ -122,7 +122,7 @@ static int check_file_memory_mapping(int mem_type, int = mode, int mapping, int ta int total =3D ARRAY_SIZE(sizes); int result =3D KSFT_PASS; =20 - mte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TAG); + mte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TAG, false); for (run =3D 0; run < total; run++) { fd =3D create_temp_file(); if (fd =3D=3D -1) @@ -161,7 +161,7 @@ static int check_clear_prot_mte_flag(int mem_type, int = mode, int mapping, int at int total =3D ARRAY_SIZE(sizes); =20 prot_flag =3D PROT_READ | PROT_WRITE; - mte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TAG); + mte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TAG, false); for (run =3D 0; run < total; run++) { map_size =3D sizes[run] + OVERFLOW + UNDERFLOW; ptr =3D (char *)mte_allocate_memory_tag_range(sizes[run], mem_type, mapp= ing, diff --git a/tools/testing/selftests/arm64/mte/check_tags_inclusion.c b/too= ls/testing/selftests/arm64/mte/check_tags_inclusion.c index b96296ab9870..4b764f2a8185 100644 --- a/tools/testing/selftests/arm64/mte/check_tags_inclusion.c +++ b/tools/testing/selftests/arm64/mte/check_tags_inclusion.c @@ -57,7 +57,7 @@ static int check_single_included_tags(int mem_type, int m= ode) return KSFT_FAIL; =20 for (tag =3D 0; (tag < MT_TAG_COUNT) && (result =3D=3D KSFT_PASS); tag++)= { - ret =3D mte_switch_mode(mode, MT_INCLUDE_VALID_TAG(tag)); + ret =3D mte_switch_mode(mode, MT_INCLUDE_VALID_TAG(tag), false); if (ret !=3D 0) result =3D KSFT_FAIL; /* Try to catch a excluded tag by a number of tries. */ @@ -91,7 +91,7 @@ static int check_multiple_included_tags(int mem_type, int= mode) =20 for (tag =3D 0; (tag < MT_TAG_COUNT - 1) && (result =3D=3D KSFT_PASS); ta= g++) { excl_mask |=3D 1 << tag; - mte_switch_mode(mode, MT_INCLUDE_VALID_TAGS(excl_mask)); + mte_switch_mode(mode, MT_INCLUDE_VALID_TAGS(excl_mask), false); /* Try to catch a excluded tag by a number of tries. */ for (run =3D 0; (run < RUNS) && (result =3D=3D KSFT_PASS); run++) { ptr =3D mte_insert_tags(ptr, BUFFER_SIZE); @@ -120,7 +120,7 @@ static int check_all_included_tags(int mem_type, int mo= de) mem_type, false) !=3D KSFT_PASS) return KSFT_FAIL; =20 - ret =3D mte_switch_mode(mode, MT_INCLUDE_TAG_MASK); + ret =3D mte_switch_mode(mode, MT_INCLUDE_TAG_MASK, false); if (ret !=3D 0) return KSFT_FAIL; /* Try to catch a excluded tag by a number of tries. */ @@ -145,7 +145,7 @@ static int check_none_included_tags(int mem_type, int m= ode) if (check_allocated_memory(ptr, BUFFER_SIZE, mem_type, false) !=3D KSFT_P= ASS) return KSFT_FAIL; =20 - ret =3D mte_switch_mode(mode, MT_EXCLUDE_TAG_MASK); + ret =3D mte_switch_mode(mode, MT_EXCLUDE_TAG_MASK, false); if (ret !=3D 0) return KSFT_FAIL; /* Try to catch a excluded tag by a number of tries. */ diff --git a/tools/testing/selftests/arm64/mte/check_user_mem.c b/tools/tes= ting/selftests/arm64/mte/check_user_mem.c index d1d14aaaba16..fb7936c4e097 100644 --- a/tools/testing/selftests/arm64/mte/check_user_mem.c +++ b/tools/testing/selftests/arm64/mte/check_user_mem.c @@ -44,7 +44,7 @@ static int check_usermem_access_fault(int mem_type, int m= ode, int mapping, =20 err =3D KSFT_PASS; len =3D 2 * page_sz; - mte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TAG); + mte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TAG, false); fd =3D create_temp_file(); if (fd =3D=3D -1) return KSFT_FAIL; diff --git a/tools/testing/selftests/arm64/mte/mte_common_util.c b/tools/te= sting/selftests/arm64/mte/mte_common_util.c index 10dcbc37e379..397e57dd946a 100644 --- a/tools/testing/selftests/arm64/mte/mte_common_util.c +++ b/tools/testing/selftests/arm64/mte/mte_common_util.c @@ -28,8 +28,10 @@ =20 struct mte_fault_cxt cur_mte_cxt; bool mtefar_support; +bool mtestonly_support; static unsigned int mte_cur_mode; static unsigned int mte_cur_pstate_tco; +static bool mte_cur_stonly; =20 void mte_default_handler(int signum, siginfo_t *si, void *uc) { @@ -314,7 +316,7 @@ void mte_initialize_current_context(int mode, uintptr_t= ptr, ssize_t range) cur_mte_cxt.trig_si_code =3D 0; } =20 -int mte_switch_mode(int mte_option, unsigned long incl_mask) +int mte_switch_mode(int mte_option, unsigned long incl_mask, bool stonly) { unsigned long en =3D 0; =20 @@ -346,6 +348,9 @@ int mte_switch_mode(int mte_option, unsigned long incl_= mask) break; } =20 + if (mtestonly_support && stonly) + en |=3D PR_MTE_STORE_ONLY; + en |=3D (incl_mask << PR_MTE_TAG_SHIFT); /* Enable address tagging ABI, mte error reporting mode and tag inclusion= mask. */ if (prctl(PR_SET_TAGGED_ADDR_CTRL, en, 0, 0, 0) !=3D 0) { @@ -370,6 +375,9 @@ int mte_default_setup(void) =20 mtefar_support =3D !!(hwcaps3 & HWCAP3_MTE_FAR); =20 + if (hwcaps3 & HWCAP3_MTE_STORE_ONLY) + mtestonly_support =3D true; + /* Get current mte mode */ ret =3D prctl(PR_GET_TAGGED_ADDR_CTRL, en, 0, 0, 0); if (ret < 0) { @@ -383,6 +391,8 @@ int mte_default_setup(void) else if (ret & PR_MTE_TCF_NONE) mte_cur_mode =3D MTE_NONE_ERR; =20 + mte_cur_stonly =3D (ret & PR_MTE_STORE_ONLY) ? true : false; + mte_cur_pstate_tco =3D mte_get_pstate_tco(); /* Disable PSTATE.TCO */ mte_disable_pstate_tco(); @@ -391,7 +401,7 @@ int mte_default_setup(void) =20 void mte_restore_setup(void) { - mte_switch_mode(mte_cur_mode, MTE_ALLOW_NON_ZERO_TAG); + mte_switch_mode(mte_cur_mode, MTE_ALLOW_NON_ZERO_TAG, mte_cur_stonly); if (mte_cur_pstate_tco =3D=3D MT_PSTATE_TCO_EN) mte_enable_pstate_tco(); else if (mte_cur_pstate_tco =3D=3D MT_PSTATE_TCO_DIS) diff --git a/tools/testing/selftests/arm64/mte/mte_common_util.h b/tools/te= sting/selftests/arm64/mte/mte_common_util.h index 045e4ad2f018..250d671329a5 100644 --- a/tools/testing/selftests/arm64/mte/mte_common_util.h +++ b/tools/testing/selftests/arm64/mte/mte_common_util.h @@ -38,6 +38,7 @@ struct mte_fault_cxt { =20 extern struct mte_fault_cxt cur_mte_cxt; extern bool mtefar_support; +extern bool mtestonly_support; =20 /* MTE utility functions */ void mte_default_handler(int signum, siginfo_t *si, void *uc); @@ -60,7 +61,7 @@ void *mte_insert_atag(void *ptr); void *mte_clear_atag(void *ptr); int mte_default_setup(void); void mte_restore_setup(void); -int mte_switch_mode(int mte_option, unsigned long incl_mask); +int mte_switch_mode(int mte_option, unsigned long incl_mask, bool stonly); void mte_initialize_current_context(int mode, uintptr_t ptr, ssize_t range= ); =20 /* Common utility functions */ --=20 LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7} From nobody Thu Oct 9 10:06:08 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id B1916283CB0 for ; Wed, 18 Jun 2025 09:30:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750239033; cv=none; b=s6dJSmpyrJGi89HG61wWefYPtc3KE6+F5wtC/8+rt2XVEz/IDrYgpLbprBRRFHNWie0s/vLjLcU8JOP/YdNxyCyqDj3J6wBUTQL0V1ggHK4z0tZDkOaY1vhtC99q67BCpNWEYyw6AR63yvRtepLyv1Y3XptifJ/tBk9S3aott1U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750239033; c=relaxed/simple; bh=TQThQFQx4m6BV3hRx3IRUB9DlYaYPEbWVYfudCwUrXw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=U50pZ5LrS9Pn6dYiuHlJ9dQk1St22W2852ddQLtfjpy4rgRyhKzxZrnlSKCVJj48Mfufx3AeOLbroIxkeiHYQn9Kstq8ucQGKBEfHmKBRu9hll2BoYbaAZAf+1SnVmpAbAXUu2egk2MsU0QeRj844sZKbWfZRdY89W5wWtcIsFk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7A44A14BF; Wed, 18 Jun 2025 02:30:10 -0700 (PDT) Received: from e129823.cambridge.arm.com (e129823.arm.com [10.1.197.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id AE9823F58B; Wed, 18 Jun 2025 02:30:27 -0700 (PDT) From: Yeoreum Yun To: catalin.marinas@arm.com, pcc@google.com, will@kernel.org, broonie@kernel.org, anshuman.khandual@arm.com, joey.gouly@arm.com, maz@kernel.org, oliver.upton@linux.dev, frederic@kernel.org, hardevsinh.palaniya@siliconsignals.io, samuel.holland@sifive.com, palmer@rivosinc.com, charlie@rivosinc.com, thiago.bauermann@linaro.org, bgray@linux.ibm.com, tglx@linutronix.de, puranjay@kernel.org, david@redhat.com, yang@os.amperecomputing.com, mbenes@suse.cz, joel.granados@kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Yeoreum Yun Subject: [PATCH v7 8/8] kselftest/arm64/mte: add MTE_STORE_ONLY testcases Date: Wed, 18 Jun 2025 10:29:57 +0100 Message-Id: <20250618092957.2069907-9-yeoreum.yun@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250618092957.2069907-1-yeoreum.yun@arm.com> References: <20250618092957.2069907-1-yeoreum.yun@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Since ARMv8.9, FEAT_MTE_STORE_ONLY can be used to restrict raise of tag check fault on store operation only. Adds new test cases using MTE_STORE_ONLY feature. Signed-off-by: Yeoreum Yun Reviewed-by: Mark Brown --- .../selftests/arm64/mte/check_mmap_options.c | 361 +++++++++++++++++- .../testing/selftests/arm64/mte/check_prctl.c | 25 +- 2 files changed, 366 insertions(+), 20 deletions(-) diff --git a/tools/testing/selftests/arm64/mte/check_mmap_options.c b/tools= /testing/selftests/arm64/mte/check_mmap_options.c index 447c0ef25f71..c100af3012cb 100644 --- a/tools/testing/selftests/arm64/mte/check_mmap_options.c +++ b/tools/testing/selftests/arm64/mte/check_mmap_options.c @@ -35,6 +35,11 @@ enum mte_mem_check_type { CHECK_CLEAR_PROT_MTE =3D 2, }; =20 +enum mte_tag_op_type { + TAG_OP_ALL =3D 0, + TAG_OP_STONLY =3D 1, +}; + struct check_mmap_testcase { int check_type; int mem_type; @@ -42,17 +47,24 @@ struct check_mmap_testcase { int mapping; int tag_check; int atag_check; + int tag_op; bool enable_tco; }; =20 +#define TAG_OP_ALL 0 +#define TAG_OP_STONLY 1 + static size_t page_size; static int sizes[] =3D { 1, 537, 989, 1269, MT_GRANULE_SIZE - 1, MT_GRANULE_SIZE, /* page size - 1*/ 0, /* page_size */ 0, /* page size + 1 */ 0 }; =20 -static int check_mte_memory(char *ptr, int size, int mode, int tag_check, = int atag_check) +static int check_mte_memory(char *ptr, int size, int mode, + int tag_check,int atag_check, int tag_op) { + char buf[MT_GRANULE_SIZE]; + if (!mtefar_support && atag_check =3D=3D ATAG_CHECK_ON) return KSFT_SKIP; =20 @@ -81,16 +93,34 @@ static int check_mte_memory(char *ptr, int size, int mo= de, int tag_check, int at if (cur_mte_cxt.fault_valid =3D=3D true && tag_check =3D=3D TAG_CHECK_OFF) return KSFT_FAIL; =20 + if (tag_op =3D=3D TAG_OP_STONLY) { + mte_initialize_current_context(mode, (uintptr_t)ptr, -UNDERFLOW); + memcpy(buf, ptr - UNDERFLOW, MT_GRANULE_SIZE); + mte_wait_after_trig(); + if (cur_mte_cxt.fault_valid =3D=3D true) + return KSFT_FAIL; + + mte_initialize_current_context(mode, (uintptr_t)ptr, size + OVERFLOW); + memcpy(buf, ptr + size, MT_GRANULE_SIZE); + mte_wait_after_trig(); + if (cur_mte_cxt.fault_valid =3D=3D true) + return KSFT_FAIL; + } + return KSFT_PASS; } =20 -static int check_anonymous_memory_mapping(int mem_type, int mode, int mapp= ing, int tag_check, int atag_check) +static int check_anonymous_memory_mapping(int mem_type, int mode, int mapp= ing, + int tag_check, int atag_check, int tag_op) { char *ptr, *map_ptr; int run, result, map_size; int item =3D ARRAY_SIZE(sizes); =20 - mte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TAG, false); + if (tag_op =3D=3D TAG_OP_STONLY && !mtestonly_support) + return KSFT_SKIP; + + mte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TAG, tag_op); for (run =3D 0; run < item; run++) { map_size =3D sizes[run] + OVERFLOW + UNDERFLOW; map_ptr =3D (char *)mte_allocate_memory(map_size, mem_type, mapping, fal= se); @@ -106,7 +136,7 @@ static int check_anonymous_memory_mapping(int mem_type,= int mode, int mapping, i munmap((void *)map_ptr, map_size); return KSFT_FAIL; } - result =3D check_mte_memory(ptr, sizes[run], mode, tag_check, atag_check= ); + result =3D check_mte_memory(ptr, sizes[run], mode, tag_check, atag_check= , tag_op); mte_clear_tags((void *)ptr, sizes[run]); mte_free_memory((void *)map_ptr, map_size, mem_type, false); if (result !=3D KSFT_PASS) @@ -115,14 +145,18 @@ static int check_anonymous_memory_mapping(int mem_typ= e, int mode, int mapping, i return KSFT_PASS; } =20 -static int check_file_memory_mapping(int mem_type, int mode, int mapping, = int tag_check, int atag_check) +static int check_file_memory_mapping(int mem_type, int mode, int mapping, + int tag_check, int atag_check, int tag_op) { char *ptr, *map_ptr; int run, fd, map_size; int total =3D ARRAY_SIZE(sizes); int result =3D KSFT_PASS; =20 - mte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TAG, false); + if (tag_op =3D=3D TAG_OP_STONLY && !mtestonly_support) + return KSFT_SKIP; + + mte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TAG, tag_op); for (run =3D 0; run < total; run++) { fd =3D create_temp_file(); if (fd =3D=3D -1) @@ -144,7 +178,7 @@ static int check_file_memory_mapping(int mem_type, int = mode, int mapping, int ta close(fd); return KSFT_FAIL; } - result =3D check_mte_memory(ptr, sizes[run], mode, tag_check, atag_check= ); + result =3D check_mte_memory(ptr, sizes[run], mode, tag_check, atag_check= , tag_op); mte_clear_tags((void *)ptr, sizes[run]); munmap((void *)map_ptr, map_size); close(fd); @@ -177,10 +211,10 @@ static int check_clear_prot_mte_flag(int mem_type, in= t mode, int mapping, int at ksft_print_msg("FAIL: mprotect not ignoring clear PROT_MTE property\n"); return KSFT_FAIL; } - result =3D check_mte_memory(ptr, sizes[run], mode, TAG_CHECK_ON, atag_ch= eck); + result =3D check_mte_memory(ptr, sizes[run], mode, TAG_CHECK_ON, atag_ch= eck, TAG_OP_ALL); mte_free_memory_tag_range((void *)ptr, sizes[run], mem_type, UNDERFLOW, = OVERFLOW); if (result !=3D KSFT_PASS) - return KSFT_FAIL; + return result; =20 fd =3D create_temp_file(); if (fd =3D=3D -1) @@ -201,7 +235,7 @@ static int check_clear_prot_mte_flag(int mem_type, int = mode, int mapping, int at close(fd); return KSFT_FAIL; } - result =3D check_mte_memory(ptr, sizes[run], mode, TAG_CHECK_ON, atag_ch= eck); + result =3D check_mte_memory(ptr, sizes[run], mode, TAG_CHECK_ON, atag_ch= eck, TAG_OP_ALL); mte_free_memory_tag_range((void *)ptr, sizes[run], mem_type, UNDERFLOW, = OVERFLOW); close(fd); if (result !=3D KSFT_PASS) @@ -219,6 +253,7 @@ const char *format_test_name(struct check_mmap_testcase= *tc) const char *mapping_str; const char *tag_check_str; const char *atag_check_str; + const char *tag_op_str; =20 switch (tc->check_type) { case CHECK_ANON_MEM: @@ -303,6 +338,23 @@ const char *format_test_name(struct check_mmap_testcas= e *tc) check_type_str, mapping_str, sync_str, mem_type_str, tag_check_str, atag_check_str); =20 + switch (tc->tag_op) { + case TAG_OP_ALL: + tag_op_str =3D ""; + break; + case TAG_OP_STONLY: + tag_op_str =3D " / store-only"; + break; + default: + assert(0); + break; + } + + snprintf(test_name, TEST_NAME_MAX, + "Check %s with %s mapping, %s mode, %s memory and %s (%s%s)\n", + check_type_str, mapping_str, sync_str, mem_type_str, + tag_check_str, atag_check_str, tag_op_str); + return test_name; } =20 @@ -318,6 +370,7 @@ int main(int argc, char *argv[]) .mapping =3D MAP_PRIVATE, .tag_check =3D TAG_CHECK_OFF, .atag_check =3D ATAG_CHECK_OFF, + .tag_op =3D TAG_OP_ALL, .enable_tco =3D true, }, { @@ -327,6 +380,7 @@ int main(int argc, char *argv[]) .mapping =3D MAP_PRIVATE, .tag_check =3D TAG_CHECK_OFF, .atag_check =3D ATAG_CHECK_OFF, + .tag_op =3D TAG_OP_ALL, .enable_tco =3D true, }, { @@ -336,6 +390,7 @@ int main(int argc, char *argv[]) .mapping =3D MAP_PRIVATE, .tag_check =3D TAG_CHECK_OFF, .atag_check =3D ATAG_CHECK_OFF, + .tag_op =3D TAG_OP_ALL, .enable_tco =3D false, }, { @@ -345,6 +400,7 @@ int main(int argc, char *argv[]) .mapping =3D MAP_PRIVATE, .tag_check =3D TAG_CHECK_OFF, .atag_check =3D ATAG_CHECK_OFF, + .tag_op =3D TAG_OP_ALL, .enable_tco =3D false, }, { @@ -354,6 +410,7 @@ int main(int argc, char *argv[]) .mapping =3D MAP_PRIVATE, .tag_check =3D TAG_CHECK_ON, .atag_check =3D ATAG_CHECK_OFF, + .tag_op =3D TAG_OP_ALL, .enable_tco =3D false, }, { @@ -363,6 +420,7 @@ int main(int argc, char *argv[]) .mapping =3D MAP_PRIVATE, .tag_check =3D TAG_CHECK_ON, .atag_check =3D ATAG_CHECK_OFF, + .tag_op =3D TAG_OP_ALL, .enable_tco =3D false, }, { @@ -372,6 +430,7 @@ int main(int argc, char *argv[]) .mapping =3D MAP_SHARED, .tag_check =3D TAG_CHECK_ON, .atag_check =3D ATAG_CHECK_OFF, + .tag_op =3D TAG_OP_ALL, .enable_tco =3D false, }, { @@ -381,6 +440,7 @@ int main(int argc, char *argv[]) .mapping =3D MAP_SHARED, .tag_check =3D TAG_CHECK_ON, .atag_check =3D ATAG_CHECK_OFF, + .tag_op =3D TAG_OP_ALL, .enable_tco =3D false, }, { @@ -390,6 +450,7 @@ int main(int argc, char *argv[]) .mapping =3D MAP_PRIVATE, .tag_check =3D TAG_CHECK_ON, .atag_check =3D ATAG_CHECK_OFF, + .tag_op =3D TAG_OP_ALL, .enable_tco =3D false, }, { @@ -399,6 +460,7 @@ int main(int argc, char *argv[]) .mapping =3D MAP_PRIVATE, .tag_check =3D TAG_CHECK_ON, .atag_check =3D ATAG_CHECK_OFF, + .tag_op =3D TAG_OP_ALL, .enable_tco =3D false, }, { @@ -408,6 +470,7 @@ int main(int argc, char *argv[]) .mapping =3D MAP_SHARED, .tag_check =3D TAG_CHECK_ON, .atag_check =3D ATAG_CHECK_OFF, + .tag_op =3D TAG_OP_ALL, .enable_tco =3D false, }, { @@ -417,6 +480,7 @@ int main(int argc, char *argv[]) .mapping =3D MAP_SHARED, .tag_check =3D TAG_CHECK_ON, .atag_check =3D ATAG_CHECK_OFF, + .tag_op =3D TAG_OP_ALL, .enable_tco =3D false, }, { @@ -426,6 +490,7 @@ int main(int argc, char *argv[]) .mapping =3D MAP_PRIVATE, .tag_check =3D TAG_CHECK_ON, .atag_check =3D ATAG_CHECK_OFF, + .tag_op =3D TAG_OP_ALL, .enable_tco =3D false, }, { @@ -435,6 +500,7 @@ int main(int argc, char *argv[]) .mapping =3D MAP_PRIVATE, .tag_check =3D TAG_CHECK_ON, .atag_check =3D ATAG_CHECK_OFF, + .tag_op =3D TAG_OP_ALL, .enable_tco =3D false, }, { @@ -444,6 +510,7 @@ int main(int argc, char *argv[]) .mapping =3D MAP_SHARED, .tag_check =3D TAG_CHECK_ON, .atag_check =3D ATAG_CHECK_OFF, + .tag_op =3D TAG_OP_ALL, .enable_tco =3D false, }, { @@ -453,6 +520,7 @@ int main(int argc, char *argv[]) .mapping =3D MAP_SHARED, .tag_check =3D TAG_CHECK_ON, .atag_check =3D ATAG_CHECK_OFF, + .tag_op =3D TAG_OP_ALL, .enable_tco =3D false, }, { @@ -462,6 +530,7 @@ int main(int argc, char *argv[]) .mapping =3D MAP_PRIVATE, .tag_check =3D TAG_CHECK_ON, .atag_check =3D ATAG_CHECK_OFF, + .tag_op =3D TAG_OP_ALL, .enable_tco =3D false, }, { @@ -471,6 +540,7 @@ int main(int argc, char *argv[]) .mapping =3D MAP_PRIVATE, .tag_check =3D TAG_CHECK_ON, .atag_check =3D ATAG_CHECK_OFF, + .tag_op =3D TAG_OP_ALL, .enable_tco =3D false, }, { @@ -480,6 +550,7 @@ int main(int argc, char *argv[]) .mapping =3D MAP_SHARED, .tag_check =3D TAG_CHECK_ON, .atag_check =3D ATAG_CHECK_OFF, + .tag_op =3D TAG_OP_ALL, .enable_tco =3D false, }, { @@ -489,6 +560,7 @@ int main(int argc, char *argv[]) .mapping =3D MAP_SHARED, .tag_check =3D TAG_CHECK_ON, .atag_check =3D ATAG_CHECK_OFF, + .tag_op =3D TAG_OP_ALL, .enable_tco =3D false, }, { @@ -498,6 +570,7 @@ int main(int argc, char *argv[]) .mapping =3D MAP_PRIVATE, .tag_check =3D TAG_CHECK_ON, .atag_check =3D ATAG_CHECK_OFF, + .tag_op =3D TAG_OP_ALL, .enable_tco =3D false, }, { @@ -507,6 +580,257 @@ int main(int argc, char *argv[]) .mapping =3D MAP_PRIVATE, .tag_check =3D TAG_CHECK_ON, .atag_check =3D ATAG_CHECK_OFF, + .tag_op =3D TAG_OP_ALL, + .enable_tco =3D false, + }, + { + .check_type =3D CHECK_ANON_MEM, + .mem_type =3D USE_MMAP, + .mte_sync =3D MTE_SYNC_ERR, + .mapping =3D MAP_PRIVATE, + .tag_check =3D TAG_CHECK_ON, + .atag_check =3D ATAG_CHECK_ON, + .tag_op =3D TAG_OP_ALL, + .enable_tco =3D false, + }, + { + .check_type =3D CHECK_ANON_MEM, + .mem_type =3D USE_MPROTECT, + .mte_sync =3D MTE_SYNC_ERR, + .mapping =3D MAP_PRIVATE, + .tag_check =3D TAG_CHECK_ON, + .atag_check =3D ATAG_CHECK_ON, + .tag_op =3D TAG_OP_ALL, + .enable_tco =3D false, + }, + { + .check_type =3D CHECK_ANON_MEM, + .mem_type =3D USE_MMAP, + .mte_sync =3D MTE_SYNC_ERR, + .mapping =3D MAP_SHARED, + .tag_check =3D TAG_CHECK_ON, + .atag_check =3D ATAG_CHECK_ON, + .tag_op =3D TAG_OP_ALL, + .enable_tco =3D false, + }, + { + .check_type =3D CHECK_ANON_MEM, + .mem_type =3D USE_MPROTECT, + .mte_sync =3D MTE_SYNC_ERR, + .mapping =3D MAP_SHARED, + .tag_check =3D TAG_CHECK_ON, + .atag_check =3D ATAG_CHECK_ON, + .tag_op =3D TAG_OP_ALL, + .enable_tco =3D false, + }, + { + .check_type =3D CHECK_FILE_MEM, + .mem_type =3D USE_MMAP, + .mte_sync =3D MTE_SYNC_ERR, + .mapping =3D MAP_PRIVATE, + .tag_check =3D TAG_CHECK_ON, + .atag_check =3D ATAG_CHECK_ON, + .tag_op =3D TAG_OP_ALL, + .enable_tco =3D false, + }, + { + .check_type =3D CHECK_FILE_MEM, + .mem_type =3D USE_MPROTECT, + .mte_sync =3D MTE_SYNC_ERR, + .mapping =3D MAP_PRIVATE, + .tag_check =3D TAG_CHECK_ON, + .atag_check =3D ATAG_CHECK_ON, + .tag_op =3D TAG_OP_ALL, + .enable_tco =3D false, + }, + { + .check_type =3D CHECK_FILE_MEM, + .mem_type =3D USE_MMAP, + .mte_sync =3D MTE_SYNC_ERR, + .mapping =3D MAP_SHARED, + .tag_check =3D TAG_CHECK_ON, + .atag_check =3D ATAG_CHECK_ON, + .tag_op =3D TAG_OP_ALL, + .enable_tco =3D false, + }, + { + .check_type =3D CHECK_FILE_MEM, + .mem_type =3D USE_MPROTECT, + .mte_sync =3D MTE_SYNC_ERR, + .mapping =3D MAP_SHARED, + .tag_check =3D TAG_CHECK_ON, + .atag_check =3D ATAG_CHECK_ON, + .tag_op =3D TAG_OP_ALL, + .enable_tco =3D false, + }, + { + .check_type =3D CHECK_FILE_MEM, + .mem_type =3D USE_MMAP, + .mte_sync =3D MTE_ASYNC_ERR, + .mapping =3D MAP_PRIVATE, + .tag_check =3D TAG_CHECK_ON, + .atag_check =3D ATAG_CHECK_ON, + .tag_op =3D TAG_OP_ALL, + .enable_tco =3D false, + }, + { + .check_type =3D CHECK_ANON_MEM, + .mem_type =3D USE_MMAP, + .mte_sync =3D MTE_SYNC_ERR, + .mapping =3D MAP_PRIVATE, + .tag_check =3D TAG_CHECK_ON, + .atag_check =3D ATAG_CHECK_OFF, + .tag_op =3D TAG_OP_STONLY, + .enable_tco =3D false, + }, + { + .check_type =3D CHECK_ANON_MEM, + .mem_type =3D USE_MPROTECT, + .mte_sync =3D MTE_SYNC_ERR, + .mapping =3D MAP_PRIVATE, + .tag_check =3D TAG_CHECK_ON, + .atag_check =3D ATAG_CHECK_OFF, + .tag_op =3D TAG_OP_STONLY, + .enable_tco =3D false, + }, + { + .check_type =3D CHECK_ANON_MEM, + .mem_type =3D USE_MMAP, + .mte_sync =3D MTE_SYNC_ERR, + .mapping =3D MAP_SHARED, + .tag_check =3D TAG_CHECK_ON, + .atag_check =3D ATAG_CHECK_OFF, + .tag_op =3D TAG_OP_STONLY, + .enable_tco =3D false, + }, + { + .check_type =3D CHECK_ANON_MEM, + .mem_type =3D USE_MPROTECT, + .mte_sync =3D MTE_SYNC_ERR, + .mapping =3D MAP_SHARED, + .tag_check =3D TAG_CHECK_ON, + .atag_check =3D ATAG_CHECK_OFF, + .tag_op =3D TAG_OP_STONLY, + .enable_tco =3D false, + }, + { + .check_type =3D CHECK_ANON_MEM, + .mem_type =3D USE_MMAP, + .mte_sync =3D MTE_ASYNC_ERR, + .mapping =3D MAP_PRIVATE, + .tag_check =3D TAG_CHECK_ON, + .atag_check =3D ATAG_CHECK_OFF, + .tag_op =3D TAG_OP_STONLY, + .enable_tco =3D false, + }, + { + .check_type =3D CHECK_ANON_MEM, + .mem_type =3D USE_MPROTECT, + .mte_sync =3D MTE_ASYNC_ERR, + .mapping =3D MAP_PRIVATE, + .tag_check =3D TAG_CHECK_ON, + .atag_check =3D ATAG_CHECK_OFF, + .tag_op =3D TAG_OP_STONLY, + .enable_tco =3D false, + }, + { + .check_type =3D CHECK_ANON_MEM, + .mem_type =3D USE_MMAP, + .mte_sync =3D MTE_ASYNC_ERR, + .mapping =3D MAP_SHARED, + .tag_check =3D TAG_CHECK_ON, + .atag_check =3D ATAG_CHECK_OFF, + .tag_op =3D TAG_OP_STONLY, + .enable_tco =3D false, + }, + { + .check_type =3D CHECK_ANON_MEM, + .mem_type =3D USE_MPROTECT, + .mte_sync =3D MTE_ASYNC_ERR, + .mapping =3D MAP_SHARED, + .tag_check =3D TAG_CHECK_ON, + .atag_check =3D ATAG_CHECK_OFF, + .tag_op =3D TAG_OP_STONLY, + .enable_tco =3D false, + }, + { + .check_type =3D CHECK_FILE_MEM, + .mem_type =3D USE_MMAP, + .mte_sync =3D MTE_SYNC_ERR, + .mapping =3D MAP_PRIVATE, + .tag_check =3D TAG_CHECK_ON, + .atag_check =3D ATAG_CHECK_OFF, + .tag_op =3D TAG_OP_STONLY, + .enable_tco =3D false, + }, + { + .check_type =3D CHECK_FILE_MEM, + .mem_type =3D USE_MPROTECT, + .mte_sync =3D MTE_SYNC_ERR, + .mapping =3D MAP_PRIVATE, + .tag_check =3D TAG_CHECK_ON, + .atag_check =3D ATAG_CHECK_OFF, + .tag_op =3D TAG_OP_STONLY, + .enable_tco =3D false, + }, + { + .check_type =3D CHECK_FILE_MEM, + .mem_type =3D USE_MMAP, + .mte_sync =3D MTE_SYNC_ERR, + .mapping =3D MAP_SHARED, + .tag_check =3D TAG_CHECK_ON, + .atag_check =3D ATAG_CHECK_OFF, + .tag_op =3D TAG_OP_STONLY, + .enable_tco =3D false, + }, + { + .check_type =3D CHECK_FILE_MEM, + .mem_type =3D USE_MPROTECT, + .mte_sync =3D MTE_SYNC_ERR, + .mapping =3D MAP_SHARED, + .tag_check =3D TAG_CHECK_ON, + .atag_check =3D ATAG_CHECK_OFF, + .tag_op =3D TAG_OP_STONLY, + .enable_tco =3D false, + }, + { + .check_type =3D CHECK_FILE_MEM, + .mem_type =3D USE_MMAP, + .mte_sync =3D MTE_ASYNC_ERR, + .mapping =3D MAP_PRIVATE, + .tag_check =3D TAG_CHECK_ON, + .atag_check =3D ATAG_CHECK_OFF, + .tag_op =3D TAG_OP_STONLY, + .enable_tco =3D false, + }, + { + .check_type =3D CHECK_FILE_MEM, + .mem_type =3D USE_MPROTECT, + .mte_sync =3D MTE_ASYNC_ERR, + .mapping =3D MAP_PRIVATE, + .tag_check =3D TAG_CHECK_ON, + .atag_check =3D ATAG_CHECK_OFF, + .tag_op =3D TAG_OP_STONLY, + .enable_tco =3D false, + }, + { + .check_type =3D CHECK_FILE_MEM, + .mem_type =3D USE_MMAP, + .mte_sync =3D MTE_ASYNC_ERR, + .mapping =3D MAP_SHARED, + .tag_check =3D TAG_CHECK_ON, + .atag_check =3D ATAG_CHECK_OFF, + .tag_op =3D TAG_OP_STONLY, + .enable_tco =3D false, + }, + { + .check_type =3D CHECK_FILE_MEM, + .mem_type =3D USE_MPROTECT, + .mte_sync =3D MTE_ASYNC_ERR, + .mapping =3D MAP_SHARED, + .tag_check =3D TAG_CHECK_ON, + .atag_check =3D ATAG_CHECK_OFF, + .tag_op =3D TAG_OP_STONLY, .enable_tco =3D false, }, { @@ -516,6 +840,7 @@ int main(int argc, char *argv[]) .mapping =3D MAP_PRIVATE, .tag_check =3D TAG_CHECK_ON, .atag_check =3D ATAG_CHECK_ON, + .tag_op =3D TAG_OP_STONLY, .enable_tco =3D false, }, { @@ -525,6 +850,7 @@ int main(int argc, char *argv[]) .mapping =3D MAP_PRIVATE, .tag_check =3D TAG_CHECK_ON, .atag_check =3D ATAG_CHECK_ON, + .tag_op =3D TAG_OP_STONLY, .enable_tco =3D false, }, { @@ -534,6 +860,7 @@ int main(int argc, char *argv[]) .mapping =3D MAP_SHARED, .tag_check =3D TAG_CHECK_ON, .atag_check =3D ATAG_CHECK_ON, + .tag_op =3D TAG_OP_STONLY, .enable_tco =3D false, }, { @@ -543,6 +870,7 @@ int main(int argc, char *argv[]) .mapping =3D MAP_SHARED, .tag_check =3D TAG_CHECK_ON, .atag_check =3D ATAG_CHECK_ON, + .tag_op =3D TAG_OP_STONLY, .enable_tco =3D false, }, { @@ -552,6 +880,7 @@ int main(int argc, char *argv[]) .mapping =3D MAP_PRIVATE, .tag_check =3D TAG_CHECK_ON, .atag_check =3D ATAG_CHECK_ON, + .tag_op =3D TAG_OP_STONLY, .enable_tco =3D false, }, { @@ -561,6 +890,7 @@ int main(int argc, char *argv[]) .mapping =3D MAP_PRIVATE, .tag_check =3D TAG_CHECK_ON, .atag_check =3D ATAG_CHECK_ON, + .tag_op =3D TAG_OP_STONLY, .enable_tco =3D false, }, { @@ -570,6 +900,7 @@ int main(int argc, char *argv[]) .mapping =3D MAP_SHARED, .tag_check =3D TAG_CHECK_ON, .atag_check =3D ATAG_CHECK_ON, + .tag_op =3D TAG_OP_STONLY, .enable_tco =3D false, }, { @@ -579,6 +910,7 @@ int main(int argc, char *argv[]) .mapping =3D MAP_SHARED, .tag_check =3D TAG_CHECK_ON, .atag_check =3D ATAG_CHECK_ON, + .tag_op =3D TAG_OP_STONLY, .enable_tco =3D false, }, { @@ -588,6 +920,7 @@ int main(int argc, char *argv[]) .mapping =3D MAP_PRIVATE, .tag_check =3D TAG_CHECK_ON, .atag_check =3D ATAG_CHECK_ON, + .tag_op =3D TAG_OP_STONLY, .enable_tco =3D false, }, { @@ -597,6 +930,7 @@ int main(int argc, char *argv[]) .mapping =3D MAP_PRIVATE, .tag_check =3D TAG_CHECK_ON, .atag_check =3D ATAG_CHECK_ON, + .tag_op =3D TAG_OP_ALL, .enable_tco =3D false, }, { @@ -606,6 +940,7 @@ int main(int argc, char *argv[]) .mapping =3D MAP_PRIVATE, .tag_check =3D TAG_CHECK_ON, .atag_check =3D ATAG_CHECK_ON, + .tag_op =3D TAG_OP_ALL, .enable_tco =3D false, }, }; @@ -643,7 +978,8 @@ int main(int argc, char *argv[]) test_cases[i].mte_sync, test_cases[i].mapping, test_cases[i].tag_check, - test_cases[i].atag_check), + test_cases[i].atag_check, + test_cases[i].tag_op), format_test_name(&test_cases[i])); break; case CHECK_FILE_MEM: @@ -651,7 +987,8 @@ int main(int argc, char *argv[]) test_cases[i].mte_sync, test_cases[i].mapping, test_cases[i].tag_check, - test_cases[i].atag_check), + test_cases[i].atag_check, + test_cases[i].tag_op), format_test_name(&test_cases[i])); break; case CHECK_CLEAR_PROT_MTE: diff --git a/tools/testing/selftests/arm64/mte/check_prctl.c b/tools/testin= g/selftests/arm64/mte/check_prctl.c index 4c89e9538ca0..e9ad8761b3fb 100644 --- a/tools/testing/selftests/arm64/mte/check_prctl.c +++ b/tools/testing/selftests/arm64/mte/check_prctl.c @@ -60,7 +60,7 @@ void check_basic_read(void) /* * Attempt to set a specified combination of modes. */ -void set_mode_test(const char *name, int hwcap2, int mask) +void set_mode_test(const char *name, int hwcap2, int hwcap3, int mask) { int ret; =20 @@ -69,6 +69,11 @@ void set_mode_test(const char *name, int hwcap2, int mas= k) return; } =20 + if ((getauxval(AT_HWCAP3) & hwcap3) !=3D hwcap3) { + ksft_test_result_skip("%s\n", name); + return; + } + ret =3D set_tagged_addr_ctrl(mask); if (ret < 0) { ksft_test_result_fail("%s\n", name); @@ -81,7 +86,7 @@ void set_mode_test(const char *name, int hwcap2, int mask) return; } =20 - if ((ret & PR_MTE_TCF_MASK) =3D=3D mask) { + if ((ret & (PR_MTE_TCF_MASK | PR_MTE_STORE_ONLY)) =3D=3D mask) { ksft_test_result_pass("%s\n", name); } else { ksft_print_msg("Got %x, expected %x\n", @@ -93,12 +98,16 @@ void set_mode_test(const char *name, int hwcap2, int ma= sk) struct mte_mode { int mask; int hwcap2; + int hwcap3; const char *name; } mte_modes[] =3D { - { PR_MTE_TCF_NONE, 0, "NONE" }, - { PR_MTE_TCF_SYNC, HWCAP2_MTE, "SYNC" }, - { PR_MTE_TCF_ASYNC, HWCAP2_MTE, "ASYNC" }, - { PR_MTE_TCF_SYNC | PR_MTE_TCF_ASYNC, HWCAP2_MTE, "SYNC+ASYNC" }, + { PR_MTE_TCF_NONE, 0, 0, = "NONE" }, + { PR_MTE_TCF_SYNC, HWCAP2_MTE, 0, = "SYNC" }, + { PR_MTE_TCF_ASYNC, HWCAP2_MTE, 0, = "ASYNC" }, + { PR_MTE_TCF_SYNC | PR_MTE_TCF_ASYNC, HWCAP2_MTE, 0, = "SYNC+ASYNC" }, + { PR_MTE_TCF_SYNC | PR_MTE_STORE_ONLY, HWCAP2_MTE, HWC= AP3_MTE_STORE_ONLY, "SYNC+STONLY" }, + { PR_MTE_TCF_ASYNC | PR_MTE_STORE_ONLY, HWCAP2_MTE, HWC= AP3_MTE_STORE_ONLY, "ASYNC+STONLY" }, + { PR_MTE_TCF_SYNC | PR_MTE_TCF_ASYNC | PR_MTE_STORE_ONLY, HWCAP2_MTE, HWC= AP3_MTE_STORE_ONLY, "SYNC+ASYNC+STONLY" }, }; =20 int main(void) @@ -106,11 +115,11 @@ int main(void) int i; =20 ksft_print_header(); - ksft_set_plan(5); + ksft_set_plan(ARRAY_SIZE(mte_modes)); =20 check_basic_read(); for (i =3D 0; i < ARRAY_SIZE(mte_modes); i++) - set_mode_test(mte_modes[i].name, mte_modes[i].hwcap2, + set_mode_test(mte_modes[i].name, mte_modes[i].hwcap2, mte_modes[i].hwcap= 3, mte_modes[i].mask); =20 ksft_print_cnts(); --=20 LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7}