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charset="utf-8" For Qualcomm SoCs which needs level shifter for SD card, extra delay is seen on receiver data path. To compensate this delay enable tuning for SDR50 mode for targets which has level shifter. SDHCI_SDR50_NEEDS_TUNING caps will be set for targets with level shifter on Qualcomm SOC's. Signed-off-by: Sarthak Garg Acked-by: Adrian Hunter --- drivers/mmc/host/sdhci-msm.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index 66c0d1ba2a33..bf91cb96a0ea 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -81,6 +81,7 @@ #define CORE_IO_PAD_PWR_SWITCH_EN BIT(15) #define CORE_IO_PAD_PWR_SWITCH BIT(16) #define CORE_HC_SELECT_IN_EN BIT(18) +#define CORE_HC_SELECT_IN_SDR50 (4 << 19) #define CORE_HC_SELECT_IN_HS400 (6 << 19) #define CORE_HC_SELECT_IN_MASK (7 << 19) =20 @@ -1133,6 +1134,10 @@ static bool sdhci_msm_is_tuning_needed(struct sdhci_= host *host) { struct mmc_ios *ios =3D &host->mmc->ios; =20 + if (ios->timing =3D=3D MMC_TIMING_UHS_SDR50 && + host->flags & SDHCI_SDR50_NEEDS_TUNING) + return true; + /* * Tuning is required for SDR104, HS200 and HS400 cards and * if clock frequency is greater than 100MHz in these modes. @@ -1201,6 +1206,8 @@ static int sdhci_msm_execute_tuning(struct mmc_host *= mmc, u32 opcode) struct mmc_ios ios =3D host->mmc->ios; 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charset="utf-8" Introduce a new optional device tree property `max-sd-hs-frequency` to limit the maximum frequency (in Hz) used for SD cards operating in High-Speed (HS) mode. This property is useful for platforms with vendor-specific hardware constraints, such as the presence of a level shifter that cannot reliably support the default 50 MHz HS frequency. It allows the host driver to cap the HS mode frequency accordingly. Signed-off-by: Sarthak Garg --- .../devicetree/bindings/mmc/mmc-controller-common.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/mmc-controller-common.ya= ml b/Documentation/devicetree/bindings/mmc/mmc-controller-common.yaml index 9a7235439759..1976f5f8c401 100644 --- a/Documentation/devicetree/bindings/mmc/mmc-controller-common.yaml +++ b/Documentation/devicetree/bindings/mmc/mmc-controller-common.yaml @@ -93,6 +93,16 @@ properties: minimum: 400000 maximum: 384000000 =20 + max-sd-hs-frequency: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Maximum frequency (in Hz) to be used for SD cards operating in + High-Speed (HS) mode. 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charset="utf-8" Introduce a new device tree flag to cap the maximum High-Speed (HS) mode frequency for SD cards, accommodating vendor-specific constraints such as the inclusion of a level shifter which cannot support the default 50Mhz HS frequency and others. Signed-off-by: Sarthak Garg --- drivers/mmc/core/host.c | 2 ++ drivers/mmc/core/sd.c | 2 +- include/linux/mmc/host.h | 1 + 3 files changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/core/host.c b/drivers/mmc/core/host.c index dacb5bd9bb71..7892e80bc073 100644 --- a/drivers/mmc/core/host.c +++ b/drivers/mmc/core/host.c @@ -302,6 +302,8 @@ int mmc_of_parse(struct mmc_host *host) /* f_max is obtained from the optional "max-frequency" property */ device_property_read_u32(dev, "max-frequency", &host->f_max); =20 + device_property_read_u32(dev, "max-sd-hs-frequency", &host->max_sd_hs_fre= q); + /* * Configure CD and WP pins. They are both by default active low to * match the SDHCI spec. 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charset="utf-8" Kernel now handles all level shifter limitations related to SD card modes. As a result, the broken hardware capabilities for SDR104 and SDR50 modes can be removed from the device tree. Additionally, due to level shifter constraints, set the maximum frequency for High Speed (HS) mode to 37.5 MHz using the max-sd-hs-frequency property for sm8550. Signed-off-by: Sarthak Garg --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qco= m/sm8550.dtsi index 82cabf777cd2..2c770c979d39 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -3180,6 +3180,7 @@ sdhc_2: mmc@8804000 { iommus =3D <&apps_smmu 0x540 0>; qcom,dll-config =3D <0x0007642c>; qcom,ddr-config =3D <0x80040868>; + max-sd-hs-frequency =3D <37500000>; power-domains =3D <&rpmhpd RPMHPD_CX>; operating-points-v2 =3D <&sdhc2_opp_table>; =20 @@ -3191,9 +3192,6 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, bus-width =3D <4>; dma-coherent; =20 - /* Forbid SDR104/SDR50 - broken hw! */ - sdhci-caps-mask =3D <0x3 0>; - status =3D "disabled"; =20 sdhc2_opp_table: opp-table { --=20 2.34.1