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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Jun 2025 06:56:03.2400 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e9239471-1f9b-47d4-91b1-08ddae3530e0 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044F9.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH1PR12MB9597 Content-Type: text/plain; charset="utf-8" From: Ankit Agrawal Fixes a security bug due to mismatched attributes between S1 and S2 mapping. Currently, it is possible for a region to be cacheable in the userspace VMA, but mapped non cached in S2. This creates a potential issue where the VMM may sanitize cacheable memory across VMs using cacheable stores, ensuring it is zeroed. However, if KVM subsequently assigns this memory to a VM as uncached, the VM could end up accessing stale, non-zeroed data from a previous VM, leading to unintended data exposure. This is a security risk. Block such mismatch attributes case by returning EINVAL when userspace try to map PFNMAP cacheable. Only allow NORMAL_NC and DEVICE_*. CC: Oliver Upton CC: Sean Christopherson CC: Catalin Marinas Suggested-by: Jason Gunthorpe Signed-off-by: Ankit Agrawal --- arch/arm64/kvm/mmu.c | 34 +++++++++++++++++++++++++++++++++- 1 file changed, 33 insertions(+), 1 deletion(-) diff --git a/arch/arm64/kvm/mmu.c b/arch/arm64/kvm/mmu.c index 3d77a278fc4f..d6e0d5f46b45 100644 --- a/arch/arm64/kvm/mmu.c +++ b/arch/arm64/kvm/mmu.c @@ -1470,6 +1470,22 @@ static bool kvm_vma_mte_allowed(struct vm_area_struc= t *vma) return vma->vm_flags & VM_MTE_ALLOWED; } =20 +/* + * Determine the memory region cacheability from VMA's pgprot. This + * is used to set the stage 2 PTEs. + */ +static bool kvm_vma_is_cacheable(struct vm_area_struct *vma) +{ + switch (FIELD_GET(PTE_ATTRINDX_MASK, pgprot_val(vma->vm_page_prot))) { + case MT_NORMAL_NC: + case MT_DEVICE_nGnRnE: + case MT_DEVICE_nGnRE: + return false; + default: + return true; + } +} + static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa, struct kvm_s2_trans *nested, struct kvm_memory_slot *memslot, unsigned long hva, @@ -1477,7 +1493,7 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys= _addr_t fault_ipa, { int ret =3D 0; bool write_fault, writable, force_pte =3D false; - bool exec_fault, mte_allowed; + bool exec_fault, mte_allowed, is_vma_cacheable =3D false; bool disable_cmo =3D false, vfio_allow_any_uc =3D false; unsigned long mmu_seq; phys_addr_t ipa =3D fault_ipa; @@ -1619,6 +1635,8 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys= _addr_t fault_ipa, =20 vfio_allow_any_uc =3D vma->vm_flags & VM_ALLOW_ANY_UNCACHED; =20 + is_vma_cacheable =3D kvm_vma_is_cacheable(vma); + /* Don't use the VMA after the unlock -- it may have vanished */ vma =3D NULL; =20 @@ -1643,6 +1661,9 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys= _addr_t fault_ipa, return -EFAULT; =20 if (!kvm_can_use_cmo_pfn(pfn)) { + if (is_vma_cacheable) + return -EINVAL; + /* * If the page was identified as device early by looking at * the VMA flags, vma_pagesize is already representing the @@ -1726,6 +1747,11 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phy= s_addr_t fault_ipa, prot |=3D KVM_PGTABLE_PROT_X; =20 if (disable_cmo) { + if (is_vma_cacheable) { + ret =3D -EINVAL; + goto out_unlock; + } + if (vfio_allow_any_uc) prot |=3D KVM_PGTABLE_PROT_NORMAL_NC; else @@ -2221,6 +2247,12 @@ int kvm_arch_prepare_memory_region(struct kvm *kvm, ret =3D -EINVAL; break; } + + /* Cacheable PFNMAP is not allowed */ + if (kvm_vma_is_cacheable(vma)) { + ret =3D -EINVAL; + break; + } } hva =3D min(reg_end, vma->vm_end); } while (hva < reg_end); --=20 2.34.1