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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Jun 2025 06:55:58.9356 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c17aa5cc-2fd0-4306-abe1-08ddae352e4f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF000015CB.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB5783 Content-Type: text/plain; charset="utf-8" From: Ankit Agrawal Currently, the kvm_is_device_pfn() detects if the memory is kernel mapped. It thus implies whether KVM can use Cache Maintenance Operations (CMOs) on that PFN. Rename the function to reflect this. Additionally, the "device" variable is effectively trying to setup the S2 to prevent CMOs. Calling it 'disable_cmo' would make this code clearer. Suggested-by: Jason Gunthorpe Signed-off-by: Ankit Agrawal --- arch/arm64/kvm/mmu.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm64/kvm/mmu.c b/arch/arm64/kvm/mmu.c index 2942ec92c5a4..3d77a278fc4f 100644 --- a/arch/arm64/kvm/mmu.c +++ b/arch/arm64/kvm/mmu.c @@ -193,9 +193,9 @@ int kvm_arch_flush_remote_tlbs_range(struct kvm *kvm, return 0; } =20 -static bool kvm_is_device_pfn(unsigned long pfn) +static bool kvm_can_use_cmo_pfn(unsigned long pfn) { - return !pfn_is_map_memory(pfn); + return pfn_is_map_memory(pfn); } =20 static void *stage2_memcache_zalloc_page(void *arg) @@ -1478,7 +1478,7 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys= _addr_t fault_ipa, int ret =3D 0; bool write_fault, writable, force_pte =3D false; bool exec_fault, mte_allowed; - bool device =3D false, vfio_allow_any_uc =3D false; + bool disable_cmo =3D false, vfio_allow_any_uc =3D false; unsigned long mmu_seq; phys_addr_t ipa =3D fault_ipa; struct kvm *kvm =3D vcpu->kvm; @@ -1642,7 +1642,7 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys= _addr_t fault_ipa, if (is_error_noslot_pfn(pfn)) return -EFAULT; =20 - if (kvm_is_device_pfn(pfn)) { + if (!kvm_can_use_cmo_pfn(pfn)) { /* * If the page was identified as device early by looking at * the VMA flags, vma_pagesize is already representing the @@ -1653,7 +1653,7 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys= _addr_t fault_ipa, * In both cases, we don't let transparent_hugepage_adjust() * change things at the last minute. */ - device =3D true; + disable_cmo =3D true; } else if (logging_active && !write_fault) { /* * Only actually map the page as writable if this was a write @@ -1662,7 +1662,7 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys= _addr_t fault_ipa, writable =3D false; } =20 - if (exec_fault && device) + if (exec_fault && disable_cmo) return -ENOEXEC; =20 /* @@ -1695,7 +1695,7 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys= _addr_t fault_ipa, * If we are not forced to use page mapping, check if we are * backed by a THP and thus use block mapping if possible. */ - if (vma_pagesize =3D=3D PAGE_SIZE && !(force_pte || device)) { + if (vma_pagesize =3D=3D PAGE_SIZE && !(force_pte || disable_cmo)) { if (fault_is_perm && fault_granule > PAGE_SIZE) vma_pagesize =3D fault_granule; else @@ -1709,7 +1709,7 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys= _addr_t fault_ipa, } } =20 - if (!fault_is_perm && !device && kvm_has_mte(kvm)) { + if (!fault_is_perm && !disable_cmo && kvm_has_mte(kvm)) { /* Check the VMM hasn't introduced a new disallowed VMA */ if (mte_allowed) { sanitise_mte_tags(kvm, pfn, vma_pagesize); @@ -1725,7 +1725,7 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys= _addr_t fault_ipa, if (exec_fault) prot |=3D KVM_PGTABLE_PROT_X; =20 - if (device) { + if (disable_cmo) { if (vfio_allow_any_uc) prot |=3D KVM_PGTABLE_PROT_NORMAL_NC; else --=20 2.34.1 From nobody Thu Oct 9 10:42:44 2025 Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on2062.outbound.protection.outlook.com [40.107.236.62]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D5F88258CE9 for ; Wed, 18 Jun 2025 06:56:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Jun 2025 06:56:03.2400 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e9239471-1f9b-47d4-91b1-08ddae3530e0 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044F9.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH1PR12MB9597 Content-Type: text/plain; charset="utf-8" From: Ankit Agrawal Fixes a security bug due to mismatched attributes between S1 and S2 mapping. Currently, it is possible for a region to be cacheable in the userspace VMA, but mapped non cached in S2. This creates a potential issue where the VMM may sanitize cacheable memory across VMs using cacheable stores, ensuring it is zeroed. However, if KVM subsequently assigns this memory to a VM as uncached, the VM could end up accessing stale, non-zeroed data from a previous VM, leading to unintended data exposure. This is a security risk. Block such mismatch attributes case by returning EINVAL when userspace try to map PFNMAP cacheable. Only allow NORMAL_NC and DEVICE_*. CC: Oliver Upton CC: Sean Christopherson CC: Catalin Marinas Suggested-by: Jason Gunthorpe Signed-off-by: Ankit Agrawal --- arch/arm64/kvm/mmu.c | 34 +++++++++++++++++++++++++++++++++- 1 file changed, 33 insertions(+), 1 deletion(-) diff --git a/arch/arm64/kvm/mmu.c b/arch/arm64/kvm/mmu.c index 3d77a278fc4f..d6e0d5f46b45 100644 --- a/arch/arm64/kvm/mmu.c +++ b/arch/arm64/kvm/mmu.c @@ -1470,6 +1470,22 @@ static bool kvm_vma_mte_allowed(struct vm_area_struc= t *vma) return vma->vm_flags & VM_MTE_ALLOWED; } =20 +/* + * Determine the memory region cacheability from VMA's pgprot. This + * is used to set the stage 2 PTEs. + */ +static bool kvm_vma_is_cacheable(struct vm_area_struct *vma) +{ + switch (FIELD_GET(PTE_ATTRINDX_MASK, pgprot_val(vma->vm_page_prot))) { + case MT_NORMAL_NC: + case MT_DEVICE_nGnRnE: + case MT_DEVICE_nGnRE: + return false; + default: + return true; + } +} + static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa, struct kvm_s2_trans *nested, struct kvm_memory_slot *memslot, unsigned long hva, @@ -1477,7 +1493,7 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys= _addr_t fault_ipa, { int ret =3D 0; bool write_fault, writable, force_pte =3D false; - bool exec_fault, mte_allowed; + bool exec_fault, mte_allowed, is_vma_cacheable =3D false; bool disable_cmo =3D false, vfio_allow_any_uc =3D false; unsigned long mmu_seq; phys_addr_t ipa =3D fault_ipa; @@ -1619,6 +1635,8 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys= _addr_t fault_ipa, =20 vfio_allow_any_uc =3D vma->vm_flags & VM_ALLOW_ANY_UNCACHED; =20 + is_vma_cacheable =3D kvm_vma_is_cacheable(vma); + /* Don't use the VMA after the unlock -- it may have vanished */ vma =3D NULL; =20 @@ -1643,6 +1661,9 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys= _addr_t fault_ipa, return -EFAULT; =20 if (!kvm_can_use_cmo_pfn(pfn)) { + if (is_vma_cacheable) + return -EINVAL; + /* * If the page was identified as device early by looking at * the VMA flags, vma_pagesize is already representing the @@ -1726,6 +1747,11 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phy= s_addr_t fault_ipa, prot |=3D KVM_PGTABLE_PROT_X; =20 if (disable_cmo) { + if (is_vma_cacheable) { + ret =3D -EINVAL; + goto out_unlock; + } + if (vfio_allow_any_uc) prot |=3D KVM_PGTABLE_PROT_NORMAL_NC; else @@ -2221,6 +2247,12 @@ int kvm_arch_prepare_memory_region(struct kvm *kvm, ret =3D -EINVAL; break; } + + /* Cacheable PFNMAP is not allowed */ + if (kvm_vma_is_cacheable(vma)) { + ret =3D -EINVAL; + break; + } } hva =3D min(reg_end, vma->vm_end); } while (hva < reg_end); --=20 2.34.1 From nobody Thu Oct 9 10:42:44 2025 Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on2080.outbound.protection.outlook.com [40.107.236.80]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2E68425A32E for ; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Jun 2025 06:56:05.6152 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a60176e6-6ee8-4283-06b0-08ddae35324b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044F9.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5747 Content-Type: text/plain; charset="utf-8" From: Ankit Agrawal VM_PFNMAP VMA's are allowed to contain PTE's which point to physical addresses that does not have a struct page and may not be in the kernel direct map. However ARM64 KVM relies on a simple conversion from physaddr to a kernel virtual address when it does cache maintenance as the CMO instructions work on virtual addresses. This simple approach does not work for physical addresses from VM_PFNMAP since those addresses may not have a kernel virtual address, or it may be difficult to find it. Fortunately if the ARM64 CPU has two features, S2FWB and CACHE DIC, then KVM no longer needs to do cache flushing and NOP's all the CMOs. This has the effect of no longer requiring a KVA for addresses mapped into the S2. Add a new function, kvm_arch_supports_cacheable_pfnmap(), to report this capability. From a core prespective it means the arch can accept a cachable VM_PFNMAP as a memslot. From an ARM64 perspective it means that no KVA is required. CC: Jason Gunthorpe CC: David Hildenbrand CC: Donald Dutile Signed-off-by: Ankit Agrawal Reviewed-by: Catalin Marinas --- arch/arm64/kvm/mmu.c | 23 +++++++++++++++++++++++ include/linux/kvm_host.h | 2 ++ virt/kvm/kvm_main.c | 5 +++++ 3 files changed, 30 insertions(+) diff --git a/arch/arm64/kvm/mmu.c b/arch/arm64/kvm/mmu.c index d6e0d5f46b45..a71b77df7c96 100644 --- a/arch/arm64/kvm/mmu.c +++ b/arch/arm64/kvm/mmu.c @@ -1287,6 +1287,29 @@ void kvm_arch_mmu_enable_log_dirty_pt_masked(struct = kvm *kvm, kvm_nested_s2_wp(kvm); } =20 +/** + * kvm_arch_supports_cacheable_pfnmap() - Determine whether hardware + * supports cache management. + * + * ARM64 KVM relies on a simple conversion from physaddr to a kernel + * virtual address (KVA) when it does cache maintenance as the CMO + * instructions work on virtual addresses. This is incompatible with + * VM_PFNMAP VMAs which may not have a kernel direct mapping to a + * virtual address. + * + * With S2FWB and CACHE DIC features, KVM need not do cache flushing + * and CMOs are NOP'd. This has the effect of no longer requiring a + * KVA for addresses mapped into the S2. The presence of these features + * are thus necessary to support cacheable S2 mapping of VM_PFNMAP. + * + * Return: True if FWB and DIC is supported. + */ +bool kvm_arch_supports_cacheable_pfnmap(void) +{ + return cpus_have_final_cap(ARM64_HAS_STAGE2_FWB) && + cpus_have_final_cap(ARM64_HAS_CACHE_DIC); +} + static void kvm_send_hwpoison_signal(unsigned long address, short lsb) { send_sig_mceerr(BUS_MCEERR_AR, (void __user *)address, lsb, current); diff --git a/include/linux/kvm_host.h b/include/linux/kvm_host.h index 3bde4fb5c6aa..c91d5b5f8c39 100644 --- a/include/linux/kvm_host.h +++ b/include/linux/kvm_host.h @@ -1235,6 +1235,8 @@ void kvm_arch_flush_shadow_all(struct kvm *kvm); /* flush memory translations pointing to 'slot' */ void kvm_arch_flush_shadow_memslot(struct kvm *kvm, struct kvm_memory_slot *slot); +/* hardware supports cache management */ +bool kvm_arch_supports_cacheable_pfnmap(void); =20 int kvm_prefetch_pages(struct kvm_memory_slot *slot, gfn_t gfn, struct page **pages, int nr_pages); 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Jun 2025 06:56:07.3237 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 775cec07-d50f-4102-b06e-08ddae35334f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044F6.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4481 Content-Type: text/plain; charset="utf-8" From: Ankit Agrawal Today KVM forces the memory to either NORMAL or DEVICE_nGnRE based on pfn_is_map_memory (which tracks whether the device memory is in the kernel map) and ignores the per-VMA flags that indicates the memory attributes. The KVM code is thus restrictive and allows only for the memory that is added to the kernel to be marked as cacheable. The device memory such as on the Grace Hopper/Blackwell systems is interchangeable with DDR memory and retains properties such as cacheability, unaligned accesses, atomics and handling of executable faults. This requires the device memory to be mapped as NORMAL in stage-2. Given that the GPU device memory is not added to the kernel (but is rather VMA mapped through remap_pfn_range() in nvgrace-gpu module which sets VM_PFNMAP), pfn_is_map_memory() is false and thus KVM prevents such memory to be mapped Normal cacheable. The patch aims to solve this use case. Note when FWB is not enabled, the kernel expects to trivially do cache management by flushing the memory by linearly converting a kvm_pte to phys_addr to a KVA, see kvm_flush_dcache_to_poc(). The cache management thus relies on memory being mapped. Moreover ARM64_HAS_CACHE_DIC CPU cap allows KVM to avoid flushing the icache and turns icache_inval_pou() into a NOP. These two capabilities are thus a requirement of the cacheable PFNMAP feature. Make use of kvm_arch_supports_cacheable_pfnmap() to check them. A cachebility check is made by consulting the VMA pgprot value. If the pgprot mapping type is cacheable, it is safe to be mapped S2 cacheable as the KVM S2 will have the same Normal memory type as the VMA has in the S1 and KVM has no additional responsibility for safety. Checking pgprot as NORMAL is thus a KVM sanity check. Add check for COW VM_PFNMAP and refuse such mapping. No additional checks for MTE are needed as kvm_arch_prepare_memory_region() already tests it at an early stage during memslot creation. There would not even be a fault if the memslot is not created. CC: Oliver Upton CC: Sean Christopherson Suggested-by: Jason Gunthorpe Suggested-by: Catalin Marinas Suggested-by: David Hildenbrand Signed-off-by: Ankit Agrawal --- arch/arm64/kvm/mmu.c | 35 +++++++++++++++++++++++++++++------ 1 file changed, 29 insertions(+), 6 deletions(-) diff --git a/arch/arm64/kvm/mmu.c b/arch/arm64/kvm/mmu.c index a71b77df7c96..6a3955e07b5e 100644 --- a/arch/arm64/kvm/mmu.c +++ b/arch/arm64/kvm/mmu.c @@ -1660,6 +1660,10 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phy= s_addr_t fault_ipa, =20 is_vma_cacheable =3D kvm_vma_is_cacheable(vma); =20 + /* Reject COW VM_PFNMAP */ + if ((vma->vm_flags & VM_PFNMAP) && is_cow_mapping(vma->vm_flags)) + return -EINVAL; + /* Don't use the VMA after the unlock -- it may have vanished */ vma =3D NULL; =20 @@ -1684,9 +1688,6 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys= _addr_t fault_ipa, return -EFAULT; =20 if (!kvm_can_use_cmo_pfn(pfn)) { - if (is_vma_cacheable) - return -EINVAL; - /* * If the page was identified as device early by looking at * the VMA flags, vma_pagesize is already representing the @@ -1696,8 +1697,13 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phy= s_addr_t fault_ipa, * * In both cases, we don't let transparent_hugepage_adjust() * change things at the last minute. + * + * Do not set device as the device memory is cacheable. Note + * that such mapping is safe as the KVM S2 will have the same + * Normal memory type as the VMA has in the S1. */ - disable_cmo =3D true; + if (!is_vma_cacheable) + disable_cmo =3D true; } else if (logging_active && !write_fault) { /* * Only actually map the page as writable if this was a write @@ -1784,6 +1790,19 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phy= s_addr_t fault_ipa, prot |=3D KVM_PGTABLE_PROT_X; } =20 + /* + * When FWB is unsupported KVM needs to do cache flushes + * (via dcache_clean_inval_poc()) of the underlying memory. This is + * only possible if the memory is already mapped into the kernel map. + * + * Outright reject as the cacheable device memory is not present in + * the kernel map and not suitable for cache management. + */ + if (is_vma_cacheable && !kvm_arch_supports_cacheable_pfnmap()) { + ret =3D -EINVAL; + goto out_unlock; + } + /* * Under the premise of getting a FSC_PERM fault, we just need to relax * permissions only if vma_pagesize equals fault_granule. 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Jun 2025 06:56:04.5372 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8dacd5bd-1491-48c4-9f68-08ddae3531ad X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF000015CC.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB7760 Content-Type: text/plain; charset="utf-8" From: Ankit Agrawal Introduce a new KVM capability to expose to the userspace whether cacheable mapping of PFNMAP is supported. The ability to safely do the cacheable mapping of PFNMAP is contingent on S2FWB and ARM64_HAS_CACHE_DIC. S2FWB allows KVM to avoid flushing the D cache, ARM64_HAS_CACHE_DIC allows KVM to avoid flushing the icache and turns icache_inval_pou() into a NOP. The cap would be false if those requirements are missing and is checked by making use of kvm_arch_supports_cacheable_pfnmap. This capability would allow userspace to discover the support. This would be used in conjunction with the KVM_MEM_ENABLE_CACHEABLE_PFNMAP memslot flag. Userspace is required to query this capability before it can set the memslot flag. This cap could also be used by userspace to prevent live-migration across FWB and non-FWB hosts. CC: Catalin Marinas CC: Jason Gunthorpe CC: Oliver Upton CC: David Hildenbrand Suggested-by: Marc Zyngier Signed-off-by: Ankit Agrawal --- Documentation/virt/kvm/api.rst | 13 ++++++++++++- arch/arm64/kvm/arm.c | 7 +++++++ include/uapi/linux/kvm.h | 1 + 3 files changed, 20 insertions(+), 1 deletion(-) diff --git a/Documentation/virt/kvm/api.rst b/Documentation/virt/kvm/api.rst index 1bd2d42e6424..615cdbdd505f 100644 --- a/Documentation/virt/kvm/api.rst +++ b/Documentation/virt/kvm/api.rst @@ -8528,7 +8528,7 @@ ENOSYS for the others. When enabled, KVM will exit to userspace with KVM_EXIT_SYSTEM_EVENT of type KVM_SYSTEM_EVENT_SUSPEND to process the guest suspend request. =20 -7.37 KVM_CAP_ARM_WRITABLE_IMP_ID_REGS +7.42 KVM_CAP_ARM_WRITABLE_IMP_ID_REGS ------------------------------------- =20 :Architectures: arm64 @@ -8557,6 +8557,17 @@ given VM. When this capability is enabled, KVM resets the VCPU when setting MP_STATE_INIT_RECEIVED through IOCTL. The original MP_STATE is preserved. =20 +7.43 KVM_CAP_ARM_CACHEABLE_PFNMAP_SUPPORTED +------------------------------------------- + +:Architectures: arm64 +:Target: VM +:Parameters: None + +This capability indicate to the userspace whether a PFNMAP memory region +can be safely mapped as cacheable. This relies on the presence of +force write back (FWB) feature support on the hardware. + 8. Other capabilities. =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index de2b4e9c9f9f..9fb8901dcd86 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -408,6 +408,13 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long= ext) case KVM_CAP_ARM_SUPPORTED_REG_MASK_RANGES: r =3D BIT(0); break; + case KVM_CAP_ARM_CACHEABLE_PFNMAP_SUPPORTED: + if (!kvm) + r =3D -EINVAL; + else + r =3D kvm_arch_supports_cacheable_pfnmap(); + break; + default: r =3D 0; } diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h index d00b85cb168c..ed9a46875a49 100644 --- a/include/uapi/linux/kvm.h +++ b/include/uapi/linux/kvm.h @@ -934,6 +934,7 @@ struct kvm_enable_cap { #define KVM_CAP_ARM_EL2 240 #define KVM_CAP_ARM_EL2_E2H0 241 #define KVM_CAP_RISCV_MP_STATE_RESET 242 +#define KVM_CAP_ARM_CACHEABLE_PFNMAP_SUPPORTED 243 =20 struct kvm_irq_routing_irqchip { __u32 irqchip; --=20 2.34.1