From nobody Thu Oct 9 11:02:24 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 15D0D2DFF2D; Wed, 18 Jun 2025 10:19:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750241992; cv=none; b=uVRmsDB5na7YaKLQnLWvJY5r7s8B047hvt5lFEZ+7YHX4lOFuHClQIjKytX+6xQAbmQR3c7maUtpRLxHdN6t8iG8ieXqJkBUa60GESUzZHsGvx0FPiVM1KJVhpMLFm5JNO3FDcJRna9rg6840JBGbjzh+WnF6VzUp2+s35Dzi3w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750241992; c=relaxed/simple; bh=Va9KYuR92Ny8pbO7LbUswID7eIVCWK7Q27i68S+Wfe8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=P5CGPj4QPnFec72O45VIj9MkaYVOVXBWWnMRYl5YK03I3vRhkO8CEdAoHcvH9ajbiHn46fhlEVsFW9ZDORyzpoGmhem7zVbi0F90HNYUuvgWe5rLknfKAruKSsJ5t8j1FDs7mb13+YVeQ7wQS+IedB0ePqEF+AfSQSD0BjhUyaQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=OlEetfEQ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="OlEetfEQ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 152B8C4CEF2; Wed, 18 Jun 2025 10:19:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1750241992; bh=Va9KYuR92Ny8pbO7LbUswID7eIVCWK7Q27i68S+Wfe8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=OlEetfEQJw4aCrKp6FQzlBzn3RJaonPtqBfY91YutpTiLWGF+IUBeoYwlI1/dQ7h7 ZEAlQ7Q1mlOr4kIHOnX1OoMlU7BK+0w0WmBoXrCB5n4O1iZbhhBmS3Rt2iv2psFoPT 056YknfpoWrxS1hELqs24f9bA97PRS4AfEsP4B2iCj0QyT05uA+7V+qIANiQQVhxpD 6wUVHMuC/zFB7og7MK00D1wV6KCOXM0CzhMQRLRK3k9HBgXLYIIkmG5EMYqR4q3OBj BjlgC13hrYjl+exXlLPNT56I+pF8/K36kedEoP8hx3ZWydxDOkAmve4gOGkEt4d67k esyLKuo+pPOPQ== From: Lorenzo Pieralisi Date: Wed, 18 Jun 2025 12:17:38 +0200 Subject: [PATCH v5 23/27] irqchip/gic-v5: Enable GICv5 SMP booting Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250618-gicv5-host-v5-23-d9e622ac5539@kernel.org> References: <20250618-gicv5-host-v5-0-d9e622ac5539@kernel.org> In-Reply-To: <20250618-gicv5-host-v5-0-d9e622ac5539@kernel.org> To: Marc Zyngier , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon Cc: Arnd Bergmann , Sascha Bischoff , Jonathan Cameron , Timothy Hayes , Bjorn Helgaas , "Liam R. Howlett" , Peter Maydell , Mark Rutland , Jiri Slaby , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, Lorenzo Pieralisi X-Mailer: b4 0.15-dev-6f78e Set up IPIs by allocating IPI IRQs for all cpus and call into arm64 core code to initialise IPIs IRQ descriptors and request the related IRQ. Implement hotplug callback to enable interrupts on a cpu and register the cpu with an IRS. Co-developed-by: Sascha Bischoff Signed-off-by: Sascha Bischoff Co-developed-by: Timothy Hayes Signed-off-by: Timothy Hayes Signed-off-by: Lorenzo Pieralisi Cc: Thomas Gleixner Cc: Marc Zyngier --- drivers/irqchip/irq-gic-v5.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/irqchip/irq-gic-v5.c b/drivers/irqchip/irq-gic-v5.c index cee29aa750a2..c2e7ba7e38f7 100644 --- a/drivers/irqchip/irq-gic-v5.c +++ b/drivers/irqchip/irq-gic-v5.c @@ -5,6 +5,7 @@ =20 #define pr_fmt(fmt) "GICv5: " fmt =20 +#include #include #include #include @@ -909,6 +910,8 @@ static void gicv5_cpu_enable_interrupts(void) write_sysreg_s(cr0, SYS_ICC_CR0_EL1); } =20 +static int base_ipi_virq; + static int gicv5_starting_cpu(unsigned int cpu) { if (WARN(!gicv5_cpuif_has_gcie(), @@ -920,6 +923,22 @@ static int gicv5_starting_cpu(unsigned int cpu) return gicv5_irs_register_cpu(cpu); } =20 +static void __init gicv5_smp_init(void) +{ + unsigned int num_ipis =3D GICV5_IPIS_PER_CPU * nr_cpu_ids; + + cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_GIC_STARTING, + "irqchip/arm/gicv5:starting", + gicv5_starting_cpu, NULL); + + base_ipi_virq =3D irq_domain_alloc_irqs(gicv5_global_data.ipi_domain, + num_ipis, NUMA_NO_NODE, NULL); + if (WARN(base_ipi_virq <=3D 0, "IPI IRQ allocation was not successful")) + return; + + set_smp_ipi_range_percpu(base_ipi_virq, GICV5_IPIS_PER_CPU, nr_cpu_ids); +} + static void __init gicv5_free_domains(void) { if (gicv5_global_data.ppi_domain) @@ -1041,6 +1060,8 @@ static int __init gicv5_of_init(struct device_node *n= ode, struct device_node *pa if (ret) goto out_int; =20 + gicv5_smp_init(); + return 0; out_int: gicv5_cpu_disable_interrupts(); --=20 2.48.0