From nobody Thu Oct 9 14:04:25 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id BAB7A2EAB9E for ; Tue, 17 Jun 2025 18:36:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750185407; cv=none; b=q9XoYvQCo+ln7FS3KjMnnAOtw0iAnelKlzGwTvV72Q7hrh273MoRNkvKRppMgz3XuNDLvjUa5BKdwpTyw1GmJyOHJcfEGDig1lRZkshi08H7Mn+OIZtD7XhLnISF1lir4Aj3qo7V7PTClMDRCOeuDcBFoFzlen37jgq+1mhlUf4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750185407; c=relaxed/simple; bh=FBL/Yw+hyg6tCVM/ypbqIOIUz4oo8ynHiYmBndj6lho=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=mhkvyw9JHhr9LIKE3ZLfUKJQu5880Wq+qBORGwGO+0J745+OnhFpmZQEyHRXv3MZgC8w6ils/JPl6enyC4cx1Nk6WnJbRVXWfo9e6qbC16IrIY+7dXymdXqQtsG9C5rSGNls2GMkC+xR3jPKxPgcBtVFlYbD7X8PEHSaXPg7fUA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 294DA1BB0; Tue, 17 Jun 2025 11:36:24 -0700 (PDT) Received: from e129823.cambridge.arm.com (e129823.arm.com [10.1.197.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 37E5C3F58B; Tue, 17 Jun 2025 11:36:43 -0700 (PDT) From: Yeoreum Yun To: catalin.marinas@arm.com, will@kernel.org, broonie@kernel.org, oliver.upton@linux.dev, ardb@kernel.org, frederic@kernel.org, james.morse@arm.com, joey.gouly@arm.com, scott@os.amperecomputing.com Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Yeoreum Yun Subject: [PATCH v3 3/7] arm64/Kconfig: add LSUI Kconfig Date: Tue, 17 Jun 2025 19:36:31 +0100 Message-Id: <20250617183635.1266015-4-yeoreum.yun@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250617183635.1266015-1-yeoreum.yun@arm.com> References: <20250617183635.1266015-1-yeoreum.yun@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Since Armv9.6, FEAT_LSUI supplies the load/store instructions for previleged level to access to access user memory without clearing PSTATE.PAN bit. It's enough to add CONFIG_AS_HAS_LSUI only because the code for LUSI uses indiviual `.arch_extension` entries. Signed-off-by: Yeoreum Yun --- arch/arm64/Kconfig | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 55fc331af337..769fbb507996 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -2237,6 +2237,15 @@ config ARM64_GCS =20 endmenu # "v9.4 architectural features" =20 +config AS_HAS_LSUI + def_bool $(as-instr,.arch_extension lsui) + help + Unprivileged Load Store is an extension to introduce unprivileged + variants of load and store instructions so that clearing PSTATE.PAN + is never required in privileged mode. + This feature is available with clang version 20 and later and not yet + supported by gcc. + config ARM64_SVE bool "ARM Scalable Vector Extension support" default y --=20 LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7}