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Tue, 17 Jun 2025 10:19:59 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v2 1/4] arm64: dts: renesas: Add initial SoC DTSI for RZ/N2H SoC Date: Tue, 17 Jun 2025 18:19:54 +0100 Message-ID: <20250617171957.162145-2-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250617171957.162145-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250617171957.162145-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Add initial SoC DTSI for Renesas RZ/N2H ("R9A09G087") SoC, below are the list of blocks added: - EXT CLKs - 4X CA55 - SCIF - CPG - GIC - ARMv8 Timer Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- v1->v2: - Reordered the `l3_ca55` node and renamed it to `L3_CA55` for consistency - Added reviewed-by tag from Geert --- arch/arm64/boot/dts/renesas/r9a09g087.dtsi | 124 +++++++++++++++++++++ 1 file changed, 124 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r9a09g087.dtsi diff --git a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi b/arch/arm64/boot/d= ts/renesas/r9a09g087.dtsi new file mode 100644 index 000000000000..e57a91adcb68 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/N2H SoC + * + * Copyright (C) 2025 Renesas Electronics Corp. + */ + +#include +#include + +/ { + compatible =3D "renesas,r9a09g087"; + #address-cells =3D <2>; + #size-cells =3D <2>; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + compatible =3D "arm,cortex-a55"; + reg =3D <0>; + device_type =3D "cpu"; + next-level-cache =3D <&L3_CA55>; + enable-method =3D "psci"; + }; + + cpu1: cpu@100 { + compatible =3D "arm,cortex-a55"; + reg =3D <0x100>; + device_type =3D "cpu"; + next-level-cache =3D <&L3_CA55>; + enable-method =3D "psci"; + }; + + cpu2: cpu@200 { + compatible =3D "arm,cortex-a55"; + reg =3D <0x200>; + device_type =3D "cpu"; + next-level-cache =3D <&L3_CA55>; + enable-method =3D "psci"; + }; + + cpu3: cpu@300 { + compatible =3D "arm,cortex-a55"; + reg =3D <0x300>; + device_type =3D "cpu"; + next-level-cache =3D <&L3_CA55>; + enable-method =3D "psci"; + }; + + L3_CA55: cache-controller-0 { + compatible =3D "cache"; + cache-unified; + cache-size =3D <0x100000>; + cache-level =3D <3>; + }; + }; + + extal_clk: extal { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + /* This value must be overridden by the board */ + clock-frequency =3D <0>; + }; + + psci { + compatible =3D "arm,psci-1.0", "arm,psci-0.2"; + method =3D "smc"; + }; + + soc: soc { + compatible =3D "simple-bus"; + interrupt-parent =3D <&gic>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + sci0: serial@80005000 { + compatible =3D "renesas,r9a09g087-rsci", "renesas,r9a09g077-rsci"; + reg =3D <0 0x80005000 0 0x400>; + interrupts =3D , + , + , + ; + interrupt-names =3D "eri", "rxi", "txi", "tei"; + clocks =3D <&cpg CPG_MOD 8>, <&cpg CPG_CORE R9A09G087_CLK_PCLKM>; + clock-names =3D "operation", "bus"; + power-domains =3D <&cpg>; + status =3D "disabled"; + }; + + cpg: clock-controller@80280000 { + compatible =3D "renesas,r9a09g087-cpg-mssr"; + reg =3D <0 0x80280000 0 0x1000>, + <0 0x81280000 0 0x9000>; + clocks =3D <&extal_clk>; + clock-names =3D "extal"; + #clock-cells =3D <2>; + #reset-cells =3D <1>; + #power-domain-cells =3D <0>; + }; + + gic: interrupt-controller@83000000 { + compatible =3D "arm,gic-v3"; + reg =3D <0x0 0x83000000 0 0x40000>, + <0x0 0x83040000 0 0x160000>; + #interrupt-cells =3D <3>; + #address-cells =3D <0>; + interrupt-controller; + interrupts =3D ; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts-extended =3D <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; + interrupt-names =3D "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; + }; +}; --=20 2.49.0