From nobody Thu Oct 9 13:45:53 2025 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 893162EBDC0; Tue, 17 Jun 2025 16:25:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750177509; cv=none; b=YZ9IR75ErlhxxJcNUIPQmOHj98phmJKsJCgtjS9nWW63jTtdLdy5MZ7otGB1aeWyAeJ+bHHeSEVcwY6+E7XGAfzBtoXCAg70xBqWQJbEI1V3y9NcwOySiId45GS3wjHIEtZxuEDARLGV77EJpnEF4Dfa1ZZcUAPRtV40v1tOiqI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750177509; c=relaxed/simple; bh=SJImj8DX4cFCxxe5T6hltCyBPxouDRd2XFWmdEWwo2Y=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=p3zy3NruEb1qmmNFcrxhOZBsCb47O/ngRx2NOqwfYm4/5wCqcHM+jfgwxaLV8bTcUw3lyR0jLKQ01R6BFMLiokdfmT5h24AQlpVGNxxgyfZqkuqlkJIdkqJ8bpvyqRwdREAhJXm3FHKLJys9bUExotYmMkJmG6zE8Gra4IkkGCg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org; spf=pass smtp.mailfrom=disroot.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b=Tw6KrqUt; arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="Tw6KrqUt" Received: from mail01.disroot.lan (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id 487F4258DE; Tue, 17 Jun 2025 18:25:06 +0200 (CEST) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id feSf5wsVr4Ax; Tue, 17 Jun 2025 18:25:05 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1750177505; bh=SJImj8DX4cFCxxe5T6hltCyBPxouDRd2XFWmdEWwo2Y=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=Tw6KrqUtPeN4KBbUYImaMiUJzCC55BOFhsF7g7zxMd80+lFQC6e5Ka8vSzJ+NRRlr 3oLzrPBpVvPryn5ypZ121PPlWEWCf1p9MHg23mvZ/s6noipc2seYXyMVt41KvzD3WA NXpj3vHicE07NovaeMrQiylztwUiEMqqduVKz4OMW5e8OuB+aE3m7FYSrSdJjgiQRP FtYoLmRpsH+snlCsvoskk3aiuZp1+0rUzr6U24xRGut399tISA9I2hkCAhvgaWaxS5 tBha1FtB/gvWl/8rVVqWlRCyqYX2ow72yl0+sRzzQDPrJTa9frInRk7znYNiYkeU7/ TZpgiOUF+qwWg== From: Yao Zi To: Yinbo Zhu , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Huacai Chen , WANG Xuerui Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, loongarch@lists.linux.dev, Mingcong Bai , Kexy Biscuit , Yao Zi Subject: [PATCH v2 1/8] dt-bindings: clock: loongson2: Add Loongson 2K0300 compatible Date: Tue, 17 Jun 2025 16:24:19 +0000 Message-ID: <20250617162426.12629-2-ziyao@disroot.org> In-Reply-To: <20250617162426.12629-1-ziyao@disroot.org> References: <20250617162426.12629-1-ziyao@disroot.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Document the clock controller shipped in Loongson 2K0300 SoC, which generates various clock signals for SoC peripherals. Differing from previous generations of SoCs, 2K0300 requires a 120MHz external clock input, and a separate dt-binding header is used for cleanness. Signed-off-by: Yao Zi --- .../bindings/clock/loongson,ls2k-clk.yaml | 26 ++++++--- MAINTAINERS | 1 + .../dt-bindings/clock/loongson,ls2k0300-clk.h | 54 +++++++++++++++++++ 3 files changed, 75 insertions(+), 6 deletions(-) create mode 100644 include/dt-bindings/clock/loongson,ls2k0300-clk.h diff --git a/Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml= b/Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml index 4f79cdb417ab..3e0a894cfb2f 100644 --- a/Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml +++ b/Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml @@ -16,6 +16,7 @@ description: | properties: compatible: enum: + - loongson,ls2k0300-clk - loongson,ls2k0500-clk - loongson,ls2k-clk # This is for Loongson-2K1000 - loongson,ls2k2000-clk @@ -24,19 +25,32 @@ properties: maxItems: 1 =20 clocks: - items: - - description: 100m ref + maxItems: 1 =20 - clock-names: - items: - - const: ref_100m + clock-names: true =20 '#clock-cells': const: 1 description: The clock consumer should specify the desired clock by having the cl= ock ID in its "clocks" phandle cell. See include/dt-bindings/clock/loong= son,ls2k-clk.h - for the full list of Loongson-2 SoC clock IDs. + and include/dt-bindings/clock/loongson,ls2k0300-clk.h for the full l= ist of + Loongson-2 SoC clock IDs. + +allOf: + - if: + properties: + compatible: + contains: + const: loongson,ls2k0300-clk + then: + properties: + clock-names: + const: ref_120m + else: + properties: + clock-names: + const: ref_100m =20 required: - compatible diff --git a/MAINTAINERS b/MAINTAINERS index dd844ac8d910..9b7c4b2b7f58 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -13954,6 +13954,7 @@ S: Maintained F: Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml F: drivers/clk/clk-loongson2.c F: include/dt-bindings/clock/loongson,ls2k-clk.h +F: include/dt-bindings/clock/loongson,ls2k0300-clk.h =20 LOONGSON SPI DRIVER M: Yinbo Zhu diff --git a/include/dt-bindings/clock/loongson,ls2k0300-clk.h b/include/dt= -bindings/clock/loongson,ls2k0300-clk.h new file mode 100644 index 000000000000..5e8f7b2f33f2 --- /dev/null +++ b/include/dt-bindings/clock/loongson,ls2k0300-clk.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (C) 2025 Yao Zi + */ +#ifndef _DT_BINDINGS_CLK_LOONGSON_LS2K300_H_ +#define _DT_BINDINGS_CLK_LOONGSON_LS2K300_H_ + +/* Derivied from REFCLK */ +#define LS2K0300_CLK_STABLE 0 +#define LS2K0300_PLL_NODE 1 +#define LS2K0300_PLL_DDR 2 +#define LS2K0300_PLL_PIX 3 +#define LS2K0300_CLK_THSENS 4 + +/* Derived from PLL_NODE */ +#define LS2K0300_CLK_NODE_DIV 5 +#define LS2K0300_CLK_NODE_PLL_GATE 6 +#define LS2K0300_CLK_NODE_SCALE 7 +#define LS2K0300_CLK_NODE_GATE 8 +#define LS2K0300_CLK_GMAC_DIV 9 +#define LS2K0300_CLK_GMAC_GATE 10 +#define LS2K0300_CLK_I2S_DIV 11 +#define LS2K0300_CLK_I2S_SCALE 12 +#define LS2K0300_CLK_I2S_GATE 13 + +/* Derived from PLL_DDR */ +#define LS2K0300_CLK_DDR_DIV 14 +#define LS2K0300_CLK_DDR_GATE 15 +#define LS2K0300_CLK_NET_DIV 16 +#define LS2K0300_CLK_NET_GATE 17 +#define LS2K0300_CLK_DEV_DIV 18 +#define LS2K0300_CLK_DEV_GATE 19 + +/* Derived from PLL_PIX */ +#define LS2K0300_CLK_PIX_DIV 20 +#define LS2K0300_CLK_PIX_PLL_GATE 21 +#define LS2K0300_CLK_PIX_SCALE 22 +#define LS2K0300_CLK_PIX_GATE 23 +#define LS2K0300_CLK_GMACBP_DIV 24 +#define LS2K0300_CLK_GMACBP_GATE 25 + +/* Derived from CLK_DEV */ +#define LS2K0300_CLK_USB_SCALE 26 +#define LS2K0300_CLK_USB_GATE 27 +#define LS2K0300_CLK_APB_SCALE 28 +#define LS2K0300_CLK_APB_GATE 29 +#define LS2K0300_CLK_BOOT_SCALE 30 +#define LS2K0300_CLK_BOOT_GATE 31 +#define LS2K0300_CLK_SDIO_SCALE 32 +#define LS2K0300_CLK_SDIO_GATE 33 + +#define LS2K0300_CLK_GMAC_IN 34 + +#endif // _DT_BINDINGS_CLK_LOONGSON_LS2K300_H_ --=20 2.49.0 From nobody Thu Oct 9 13:45:53 2025 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 778272ECEA2; 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arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="VmOYfInl" Received: from mail01.disroot.lan (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id 0A1B2258FA; Tue, 17 Jun 2025 18:25:12 +0200 (CEST) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id jUxbmW2mupcO; Tue, 17 Jun 2025 18:25:11 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1750177511; bh=aW5yvpNvSkcVrVrORKxyIa2LVFmcbX7kq7M2CNVH9bc=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=VmOYfInlvA1Ys9OKyUHUqrupu3ZiTwputngASKRn5LDUlf7LCISFWlJwGMOtwJLzd 6nT2+xQap/KwYbx7DaYzObHW+aFCGHqX4+OzUxqdDZX8ebCz4eeVoXQIx8GlJaSHHs 5YjNmdP3h9BAr5IxARgokMbk2+pOeIHLA8Gpg9l27kNgumDlXg3HyLNpRj0QF8xidf 551Qv8nRm0Mibuv9GjD+EpYyyZKlQRpNwA9PdyYfBb85Bi67Q0lODysMkl8+weceUD 6WhGKqVBn2Dq3WuvtH0atYeu4difjSyE4SBB0PcRu+fPbytG8gK2g0knzAoWSdcrfT Gaf+FWqyCBd1g== From: Yao Zi To: Yinbo Zhu , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Huacai Chen , WANG Xuerui Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, loongarch@lists.linux.dev, Mingcong Bai , Kexy Biscuit , Yao Zi Subject: [PATCH v2 2/8] clk: loongson2: Allow specifying clock flags for gate clock Date: Tue, 17 Jun 2025 16:24:20 +0000 Message-ID: <20250617162426.12629-3-ziyao@disroot.org> In-Reply-To: <20250617162426.12629-1-ziyao@disroot.org> References: <20250617162426.12629-1-ziyao@disroot.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some gate clocks need to be supplied with flags, e.g., it may be required to specify CLK_IS_CRTICAL for CPU clocks. Add a field to loongson2_clk_board_info for representing clock flags, and specify it when registering gate clocks. A new helper macro, CLK_GATE_FLAGS, is added to simplify definitions. Signed-off-by: Yao Zi --- drivers/clk/clk-loongson2.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/clk/clk-loongson2.c b/drivers/clk/clk-loongson2.c index 27e632edd484..cc3fb13e770f 100644 --- a/drivers/clk/clk-loongson2.c +++ b/drivers/clk/clk-loongson2.c @@ -50,6 +50,7 @@ struct loongson2_clk_board_info { const char *name; const char *parent_name; unsigned long fixed_rate; + unsigned long flags; u8 reg_offset; u8 div_shift; u8 div_width; @@ -105,6 +106,18 @@ struct loongson2_clk_board_info { .bit_idx =3D _bidx, \ } =20 +#define CLK_GATE_FLAGS(_id, _name, _pname, _offset, _bidx, \ + _flags) \ + { \ + .id =3D _id, \ + .type =3D CLK_TYPE_GATE, \ + .name =3D _name, \ + .parent_name =3D _pname, \ + .reg_offset =3D _offset, \ + .bit_idx =3D _bidx, \ + .flags =3D _flags \ + } + #define CLK_FIXED(_id, _name, _pname, _rate) \ { \ .id =3D _id, \ @@ -332,7 +345,8 @@ static int loongson2_clk_probe(struct platform_device *= pdev) &clp->clk_lock); break; case CLK_TYPE_GATE: - hw =3D devm_clk_hw_register_gate(dev, p->name, p->parent_name, 0, + hw =3D devm_clk_hw_register_gate(dev, p->name, p->parent_name, + p->flags, clp->base + p->reg_offset, p->bit_idx, 0, &clp->clk_lock); --=20 2.49.0 From nobody Thu Oct 9 13:45:53 2025 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 603472F9484; Tue, 17 Jun 2025 16:25:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750177558; cv=none; b=itvaviJCcDzMylGr2jWaJ/9OHU7nNH0mQYHflmlrWchtkWSAdY3sOAC4P1Wnn9feRzMc/km6uoK2A5w4CKbfQZ5mDYY7n3v386WEjG+eiRXEfKVdUs89U5wCsly6IujeVtNnobbkVx4m3Dz48+u5JG16Pa6IGaq4W0/4kx3dCV8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750177558; c=relaxed/simple; bh=UelRARJ4L5EQo961j7oIIU5hjPjnKWR1JwdiW487Osg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=IHcrClBUda4EoAN6qIAxIe9yWB175+G+bjE9E6A3/+G/+HRiu2izZcU/vFcpRrYU5grXjfQx2aPDWRS2QtjLmCKd9616d69xImcg3+GVHVpX4K1bAGeQP2GuvpjDXXYRD94hMxB4XSzD9mVRgjvzzTMhGcxEQx4i3fVREj1MjFQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org; spf=pass smtp.mailfrom=disroot.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b=IX9D2c+8; arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="IX9D2c+8" Received: from mail01.disroot.lan (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id D013125C75; Tue, 17 Jun 2025 18:25:55 +0200 (CEST) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id SbyVTrkJiCPk; Tue, 17 Jun 2025 18:25:55 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1750177554; bh=UelRARJ4L5EQo961j7oIIU5hjPjnKWR1JwdiW487Osg=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=IX9D2c+8JDAc2C4muJAewfDy3vqSzWa96Zga3OOIqdLGQKgcgiqAe8WLi3yQsN62V HaghMZXr/jZbJfwf2vYa1FReI6lXla3bLnh6IP/H+KMby1Dcs+NifvGIVBi55ERy2L QDk8nm+et2vRuJJLsea1FwLI0QL7jFHTJony4eo6wjckQp9Q/YikGOKRNcybjPMjx7 Ty7Yp/CG6RJFdnkHPTURT3FIBpiXxSRMDuCkyVHScgIXM6phtwAbnAJNS2FEqRcht4 YyRk1KNEVe5hm63SHAoe1ndhs24awjtD5l7jpphzKlVJnlO3/BuCzmin+E3jCkpcJr 8ou8Vn0G/LG7A== From: Yao Zi To: Yinbo Zhu , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Huacai Chen , WANG Xuerui Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, loongarch@lists.linux.dev, Mingcong Bai , Kexy Biscuit , Yao Zi Subject: [PATCH v2 3/8] clk: loongson2: Support scale clocks with an alternative mode Date: Tue, 17 Jun 2025 16:24:21 +0000 Message-ID: <20250617162426.12629-4-ziyao@disroot.org> In-Reply-To: <20250617162426.12629-1-ziyao@disroot.org> References: <20250617162426.12629-1-ziyao@disroot.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Loongson 2K0300 and 2K1500 ship scale clocks with an alternative mode. There's one mode bit in clock configuration register indicating the operation mode. When mode bit is unset, the scale clock acts the same as previous generation of scale clocks. When it's set, a different equation for calculating result frequency, Fout =3D Fin / (scale + 1), is used. This patch adds frequency calculation support for the scale clock variant. A helper macro, CLK_SCALE_MODE, is added to simplify definitions. Signed-off-by: Yao Zi --- drivers/clk/clk-loongson2.c | 26 +++++++++++++++++++++++--- 1 file changed, 23 insertions(+), 3 deletions(-) diff --git a/drivers/clk/clk-loongson2.c b/drivers/clk/clk-loongson2.c index cc3fb13e770f..bba97270376c 100644 --- a/drivers/clk/clk-loongson2.c +++ b/drivers/clk/clk-loongson2.c @@ -42,6 +42,7 @@ struct loongson2_clk_data { u8 div_width; u8 mult_shift; u8 mult_width; + u8 bit_idx; }; =20 struct loongson2_clk_board_info { @@ -96,6 +97,19 @@ struct loongson2_clk_board_info { .div_width =3D _dwidth, \ } =20 +#define CLK_SCALE_MODE(_id, _name, _pname, _offset, \ + _dshift, _dwidth, _midx) \ + { \ + .id =3D _id, \ + .type =3D CLK_TYPE_SCALE, \ + .name =3D _name, \ + .parent_name =3D _pname, \ + .reg_offset =3D _offset, \ + .div_shift =3D _dshift, \ + .div_width =3D _dwidth, \ + .bit_idx =3D _midx + 1, \ + } + #define CLK_GATE(_id, _name, _pname, _offset, _bidx) \ { \ .id =3D _id, \ @@ -243,13 +257,18 @@ static const struct clk_ops loongson2_pll_recalc_ops = =3D { static unsigned long loongson2_freqscale_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - u64 val, mult; + u64 val, scale; + u32 mode =3D 0; struct loongson2_clk_data *clk =3D to_loongson2_clk(hw); =20 val =3D readq(clk->reg); - mult =3D loongson2_rate_part(val, clk->div_shift, clk->div_width) + 1; + scale =3D loongson2_rate_part(val, clk->div_shift, clk->div_width) + 1; + + if (clk->bit_idx) + mode =3D val & BIT(clk->bit_idx - 1); =20 - return div_u64((u64)parent_rate * mult, 8); + return mode =3D=3D 0 ? div_u64((u64)parent_rate * scale, 8) : + div_u64((u64)parent_rate, scale); } =20 static const struct clk_ops loongson2_freqscale_recalc_ops =3D { @@ -284,6 +303,7 @@ static struct clk_hw *loongson2_clk_register(struct loo= ngson2_clk_provider *clp, clk->div_width =3D cld->div_width; clk->mult_shift =3D cld->mult_shift; clk->mult_width =3D cld->mult_width; + clk->bit_idx =3D cld->bit_idx; clk->hw.init =3D &init; =20 hw =3D &clk->hw; --=20 2.49.0 From nobody Thu Oct 9 13:45:53 2025 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B9D722EE287; Tue, 17 Jun 2025 16:26:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750177564; cv=none; b=ot/cVbF8AqaPQ0HyZY06PW1B7ocKtGqSvHKbuL7NORbQPzY6VEn2FY2BpIdA/3LXCWRUqJMNsQFrAvypI+d3W4KQ56wsCty09VZJGYZZmXjNYeOi2ix675ijO24sB7LW2hi2ohCevPsq6zqFI1acSivY2dFy3KBVUFZ4JxJ2jiE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750177564; c=relaxed/simple; bh=hVpvRGbKFKtFx1BRcVBUOZPuHWI/E7Qle7Kn2K+uayU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=K9yao3NXxXnqqys3+s/RC8tEavsvvXyn9gqXOwQOK44eqQCGiWEFriiY3zmuLiMEH4alONpzJtIXHxTQOPhRXLO34ovPiCY0CXT/qbRa99+vAhhKjf1NPwqXWU3klId4wPPKaYizd5VRLZm746V5446/knJlDNDhdfrArlJm+A8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org; spf=pass smtp.mailfrom=disroot.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b=XQaWgLdg; arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="XQaWgLdg" Received: from mail01.disroot.lan (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id 3E47425CE1; Tue, 17 Jun 2025 18:26:01 +0200 (CEST) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id 6U7ouOmMD5_m; Tue, 17 Jun 2025 18:26:00 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1750177560; bh=hVpvRGbKFKtFx1BRcVBUOZPuHWI/E7Qle7Kn2K+uayU=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=XQaWgLdgMX6bWjB9ziBBD1yJ0zBnIbfl7hw/2+XwS7fpl6En3RrW1/rd+Sm3tnllb uhdsNIByUGzPJpaynwq0+94VcbZAyT2Xnh24kdApGFRh/IFJklCisnumA0NHDp6gUh sJPrEilrSEzjCz/ZoCH1Jpg9VRY+D1lQ2+MpsHzO+pjuZWfL92B/s1R4ZpR0J9bl9g HDC2JOL0HJQLBEecaUETuNAQSn1Qf2q7S9ED2P2J69tEVly1EN/PdjtIcGz2BjKxVE Ehh/dmx0KA5WmvRsfLG/FWLLKaKr01VhxbO8rDnhyf0eM9L1P17Uurv70ubc3mdWxb KdLhJf89s0NvA== From: Yao Zi To: Yinbo Zhu , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Huacai Chen , WANG Xuerui Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, loongarch@lists.linux.dev, Mingcong Bai , Kexy Biscuit , Yao Zi Subject: [PATCH v2 4/8] clk: loongson2: Allow zero divisors for dividers Date: Tue, 17 Jun 2025 16:24:22 +0000 Message-ID: <20250617162426.12629-5-ziyao@disroot.org> In-Reply-To: <20250617162426.12629-1-ziyao@disroot.org> References: <20250617162426.12629-1-ziyao@disroot.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Loongson 2K0300 and 2K0500 ship divider clocks which allows zero divisors, in which case the divider acts the same as one is specified. Let's pass CLK_DIVIDER_ALLOW_ZERO when registering divider clocks to prepare for future introduction of these clocks. Signed-off-by: Yao Zi --- drivers/clk/clk-loongson2.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/clk/clk-loongson2.c b/drivers/clk/clk-loongson2.c index bba97270376c..7a916c7d2718 100644 --- a/drivers/clk/clk-loongson2.c +++ b/drivers/clk/clk-loongson2.c @@ -361,7 +361,8 @@ static int loongson2_clk_probe(struct platform_device *= pdev) p->parent_name, 0, clp->base + p->reg_offset, p->div_shift, p->div_width, - CLK_DIVIDER_ONE_BASED, + CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, &clp->clk_lock); break; case CLK_TYPE_GATE: --=20 2.49.0 From nobody Thu Oct 9 13:45:53 2025 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 467482EE287; Tue, 17 Jun 2025 16:26:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750177570; cv=none; b=swdGnaIuTtDJuLKp31GK7UCEo2HgWw2Da88sB7S/9YORgAIXpcI1eTm1zdZgI3JjZfAJuRQ4RJ80ZLCYDLVSh3xLDXS4NsfSM81ubRJngFZB+9U2GoNtPqaNKSSBCWibpeO6JclFcBnQuXwfKN2HAce2913hwOZDSiVAKECxZ/I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750177570; c=relaxed/simple; bh=yLdR6mHtlRPoNVFrYNKreCLkJDkwlDyjW2OgdjtFUl0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=PdTvhIfHg1nVKl6PJrvr1ecKpfzY2lCJE51pKc0Cu8wvzludPyX6EY5v0+I1lxOinder2v572uexXCnvQvd9KjY4y3G3j9l3GJ+e7YTBqVjCiVQM7VFvZp7CLOArDhzbyycnWFBlzVb3cKzbo1drg01JlX9hN+8i4r9duCwJBKQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org; spf=pass smtp.mailfrom=disroot.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b=d9d4km66; arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="d9d4km66" Received: from mail01.disroot.lan (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id 059FE25CF4; Tue, 17 Jun 2025 18:26:07 +0200 (CEST) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id iTuHbFsScbuO; Tue, 17 Jun 2025 18:26:05 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1750177565; bh=yLdR6mHtlRPoNVFrYNKreCLkJDkwlDyjW2OgdjtFUl0=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=d9d4km66jUCy0m2MsRGR7IloQFTD4qraGHLC8/h7D/wadR/GGu9em9PsKPvQO/84n hDajqPqGQ3AznBACjPQ/bvlKb0vcToA0hMRStK/TtyFVUX9WtjJPEy2CnyM3kqpCjh rs+mvRqWzu7NQq68kQWe9nsUytNe1Q3rMJwiwDE/FFyQRnm2d8s8WrokY/n9AYrMWw gxKQ79x0uAQOvIpB2BHjKLUz6Ah7gesVlpsf6L2TWxYh54HJzCYf8UujQ3vnTopbG6 LL+bRLI6k4ZvUv6U3lCYG+7QJnEiQU76gkXoS51kSBsbZZ3TJf0FEoFvGZVmT8Vc3j 4wo7Smn4Vf6GQ== From: Yao Zi To: Yinbo Zhu , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Huacai Chen , WANG Xuerui Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, loongarch@lists.linux.dev, Mingcong Bai , Kexy Biscuit , Yao Zi Subject: [PATCH v2 5/8] clk: loongson2: Avoid hardcoding firmware name of the reference clock Date: Tue, 17 Jun 2025 16:24:23 +0000 Message-ID: <20250617162426.12629-6-ziyao@disroot.org> In-Reply-To: <20250617162426.12629-1-ziyao@disroot.org> References: <20250617162426.12629-1-ziyao@disroot.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Loongson 2K0300 requires a reference clock with a frequency different from previous SoCs (120MHz v.s. 100MHz), thus hardcoding the firmware name of the reference clock as ref_100m isn't a good idea. This patch retrives the clock name of the reference clock dynamically during probe, avoiding the hardcoded pdata structure and preparing for support of future SoCs. Signed-off-by: Yao Zi --- drivers/clk/clk-loongson2.c | 33 +++++++++++++++++---------------- 1 file changed, 17 insertions(+), 16 deletions(-) diff --git a/drivers/clk/clk-loongson2.c b/drivers/clk/clk-loongson2.c index 7a916c7d2718..52a9f1c2794a 100644 --- a/drivers/clk/clk-loongson2.c +++ b/drivers/clk/clk-loongson2.c @@ -13,10 +13,6 @@ #include #include =20 -static const struct clk_parent_data pdata[] =3D { - { .fw_name =3D "ref_100m", }, -}; - enum loongson2_clk_type { CLK_TYPE_PLL, CLK_TYPE_SCALE, @@ -275,7 +271,8 @@ static const struct clk_ops loongson2_freqscale_recalc_= ops =3D { .recalc_rate =3D loongson2_freqscale_recalc_rate, }; =20 -static struct clk_hw *loongson2_clk_register(struct loongson2_clk_provider= *clp, +static struct clk_hw *loongson2_clk_register(const char *parent, + struct loongson2_clk_provider *clp, const struct loongson2_clk_board_info *cld, const struct clk_ops *ops) { @@ -292,11 +289,7 @@ static struct clk_hw *loongson2_clk_register(struct lo= ongson2_clk_provider *clp, init.ops =3D ops; init.flags =3D 0; init.num_parents =3D 1; - - if (!cld->parent_name) - init.parent_data =3D pdata; - else - init.parent_names =3D &cld->parent_name; + init.parent_names =3D &parent; =20 clk->reg =3D clp->base + cld->reg_offset; clk->div_shift =3D cld->div_shift; @@ -321,11 +314,17 @@ static int loongson2_clk_probe(struct platform_device= *pdev) struct device *dev =3D &pdev->dev; struct loongson2_clk_provider *clp; const struct loongson2_clk_board_info *p, *data; + const char *refclk_name, *parent_name; =20 data =3D device_get_match_data(dev); if (!data) return -EINVAL; =20 + refclk_name =3D of_clk_get_parent_name(dev->of_node, 0); + if (IS_ERR(refclk_name)) + return dev_err_probe(dev, PTR_ERR(refclk_name), + "failed to get refclk name\n"); + for (p =3D data; p->name; p++) clks_num =3D max(clks_num, p->id + 1); =20 @@ -347,18 +346,20 @@ static int loongson2_clk_probe(struct platform_device= *pdev) =20 for (i =3D 0; i < clks_num; i++) { p =3D &data[i]; + parent_name =3D p->parent_name ? p->parent_name : refclk_name; + switch (p->type) { case CLK_TYPE_PLL: - hw =3D loongson2_clk_register(clp, p, + hw =3D loongson2_clk_register(parent_name, clp, p, &loongson2_pll_recalc_ops); break; case CLK_TYPE_SCALE: - hw =3D loongson2_clk_register(clp, p, + hw =3D loongson2_clk_register(parent_name, clp, p, &loongson2_freqscale_recalc_ops); break; case CLK_TYPE_DIVIDER: hw =3D devm_clk_hw_register_divider(dev, p->name, - p->parent_name, 0, + parent_name, 0, clp->base + p->reg_offset, p->div_shift, p->div_width, CLK_DIVIDER_ONE_BASED | @@ -366,15 +367,15 @@ static int loongson2_clk_probe(struct platform_device= *pdev) &clp->clk_lock); break; case CLK_TYPE_GATE: - hw =3D devm_clk_hw_register_gate(dev, p->name, p->parent_name, + hw =3D devm_clk_hw_register_gate(dev, p->name, parent_name, p->flags, clp->base + p->reg_offset, p->bit_idx, 0, &clp->clk_lock); break; case CLK_TYPE_FIXED: - hw =3D devm_clk_hw_register_fixed_rate_parent_data(dev, p->name, pdata, - 0, p->fixed_rate); + hw =3D devm_clk_hw_register_fixed_rate(dev, p->name, parent_name, + 0, p->fixed_rate); break; default: return dev_err_probe(dev, -EINVAL, "Invalid clk type\n"); --=20 2.49.0 From nobody Thu Oct 9 13:45:53 2025 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1FAAF2ED868; Tue, 17 Jun 2025 16:26:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750177618; cv=none; b=Ql9dfokQz95X9k/RXtdDN2slQ33sfDhwz2qOnw4jXJECCaH+Mz9eFvKhHBJx9PpCpbFE2wRuG87UYlbY12UQAgKzl9y9pJ/aERAkhuY3JjzgWzCZMvuLWPvH+N0rxxYAcBL6MOr5fT9TiUm5gpkvQcw5RI3/m5f+ZbB+PrvHzr4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750177618; c=relaxed/simple; bh=gcYtgfygnQQQpxyGja4Ww0pSmxn9UnF2hNVedw7xXtc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=pKXdFba3YgsFedFD6dCtWpln7NV55R9ej9xHHiCsLVbwyCoRRcASrLb2fnLgBucb+pklszdPbgANjIhHW6z5xHifmUxpSMOm+RgAqCwVyVy1N4riyvMzEX0ezoDvKIG87cFZRq0ucz6KYKTn0tSKckZKTS7S+P8EVFtKG2AJm3k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org; spf=pass smtp.mailfrom=disroot.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b=OKQRS5Vu; arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="OKQRS5Vu" Received: from mail01.disroot.lan (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id BB23625CF4; Tue, 17 Jun 2025 18:26:55 +0200 (CEST) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id 2Et__IjP5nuD; Tue, 17 Jun 2025 18:26:54 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1750177614; bh=gcYtgfygnQQQpxyGja4Ww0pSmxn9UnF2hNVedw7xXtc=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=OKQRS5VuwWsVTZZzk/HvnbjS3AO28oSt0GAVf9bNdqa5H7+89R+TOzFxWz6YgKPht IG77f+bJWVB3LfXRUdBcU4yI0brygQMWpH3No7xqRyKzcM6u7rWfjk60QMYDBlPszr UsGb6MUuksZE17b9nlZAu34uzFUfoupF09NyUjb4xswdC3UFrOYcWcQtnZs3RrfRn3 P5Rct+0AbfqFVVW7c+FpgZry8H7u4anqbZYb4KpFMvtykzI5Wl8qUgFnp5zTHeJyTE gJpFtc/y0qcFeP5Xf7r8bR//Xbb80F56j05TaR6J11hsX6GjjxrfSCge6nILBF1H16 o/KsWzYA4h/TA== From: Yao Zi To: Yinbo Zhu , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Huacai Chen , WANG Xuerui Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, loongarch@lists.linux.dev, Mingcong Bai , Kexy Biscuit , Yao Zi Subject: [PATCH v2 6/8] clk: loongson2: Add clock definitions for Loongson 2K0300 SoC Date: Tue, 17 Jun 2025 16:24:24 +0000 Message-ID: <20250617162426.12629-7-ziyao@disroot.org> In-Reply-To: <20250617162426.12629-1-ziyao@disroot.org> References: <20250617162426.12629-1-ziyao@disroot.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The clock controller of Loongson 2K0300 consists of three PLLs, requires an 120MHz external reference clock to function, and generates clocks in various frequencies for SoC peripherals. Clock definitions for previous SoC generations could be reused for most clock hardwares. There're two gates marked as critical, clk_node_gate and clk_boot_gate, which supply the CPU cores and the system configuration bus. Disabling them leads to a SoC hang. Signed-off-by: Yao Zi --- drivers/clk/clk-loongson2.c | 48 +++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/drivers/clk/clk-loongson2.c b/drivers/clk/clk-loongson2.c index 52a9f1c2794a..1d210a7683ea 100644 --- a/drivers/clk/clk-loongson2.c +++ b/drivers/clk/clk-loongson2.c @@ -12,6 +12,7 @@ #include #include #include +#include =20 enum loongson2_clk_type { CLK_TYPE_PLL, @@ -137,6 +138,52 @@ struct loongson2_clk_board_info { .fixed_rate =3D _rate, \ } =20 +static const struct loongson2_clk_board_info ls2k0300_clks[] =3D { + /* Reference Clock */ + CLK_PLL(LS2K0300_PLL_NODE, "pll_node", 0x00, 15, 9, 8, 7), + CLK_PLL(LS2K0300_PLL_DDR, "pll_ddr", 0x08, 15, 9, 8, 7), + CLK_PLL(LS2K0300_PLL_PIX, "pll_pix", 0x10, 15, 9, 8, 7), + CLK_FIXED(LS2K0300_CLK_STABLE, "clk_stable", NULL, 100000000), + CLK_FIXED(LS2K0300_CLK_THSENS, "clk_thsens", NULL, 10000000), + /* Node PLL */ + CLK_DIV(LS2K0300_CLK_NODE_DIV, "clk_node_div", "pll_node", 0x00, 24, 7), + CLK_DIV(LS2K0300_CLK_GMAC_DIV, "clk_gmac_div", "pll_node", 0x04, 0, 7), + CLK_DIV(LS2K0300_CLK_I2S_DIV, "clk_i2s_div", "pll_node", 0x04, 8, 7), + CLK_GATE(LS2K0300_CLK_NODE_PLL_GATE, "clk_node_pll_gate", "clk_node_div= ", 0x00, 0), + CLK_GATE(LS2K0300_CLK_GMAC_GATE, "clk_gmac_gate", "clk_gmac_div= ", 0x00, 1), + CLK_GATE(LS2K0300_CLK_I2S_GATE, "clk_i2s_gate", "clk_i2s_div",= 0x00, 2), + CLK_GATE_FLAGS(LS2K0300_CLK_NODE_GATE, "clk_node_gate", "clk_node_sca= le", + 0x24, 0, CLK_IS_CRITICAL), + CLK_SCALE_MODE(LS2K0300_CLK_NODE_SCALE, "clk_node_scale", "clk_node= _pll_gate", + 0x20, 0, 3, 3), + /* DDR PLL */ + CLK_DIV(LS2K0300_CLK_DDR_DIV, "clk_ddr_div", "pll_ddr", 0x08, 24, 7), + CLK_DIV(LS2K0300_CLK_NET_DIV, "clk_net_div", "pll_ddr", 0x0c, 0, 7), + CLK_DIV(LS2K0300_CLK_DEV_DIV, "clk_dev_div", "pll_ddr", 0x0c, 8, 7), + CLK_GATE(LS2K0300_CLK_NET_GATE, "clk_net_gate", "clk_net_div", 0x08, 1), + CLK_GATE(LS2K0300_CLK_DEV_GATE, "clk_dev_gate", "clk_dev_div", 0x08, 2), + CLK_GATE_FLAGS(LS2K0300_CLK_DDR_GATE, "clk_ddr_gate", "clk_ddr_div", + 0x08, 0, CLK_IS_CRITICAL), + /* PIX PLL */ + CLK_DIV(LS2K0300_CLK_PIX_DIV, "clk_pix_div", "pll_pix", 0x10, 24, 7), + CLK_DIV(LS2K0300_CLK_GMACBP_DIV, "clk_gmacbp_div", "pll_pix", 0x14, 0, 7), + CLK_GATE(LS2K0300_CLK_PIX_PLL_GATE, "clk_pix_pll_gate", "clk_pix_div", 0x= 10, 0), + CLK_GATE(LS2K0300_CLK_PIX_GATE, "clk_pix_gate", "clk_pix_scale", 0x24= , 6), + CLK_GATE(LS2K0300_CLK_GMACBP_GATE, "clk_gmacbp_gate", "clk_gmacbp_div", = 0x10, 1), + CLK_SCALE_MODE(LS2K0300_CLK_PIX_SCALE, "clk_pix_scale", "clk_pix_pll_gate= ", + 0x20, 4, 3, 7), + /* clk_dev_gate */ + CLK_DIV(LS2K0300_CLK_SDIO_SCALE, "clk_sdio_scale", "clk_dev_gate", 0x20, = 24, 4), + CLK_GATE(LS2K0300_CLK_USB_GATE, "clk_usb_gate", "clk_usb_scale", 0x24, 2= ), + CLK_GATE(LS2K0300_CLK_SDIO_GATE, "clk_sdio_gate", "clk_sdio_scale", 0x24,= 4), + CLK_GATE(LS2K0300_CLK_APB_GATE, "clk_apb_gate", "clk_apb_scale", 0x24, 3= ), + CLK_GATE_FLAGS(LS2K0300_CLK_BOOT_GATE, "clk_boot_gate", "clk_boot_scale", + 0x24, 1, CLK_IS_CRITICAL), + CLK_SCALE_MODE(LS2K0300_CLK_USB_SCALE, "clk_usb_scale", "clk_dev_gate",= 0x20, 12, 3, 15), + CLK_SCALE_MODE(LS2K0300_CLK_APB_SCALE, "clk_apb_scale", "clk_dev_gate",= 0x20, 16, 3, 19), + CLK_SCALE_MODE(LS2K0300_CLK_BOOT_SCALE, "clk_boot_scale", "clk_dev_gate",= 0x20, 8, 3, 11), +}; + static const struct loongson2_clk_board_info ls2k0500_clks[] =3D { CLK_PLL(LOONGSON2_NODE_PLL, "pll_node", 0, 16, 8, 8, 6), CLK_PLL(LOONGSON2_DDR_PLL, "pll_ddr", 0x8, 16, 8, 8, 6), @@ -393,6 +440,7 @@ static int loongson2_clk_probe(struct platform_device *= pdev) } =20 static const struct of_device_id loongson2_clk_match_table[] =3D { + { .compatible =3D "loongson,ls2k0300-clk", .data =3D &ls2k0300_clks }, { .compatible =3D "loongson,ls2k0500-clk", .data =3D &ls2k0500_clks }, { .compatible =3D "loongson,ls2k-clk", .data =3D &ls2k1000_clks }, { .compatible =3D "loongson,ls2k2000-clk", .data =3D &ls2k2000_clks }, --=20 2.49.0 From nobody Thu Oct 9 13:45:53 2025 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 736C12EE5E8; Tue, 17 Jun 2025 16:27:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; 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charset="utf-8" Describe the clock controller integrated in Loongson 2K0300 SoC and clocks for UARTs. Signed-off-by: Yao Zi --- arch/loongarch/boot/dts/loongson-2k0300.dtsi | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/arch/loongarch/boot/dts/loongson-2k0300.dtsi b/arch/loongarch/= boot/dts/loongson-2k0300.dtsi index ce3574691aa9..44e37d6f8e98 100644 --- a/arch/loongarch/boot/dts/loongson-2k0300.dtsi +++ b/arch/loongarch/boot/dts/loongson-2k0300.dtsi @@ -6,6 +6,7 @@ =20 /dts-v1/; =20 +#include #include =20 / { @@ -21,7 +22,7 @@ cpu0: cpu@0 { compatible =3D "loongson,la264"; reg =3D <0>; device_type =3D "cpu"; - clocks =3D <&cpu_clk>; + clocks =3D <&clk LS2K0300_CLK_NODE_GATE>; }; =20 }; @@ -32,9 +33,10 @@ cpuintc: interrupt-controller { #interrupt-cells =3D <1>; }; =20 - cpu_clk: clock-1000m { + refclk: clock-120m { compatible =3D "fixed-clock"; - clock-frequency =3D <1000000000>; + clock-frequency =3D <120000000>; + clock-output-names =3D "refclk_120m"; #clock-cells =3D <0>; }; =20 @@ -46,6 +48,14 @@ soc@10000000 { <0x00 0x02000000 0x00 0x02000000 0x0 0x04000000>, <0x00 0x40000000 0x00 0x40000000 0x0 0x40000000>; =20 + clk: clock-controller@16000400 { + compatible =3D "loongson,ls2k0300-clk"; + reg =3D <0x0 0x16000400 0x0 0x100>; + clocks =3D <&refclk>; + clock-names =3D "ref_120m"; + #clock-cells =3D <1>; + }; + liointc0: interrupt-controller@16001400 { compatible =3D "loongson,liointc-2.0"; reg =3D <0x0 0x16001400 0x0 0x40>, @@ -87,6 +97,7 @@ liointc1: interrupt-controller@16001440 { uart0: serial@16100000 { compatible =3D "ns16550a"; reg =3D <0 0x16100000 0 0x10>; + clocks =3D <&clk LS2K0300_CLK_APB_GATE>; interrupt-parent =3D <&liointc0>; interrupts =3D <0 IRQ_TYPE_LEVEL_HIGH>; no-loopback-test; --=20 2.49.0 From nobody Thu Oct 9 13:45:53 2025 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BBD242F3636; Tue, 17 Jun 2025 16:27:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; 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charset="utf-8" The property isn't required anymore as the supply clock of UART0 has been described. Signed-off-by: Yao Zi --- arch/loongarch/boot/dts/loongson-2k0300-ctcisz-forever-pi.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/loongarch/boot/dts/loongson-2k0300-ctcisz-forever-pi.dts = b/arch/loongarch/boot/dts/loongson-2k0300-ctcisz-forever-pi.dts index a033c086461f..1bdfff7fae92 100644 --- a/arch/loongarch/boot/dts/loongson-2k0300-ctcisz-forever-pi.dts +++ b/arch/loongarch/boot/dts/loongson-2k0300-ctcisz-forever-pi.dts @@ -40,6 +40,5 @@ linux,cma { }; =20 &uart0 { - clock-frequency =3D <100000000>; status =3D "okay"; }; --=20 2.49.0