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Tue, 17 Jun 2025 08:58:03 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:a081:30f1:e1c7:6f28]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a568a53f79sm14189115f8f.4.2025.06.17.08.58.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Jun 2025 08:58:02 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v2 4/4] clk: renesas: Add CPG/MSSR support to RZ/N2H SoC Date: Tue, 17 Jun 2025 16:57:57 +0100 Message-ID: <20250617155757.149597-5-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250617155757.149597-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250617155757.149597-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Add clock driver support for the Renesas RZ/N2H (R9A09G087) SoC by reusing the existing RZ/T2H (R9A09G077) CPG/MSSR implementation, as both SoCs share the same clock and reset architecture. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- v1->v2: - Updated commit message - Added reviewed-by tags --- drivers/clk/renesas/Kconfig | 5 +++++ drivers/clk/renesas/Makefile | 1 + drivers/clk/renesas/r9a09g077-cpg.c | 1 + drivers/clk/renesas/renesas-cpg-mssr.c | 6 ++++++ 4 files changed, 13 insertions(+) diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig index 45f9ae5b6ef1..6a5a04664990 100644 --- a/drivers/clk/renesas/Kconfig +++ b/drivers/clk/renesas/Kconfig @@ -44,6 +44,7 @@ config CLK_RENESAS select CLK_R9A09G056 if ARCH_R9A09G056 select CLK_R9A09G057 if ARCH_R9A09G057 select CLK_R9A09G077 if ARCH_R9A09G077 + select CLK_R9A09G087 if ARCH_R9A09G087 select CLK_SH73A0 if ARCH_SH73A0 =20 if CLK_RENESAS @@ -213,6 +214,10 @@ config CLK_R9A09G077 bool "RZ/T2H clock support" if COMPILE_TEST select CLK_RENESAS_CPG_MSSR =20 +config CLK_R9A09G087 + bool "RZ/N2H clock support" if COMPILE_TEST + select CLK_RENESAS_CPG_MSSR + config CLK_SH73A0 bool "SH-Mobile AG5 clock support" if COMPILE_TEST select CLK_RENESAS_CPG_MSTP diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile index d8d894a15d24..d28eb276a153 100644 --- a/drivers/clk/renesas/Makefile +++ b/drivers/clk/renesas/Makefile @@ -41,6 +41,7 @@ obj-$(CONFIG_CLK_R9A09G047) +=3D r9a09g047-cpg.o obj-$(CONFIG_CLK_R9A09G056) +=3D r9a09g056-cpg.o obj-$(CONFIG_CLK_R9A09G057) +=3D r9a09g057-cpg.o obj-$(CONFIG_CLK_R9A09G077) +=3D r9a09g077-cpg.o +obj-$(CONFIG_CLK_R9A09G087) +=3D r9a09g077-cpg.o obj-$(CONFIG_CLK_SH73A0) +=3D clk-sh73a0.o =20 # Family diff --git a/drivers/clk/renesas/r9a09g077-cpg.c b/drivers/clk/renesas/r9a0= 9g077-cpg.c index b83ef933ae0f..baf917ff4beb 100644 --- a/drivers/clk/renesas/r9a09g077-cpg.c +++ b/drivers/clk/renesas/r9a09g077-cpg.c @@ -13,6 +13,7 @@ #include =20 #include +#include #include "renesas-cpg-mssr.h" =20 #define RZT2H_REG_BLOCK_SHIFT 11 diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/r= enesas-cpg-mssr.c index 4a5ac9eef9cc..5ff6ee1f7d4b 100644 --- a/drivers/clk/renesas/renesas-cpg-mssr.c +++ b/drivers/clk/renesas/renesas-cpg-mssr.c @@ -941,6 +941,12 @@ static const struct of_device_id cpg_mssr_match[] =3D { .compatible =3D "renesas,r9a09g077-cpg-mssr", .data =3D &r9a09g077_cpg_mssr_info, }, +#endif +#ifdef CONFIG_CLK_R9A09G087 + { + .compatible =3D "renesas,r9a09g087-cpg-mssr", + .data =3D &r9a09g077_cpg_mssr_info, + }, #endif { /* sentinel */ } }; --=20 2.49.0