From nobody Thu Oct 9 16:42:20 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 945A22E267E for ; Tue, 17 Jun 2025 13:59:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750168791; cv=none; b=YnPabiAfUKzPizwYyWP38A9PK5dchpbDIGl6khvJayfGf3XXyGeZMGapSRrk2It8Ed+ilDOP02UiZMKuPOK7EtYjXSZL7HEE7H6SQSxwXzdWia0L5Z+dBhesivPzjZB2YEUF3IoCOWEAZkBisnIRRqYZjCKHfYv6NuXE8dfrpME= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750168791; c=relaxed/simple; bh=brHnIOdScb0KxCyYh6StjKNndkZEaHPzreNgxMkxZxU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Hwh9IhaVzS9bMSTxR3ciSoOEadLU8js3a4quovEqE0XaOt88STdZupbOTbBp2DitZnPX7Qa8fjJarn3BZ3kQ1roS97Q92YvjX+RhfSWz6oDUGerwWvLdXVw03p7534svbUB4nJrnq0XWzFconPzmT0FhlujgO+RueT0WOmWIJTo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=PGDzQiCI; arc=none smtp.client-ip=198.175.65.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="PGDzQiCI" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1750168790; x=1781704790; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=brHnIOdScb0KxCyYh6StjKNndkZEaHPzreNgxMkxZxU=; b=PGDzQiCILF+ErBHaI7GdSz3FZW9nRcSRy/PaTmJSASMySLAAH3bzT9Wg la0IJXW8VFkvf7d0ABo91g7g4P/Lu3fhI6UspQl/Bry13INegfpx1T9Mw NcfXZNjUx7/DA4+I03TGNnODVVIiEd8dGqLYjEJrpnut11Snaq30UUtWs cEhKX6RYz1lcOs+jlAG7Gci5IYtEfPE7Ej1OHBI2DpjzKo+T0m3H4O+xg oc0xm+DP6r5vfpLVY4rmJ4aKfBcqR0fqst8BfXEb9GpGVlCb9vCkf/bzF Vd4tn7Ky8k3E32/nt/ZcJN8PGP4qdItBEoKQAjxRO8E/7oCAntMR4HkZ+ g==; X-CSE-ConnectionGUID: 70xAjLH2RuaTOnBnxVhmVw== X-CSE-MsgGUID: 6Cpe5BQxQD27fq8r3qHlnw== X-IronPort-AV: E=McAfee;i="6800,10657,11467"; a="56026582" X-IronPort-AV: E=Sophos;i="6.16,243,1744095600"; d="scan'208";a="56026582" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jun 2025 06:59:49 -0700 X-CSE-ConnectionGUID: kVM6VBcbTL24Dzz690BmJQ== X-CSE-MsgGUID: SteaBKKCRLeHZUO7Whk3Ig== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,243,1744095600"; d="scan'208";a="153739554" Received: from sannilnx-dsk.jer.intel.com ([10.12.231.107]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jun 2025 06:59:43 -0700 From: Alexander Usyskin To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Lucas De Marchi , =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= , Rodrigo Vivi , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Jani Nikula , Joonas Lahtinen , Tvrtko Ursulin , Karthik Poosa , Raag Jadav Cc: Reuven Abliyev , linux-mtd@lists.infradead.org, intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, Alexander Usyskin Subject: [PATCH v13 07/10] drm/i915/nvm: add support for access mode Date: Tue, 17 Jun 2025 16:45:29 +0300 Message-ID: <20250617134532.3768283-8-alexander.usyskin@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250617134532.3768283-1-alexander.usyskin@intel.com> References: <20250617134532.3768283-1-alexander.usyskin@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Check NVM access mode from GSC FW status registers and overwrite access status read from SPI descriptor, if needed. Reviewed-by: Rodrigo Vivi Acked-by: Rodrigo Vivi Signed-off-by: Alexander Usyskin --- drivers/gpu/drm/i915/intel_nvm.c | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_nvm.c b/drivers/gpu/drm/i915/intel_= nvm.c index ae7f9f2c01bf..4624cba26fa7 100644 --- a/drivers/gpu/drm/i915/intel_nvm.c +++ b/drivers/gpu/drm/i915/intel_nvm.c @@ -11,6 +11,7 @@ #include "intel_nvm.h" =20 #define GEN12_GUNIT_NVM_SIZE 0x80 +#define HECI_FW_STATUS_2_NVM_ACCESS_MODE BIT(3) =20 static const struct intel_dg_nvm_region regions[INTEL_DG_NVM_REGIONS] =3D { [0] =3D { .name =3D "DESCRIPTOR", }, @@ -23,6 +24,28 @@ static void i915_nvm_release_dev(struct device *dev) { } =20 +static bool i915_nvm_writable_override(struct drm_i915_private *i915) +{ + bool writable_override; + resource_size_t base; + + if (IS_DG1(i915)) { + base =3D DG1_GSC_HECI2_BASE; + } else if (IS_DG2(i915)) { + base =3D DG2_GSC_HECI2_BASE; + } else { + drm_err(&i915->drm, "Unknown platform\n"); + return true; + } + + writable_override =3D + !(intel_uncore_read(&i915->uncore, HECI_FWSTS(base, 2)) & + HECI_FW_STATUS_2_NVM_ACCESS_MODE); + if (writable_override) + drm_info(&i915->drm, "NVM access overridden by jumper\n"); + return writable_override; +} + int intel_nvm_init(struct drm_i915_private *i915) { struct pci_dev *pdev =3D to_pci_dev(i915->drm.dev); @@ -44,7 +67,7 @@ int intel_nvm_init(struct drm_i915_private *i915) =20 nvm =3D i915->nvm; =20 - nvm->writable_override =3D true; + nvm->writable_override =3D i915_nvm_writable_override(i915); nvm->bar.parent =3D &pdev->resource[0]; nvm->bar.start =3D GEN12_GUNIT_NVM_BASE + pdev->resource[0].start; nvm->bar.end =3D nvm->bar.start + GEN12_GUNIT_NVM_SIZE - 1; --=20 2.43.0