From nobody Thu Oct 9 16:48:54 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 54BF32E337C for ; Tue, 17 Jun 2025 14:00:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750168803; cv=none; b=E91NCvZc0xPU2Zj9PvREE5C2zYQHcCxcx2WOkOq0YY3oBfO36LZTBv47+EKTHVpvchcCOAIRLJDqcjAtczfcVQcvaAXT6HW4kfrzTYDVm4c1EkFthgAqWjdIQxvsVFq1DuUqjPGARXORXuuQ2QijuUhIXsZxkotLKaV2JHnN4PI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750168803; c=relaxed/simple; bh=luOze6g0PP5F5pCLOK5jBaa2umhqnsfnayAFqvQ9H4M=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=AAy10qcEHK6U9sCdPQxy/RRk/mN6rgYBlRPr6JfEz4mfaIzfmLCuqxslVnnkuZ6Xd97k5pnbhShEA0sl8Q//sbPCe6/0XoiXw8ZfpTqw0IQyk4ztcA5enA2hu8zwTNAzTNVmw70mYIjQOaciqwLjP1cyIPsyYI4CMT7c53eSXVM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=kEFdY1Pa; arc=none smtp.client-ip=198.175.65.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="kEFdY1Pa" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1750168802; x=1781704802; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=luOze6g0PP5F5pCLOK5jBaa2umhqnsfnayAFqvQ9H4M=; b=kEFdY1PaIU7yD332r/EJ59NDEqLjBbF5BAO7XaHCg3g3vxLaxVenL5nH EX2NpX9ls2PccIXWyheOzIXK1O852IOEjHkbKBuuURo05iV+xwUmTBhpy vFwrgQ2sLS8UuhxugY5XaDel5ntx2s7/LM7Y6O6mvTjdnp52EloH02vsO rm9pMQJqXQcxAhHQ8xs7nxoYdWF11n/XrQNeFrXHXmPpWPS52sVFrG4Ml LEqluWDESEpDqf1hHgVCsbXc2M1/y/208YypoLN4fehreNNwYzoOa4loY kh/WS8LTB/fvt/2eH5BFbzW0BYIyr/mFpIubRe4U0EvtqMfPhysS7GmOl A==; X-CSE-ConnectionGUID: JvDeQZY+T5yob3WDa32ZXA== X-CSE-MsgGUID: aLLdW2cETlmyfJBYfMl6IA== X-IronPort-AV: E=McAfee;i="6800,10657,11467"; a="56026621" X-IronPort-AV: E=Sophos;i="6.16,243,1744095600"; d="scan'208";a="56026621" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jun 2025 07:00:02 -0700 X-CSE-ConnectionGUID: i15ZEAL8RnmLowW2w0pDRQ== X-CSE-MsgGUID: 0G+t6T5yTzyE6tQFi27Gjg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,243,1744095600"; d="scan'208";a="153739583" Received: from sannilnx-dsk.jer.intel.com ([10.12.231.107]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jun 2025 06:59:56 -0700 From: Alexander Usyskin To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Lucas De Marchi , =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= , Rodrigo Vivi , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Jani Nikula , Joonas Lahtinen , Tvrtko Ursulin , Karthik Poosa , Raag Jadav Cc: Reuven Abliyev , linux-mtd@lists.infradead.org, intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, Alexander Usyskin Subject: [PATCH v13 09/10] drm/xe/nvm: add support for access mode Date: Tue, 17 Jun 2025 16:45:31 +0300 Message-ID: <20250617134532.3768283-10-alexander.usyskin@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250617134532.3768283-1-alexander.usyskin@intel.com> References: <20250617134532.3768283-1-alexander.usyskin@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Check NVM access mode from GSC FW status registers and overwrite access status read from SPI descriptor, if needed. Reviewed-by: Rodrigo Vivi Acked-by: Rodrigo Vivi Signed-off-by: Alexander Usyskin --- drivers/gpu/drm/xe/regs/xe_gsc_regs.h | 4 +++ drivers/gpu/drm/xe/xe_heci_gsc.c | 5 +--- drivers/gpu/drm/xe/xe_nvm.c | 37 ++++++++++++++++++++++++++- 3 files changed, 41 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/xe/regs/xe_gsc_regs.h b/drivers/gpu/drm/xe/reg= s/xe_gsc_regs.h index 7702364b65f1..9b66cc972a63 100644 --- a/drivers/gpu/drm/xe/regs/xe_gsc_regs.h +++ b/drivers/gpu/drm/xe/regs/xe_gsc_regs.h @@ -16,6 +16,10 @@ #define MTL_GSC_HECI1_BASE 0x00116000 #define MTL_GSC_HECI2_BASE 0x00117000 =20 +#define DG1_GSC_HECI2_BASE 0x00259000 +#define PVC_GSC_HECI2_BASE 0x00285000 +#define DG2_GSC_HECI2_BASE 0x00374000 + #define HECI_H_CSR(base) XE_REG((base) + 0x4) #define HECI_H_CSR_IE REG_BIT(0) #define HECI_H_CSR_IS REG_BIT(1) diff --git a/drivers/gpu/drm/xe/xe_heci_gsc.c b/drivers/gpu/drm/xe/xe_heci_= gsc.c index 27d11e06a82b..6d7b62724126 100644 --- a/drivers/gpu/drm/xe/xe_heci_gsc.c +++ b/drivers/gpu/drm/xe/xe_heci_gsc.c @@ -11,15 +11,12 @@ #include "xe_device_types.h" #include "xe_drv.h" #include "xe_heci_gsc.h" +#include "regs/xe_gsc_regs.h" #include "xe_platform_types.h" #include "xe_survivability_mode.h" =20 #define GSC_BAR_LENGTH 0x00000FFC =20 -#define DG1_GSC_HECI2_BASE 0x259000 -#define PVC_GSC_HECI2_BASE 0x285000 -#define DG2_GSC_HECI2_BASE 0x374000 - static void heci_gsc_irq_mask(struct irq_data *d) { /* generic irq handling */ diff --git a/drivers/gpu/drm/xe/xe_nvm.c b/drivers/gpu/drm/xe/xe_nvm.c index 33ba635ce116..20aa3b5d3637 100644 --- a/drivers/gpu/drm/xe/xe_nvm.c +++ b/drivers/gpu/drm/xe/xe_nvm.c @@ -6,8 +6,11 @@ #include #include =20 +#include "xe_device.h" #include "xe_device_types.h" +#include "xe_mmio.h" #include "xe_nvm.h" +#include "regs/xe_gsc_regs.h" #include "xe_sriov.h" =20 #define GEN12_GUNIT_NVM_BASE 0x00102040 @@ -26,6 +29,38 @@ static void xe_nvm_release_dev(struct device *dev) { } =20 +static bool xe_nvm_writable_override(struct xe_device *xe) +{ + struct xe_gt *gt =3D xe_root_mmio_gt(xe); + bool writable_override; + resource_size_t base; + + switch (xe->info.platform) { + case XE_BATTLEMAGE: + base =3D DG2_GSC_HECI2_BASE; + break; + case XE_PVC: + base =3D PVC_GSC_HECI2_BASE; + break; + case XE_DG2: + base =3D DG2_GSC_HECI2_BASE; + break; + case XE_DG1: + base =3D DG1_GSC_HECI2_BASE; + break; + default: + drm_err(&xe->drm, "Unknown platform\n"); + return true; + } + + writable_override =3D + !(xe_mmio_read32(>->mmio, HECI_FWSTS2(base)) & + HECI_FW_STATUS_2_NVM_ACCESS_MODE); + if (writable_override) + drm_info(&xe->drm, "NVM access overridden by jumper\n"); + return writable_override; +} + int xe_nvm_init(struct xe_device *xe) { struct pci_dev *pdev =3D to_pci_dev(xe->drm.dev); @@ -50,7 +85,7 @@ int xe_nvm_init(struct xe_device *xe) =20 nvm =3D xe->nvm; =20 - nvm->writable_override =3D false; + nvm->writable_override =3D xe_nvm_writable_override(xe); nvm->bar.parent =3D &pdev->resource[0]; nvm->bar.start =3D GEN12_GUNIT_NVM_BASE + pdev->resource[0].start; nvm->bar.end =3D nvm->bar.start + GEN12_GUNIT_NVM_SIZE - 1; --=20 2.43.0