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[93.34.88.225]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-4532e24b0c8sm173809435e9.24.2025.06.17.06.05.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Jun 2025 06:05:28 -0700 (PDT) From: Christian Marangi To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Felix Fietkau , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Christian Marangi Subject: [PATCH v2 03/10] clk: en7523: convert to full clk_hw implementation Date: Tue, 17 Jun 2025 15:04:46 +0200 Message-ID: <20250617130455.32682-4-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250617130455.32682-1-ansuelsmth@gmail.com> References: <20250617130455.32682-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In preparation for support of .set_rate, convert the clock register logic from fixed clock implementation to full clk_hw implementation with dedicated OPs. This is just a rework and no behaviour change is expected. Signed-off-by: Christian Marangi --- drivers/clk/clk-en7523.c | 83 ++++++++++++++++++++++++++++------------ 1 file changed, 59 insertions(+), 24 deletions(-) diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c index b040f0f0d727..10fb0dcdc88b 100644 --- a/drivers/clk/clk-en7523.c +++ b/drivers/clk/clk-en7523.c @@ -69,6 +69,12 @@ struct en_clk_gate { struct clk_hw hw; }; =20 +struct en_clk { + struct regmap *map; + const struct en_clk_desc *desc; + struct clk_hw hw; +}; + struct en_rst_data { const u16 *bank_ofs; const u16 *idx_map; @@ -471,44 +477,73 @@ static struct clk_hw *en7523_register_pcie_clk(struct= device *dev, return &cg->hw; } =20 +static unsigned long en75xx_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct en_clk *c =3D container_of(hw, struct en_clk, hw); + const struct en_clk_desc *desc =3D c->desc; + struct regmap *map =3D c->map; + u32 val, reg; + u32 rate; + int err; + + err =3D regmap_read(map, desc->base_reg, &val); + if (err) { + pr_err("Failed reading fixed clk rate %s: %d\n", + desc->name, err); + return err; + } + rate =3D en7523_get_base_rate(desc, val); + + reg =3D desc->div_reg ? desc->div_reg : desc->base_reg; + err =3D regmap_read(map, reg, &val); + if (err) { + pr_err("Failed reading fixed clk div %s: %d\n", + desc->name, err); + return err; + } + + return rate / en7523_get_div(desc, val); +} + +static const struct clk_ops en75xx_clk_ops =3D { + .recalc_rate =3D en75xx_recalc_rate, +}; + static int en75xx_register_clocks(struct device *dev, const struct en_clk_soc_data *soc_data, struct clk_hw_onecell_data *clk_data, struct regmap *map, struct regmap *clk_map) { struct clk_hw *hw; - u32 rate; int i; =20 for (i =3D 0; i < soc_data->num_clocks - 1; i++) { const struct en_clk_desc *desc =3D &soc_data->base_clks[i]; - u32 val, reg =3D desc->div_reg ? desc->div_reg : desc->base_reg; + struct clk_init_data init =3D { + .ops =3D &en75xx_clk_ops, + }; + struct en_clk *en_clk; int err; =20 - err =3D regmap_read(map, desc->base_reg, &val); - if (err) { - pr_err("Failed reading fixed clk rate %s: %d\n", - desc->name, err); - return err; - } - rate =3D en7523_get_base_rate(desc, val); + en_clk =3D devm_kzalloc(dev, sizeof(*en_clk), GFP_KERNEL); + if (!en_clk) + return -ENOMEM; =20 - err =3D regmap_read(map, reg, &val); + init.name =3D desc->name; + + en_clk->map =3D map; + en_clk->desc =3D desc; + en_clk->hw.init =3D &init; + + err =3D devm_clk_hw_register(dev, &en_clk->hw); if (err) { - pr_err("Failed reading fixed clk div %s: %d\n", + pr_err("Failed to register clk %s: %d\n", desc->name, err); return err; } - rate /=3D en7523_get_div(desc, val); - - hw =3D clk_hw_register_fixed_rate(dev, desc->name, NULL, 0, rate); - if (IS_ERR(hw)) { - pr_err("Failed to register clk %s: %ld\n", - desc->name, PTR_ERR(hw)); - return PTR_ERR(hw); - } =20 - clk_data->hws[desc->id] =3D hw; + clk_data->hws[desc->id] =3D &en_clk->hw; } =20 hw =3D en7523_register_pcie_clk(dev, clk_map); @@ -672,7 +707,7 @@ static int en7581_clk_hw_init(struct platform_device *p= dev, { struct regmap *map, *clk_map; void __iomem *base; - int ret; + int err; =20 map =3D syscon_regmap_lookup_by_compatible("airoha,en7581-chip-scu"); if (IS_ERR(map)) @@ -686,9 +721,9 @@ static int en7581_clk_hw_init(struct platform_device *p= dev, if (IS_ERR(clk_map)) return PTR_ERR(clk_map); =20 - ret =3D en75xx_register_clocks(&pdev->dev, soc_data, clk_data, map, clk_m= ap); - if (ret) - return ret; + err =3D en75xx_register_clocks(&pdev->dev, soc_data, clk_data, map, clk_m= ap); + if (err) + return err; =20 regmap_clear_bits(clk_map, REG_NP_SCU_SSTR, REG_PCIE_XSI0_SEL_MASK | REG_PCIE_XSI1_SEL_MASK); --=20 2.48.1