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[93.34.88.225]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-4532e24b0c8sm173809435e9.24.2025.06.17.06.05.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Jun 2025 06:05:26 -0700 (PDT) From: Christian Marangi To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Felix Fietkau , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Christian Marangi Subject: [PATCH v2 02/10] clk: en7523: generalize register clocks function Date: Tue, 17 Jun 2025 15:04:45 +0200 Message-ID: <20250617130455.32682-3-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250617130455.32682-1-ansuelsmth@gmail.com> References: <20250617130455.32682-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Generalize register clocks function for Airoha EN7523 and EN7581 clocks driver. The same logic is applied for both clock hence code can be reduced and simplified by putting the base_clocks struct in the soc_data and passing that to a generic register clocks function. While at it rework some function to return error and use devm variant for clk_hw_regiser. Signed-off-by: Christian Marangi --- drivers/clk/clk-en7523.c | 148 +++++++++++++++++---------------------- 1 file changed, 66 insertions(+), 82 deletions(-) diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c index 314e7450313f..b040f0f0d727 100644 --- a/drivers/clk/clk-en7523.c +++ b/drivers/clk/clk-en7523.c @@ -78,8 +78,10 @@ struct en_rst_data { =20 struct en_clk_soc_data { u32 num_clocks; + const struct en_clk_desc *base_clks; const struct clk_ops pcie_ops; int (*hw_init)(struct platform_device *pdev, + const struct en_clk_soc_data *soc_data, struct clk_hw_onecell_data *clk_data); }; =20 @@ -450,10 +452,11 @@ static struct clk_hw *en7523_register_pcie_clk(struct= device *dev, .ops =3D &soc_data->pcie_ops, }; struct en_clk_gate *cg; + int err; =20 cg =3D devm_kzalloc(dev, sizeof(*cg), GFP_KERNEL); if (!cg) - return NULL; + return ERR_PTR(-ENOMEM); =20 cg->map =3D clk_map; cg->hw.init =3D &init; @@ -461,12 +464,62 @@ static struct clk_hw *en7523_register_pcie_clk(struct= device *dev, if (init.ops->unprepare) init.ops->unprepare(&cg->hw); =20 - if (clk_hw_register(dev, &cg->hw)) - return NULL; + err =3D devm_clk_hw_register(dev, &cg->hw); + if (err) + return ERR_PTR(err); =20 return &cg->hw; } =20 +static int en75xx_register_clocks(struct device *dev, + const struct en_clk_soc_data *soc_data, + struct clk_hw_onecell_data *clk_data, + struct regmap *map, struct regmap *clk_map) +{ + struct clk_hw *hw; + u32 rate; + int i; + + for (i =3D 0; i < soc_data->num_clocks - 1; i++) { + const struct en_clk_desc *desc =3D &soc_data->base_clks[i]; + u32 val, reg =3D desc->div_reg ? desc->div_reg : desc->base_reg; + int err; + + err =3D regmap_read(map, desc->base_reg, &val); + if (err) { + pr_err("Failed reading fixed clk rate %s: %d\n", + desc->name, err); + return err; + } + rate =3D en7523_get_base_rate(desc, val); + + err =3D regmap_read(map, reg, &val); + if (err) { + pr_err("Failed reading fixed clk div %s: %d\n", + desc->name, err); + return err; + } + rate /=3D en7523_get_div(desc, val); + + hw =3D clk_hw_register_fixed_rate(dev, desc->name, NULL, 0, rate); + if (IS_ERR(hw)) { + pr_err("Failed to register clk %s: %ld\n", + desc->name, PTR_ERR(hw)); + return PTR_ERR(hw); + } + + clk_data->hws[desc->id] =3D hw; + } + + hw =3D en7523_register_pcie_clk(dev, clk_map); + if (IS_ERR(hw)) + return PTR_ERR(hw); + + clk_data->hws[EN7523_CLK_PCIE] =3D hw; + + return 0; +} + static int en7581_pci_is_enabled(struct clk_hw *hw) { struct en_clk_gate *cg =3D container_of(hw, struct en_clk_gate, hw); @@ -504,38 +557,6 @@ static void en7581_pci_disable(struct clk_hw *hw) usleep_range(1000, 2000); } =20 -static void en7523_register_clocks(struct device *dev, struct clk_hw_onece= ll_data *clk_data, - struct regmap *map, struct regmap *clk_map) -{ - struct clk_hw *hw; - u32 rate; - int i; - - for (i =3D 0; i < ARRAY_SIZE(en7523_base_clks); i++) { - const struct en_clk_desc *desc =3D &en7523_base_clks[i]; - u32 reg =3D desc->div_reg ? desc->div_reg : desc->base_reg; - u32 val; - - regmap_read(map, desc->base_reg, &val); - - rate =3D en7523_get_base_rate(desc, val); - regmap_read(map, reg, &val); - rate /=3D en7523_get_div(desc, val); - - hw =3D clk_hw_register_fixed_rate(dev, desc->name, NULL, 0, rate); - if (IS_ERR(hw)) { - pr_err("Failed to register clk %s: %ld\n", - desc->name, PTR_ERR(hw)); - continue; - } - - clk_data->hws[desc->id] =3D hw; - } - - hw =3D en7523_register_pcie_clk(dev, clk_map); - clk_data->hws[EN7523_CLK_PCIE] =3D hw; -} - static const struct regmap_config en7523_clk_regmap_config =3D { .reg_bits =3D 32, .val_bits =3D 32, @@ -543,6 +564,7 @@ static const struct regmap_config en7523_clk_regmap_con= fig =3D { }; =20 static int en7523_clk_hw_init(struct platform_device *pdev, + const struct en_clk_soc_data *soc_data, struct clk_hw_onecell_data *clk_data) { void __iomem *base, *np_base; @@ -566,51 +588,7 @@ static int en7523_clk_hw_init(struct platform_device *= pdev, if (IS_ERR(clk_map)) return PTR_ERR(clk_map); =20 - en7523_register_clocks(&pdev->dev, clk_data, map, clk_map); - - return 0; -} - -static void en7581_register_clocks(struct device *dev, struct clk_hw_onece= ll_data *clk_data, - struct regmap *map, struct regmap *clk_map) -{ - struct clk_hw *hw; - u32 rate; - int i; - - for (i =3D 0; i < ARRAY_SIZE(en7581_base_clks); i++) { - const struct en_clk_desc *desc =3D &en7581_base_clks[i]; - u32 val, reg =3D desc->div_reg ? desc->div_reg : desc->base_reg; - int err; - - err =3D regmap_read(map, desc->base_reg, &val); - if (err) { - pr_err("Failed reading fixed clk rate %s: %d\n", - desc->name, err); - continue; - } - rate =3D en7523_get_base_rate(desc, val); - - err =3D regmap_read(map, reg, &val); - if (err) { - pr_err("Failed reading fixed clk div %s: %d\n", - desc->name, err); - continue; - } - rate /=3D en7523_get_div(desc, val); - - hw =3D clk_hw_register_fixed_rate(dev, desc->name, NULL, 0, rate); - if (IS_ERR(hw)) { - pr_err("Failed to register clk %s: %ld\n", - desc->name, PTR_ERR(hw)); - continue; - } - - clk_data->hws[desc->id] =3D hw; - } - - hw =3D en7523_register_pcie_clk(dev, clk_map); - clk_data->hws[EN7523_CLK_PCIE] =3D hw; + return en75xx_register_clocks(&pdev->dev, soc_data, clk_data, map, clk_ma= p); } =20 static int en7523_reset_update(struct reset_controller_dev *rcdev, @@ -689,10 +667,12 @@ static int en7581_reset_register(struct device *dev, = struct regmap *map) } =20 static int en7581_clk_hw_init(struct platform_device *pdev, + const struct en_clk_soc_data *soc_data, struct clk_hw_onecell_data *clk_data) { struct regmap *map, *clk_map; void __iomem *base; + int ret; =20 map =3D syscon_regmap_lookup_by_compatible("airoha,en7581-chip-scu"); if (IS_ERR(map)) @@ -706,7 +686,9 @@ static int en7581_clk_hw_init(struct platform_device *p= dev, if (IS_ERR(clk_map)) return PTR_ERR(clk_map); =20 - en7581_register_clocks(&pdev->dev, clk_data, map, clk_map); + ret =3D en75xx_register_clocks(&pdev->dev, soc_data, clk_data, map, clk_m= ap); + if (ret) + return ret; =20 regmap_clear_bits(clk_map, REG_NP_SCU_SSTR, REG_PCIE_XSI0_SEL_MASK | REG_PCIE_XSI1_SEL_MASK); @@ -732,7 +714,7 @@ static int en7523_clk_probe(struct platform_device *pde= v) return -ENOMEM; =20 clk_data->num =3D soc_data->num_clocks; - r =3D soc_data->hw_init(pdev, clk_data); + r =3D soc_data->hw_init(pdev, soc_data, clk_data); if (r) return r; =20 @@ -740,6 +722,7 @@ static int en7523_clk_probe(struct platform_device *pde= v) } =20 static const struct en_clk_soc_data en7523_data =3D { + .base_clks =3D en7523_base_clks, .num_clocks =3D ARRAY_SIZE(en7523_base_clks) + 1, .pcie_ops =3D { .is_enabled =3D en7523_pci_is_enabled, @@ -750,6 +733,7 @@ static const struct en_clk_soc_data en7523_data =3D { }; =20 static const struct en_clk_soc_data en7581_data =3D { + .base_clks =3D en7581_base_clks, /* We increment num_clocks by 1 to account for additional PCIe clock */ .num_clocks =3D ARRAY_SIZE(en7581_base_clks) + 1, .pcie_ops =3D { --=20 2.48.1