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[93.34.88.225]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-4532e24b0c8sm173809435e9.24.2025.06.17.06.05.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Jun 2025 06:05:24 -0700 (PDT) From: Christian Marangi To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Felix Fietkau , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Christian Marangi Subject: [PATCH v2 01/10] clk: en7523: convert driver to regmap API Date: Tue, 17 Jun 2025 15:04:44 +0200 Message-ID: <20250617130455.32682-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250617130455.32682-1-ansuelsmth@gmail.com> References: <20250617130455.32682-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Convert driver to regmap API, in preparation for support of Airoha AN7523 as the SCU will be an MFD and the regmap will be provided in the parent node. Signed-off-by: Christian Marangi --- drivers/clk/clk-en7523.c | 137 ++++++++++++++++++++++----------------- 1 file changed, 76 insertions(+), 61 deletions(-) diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c index 15bbdeb60b8e..314e7450313f 100644 --- a/drivers/clk/clk-en7523.c +++ b/drivers/clk/clk-en7523.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only =20 +#include #include #include #include @@ -34,6 +35,7 @@ #define REG_RESET_CONTROL_PCIE2 BIT(26) /* EN7581 */ #define REG_NP_SCU_PCIC 0x88 +#define REG_PCIE_CTRL GENMASK(7, 0) #define REG_NP_SCU_SSTR 0x9c #define REG_PCIE_XSI0_SEL_MASK GENMASK(14, 13) #define REG_PCIE_XSI1_SEL_MASK GENMASK(12, 11) @@ -63,14 +65,14 @@ struct en_clk_desc { }; =20 struct en_clk_gate { - void __iomem *base; + struct regmap *map; struct clk_hw hw; }; =20 struct en_rst_data { const u16 *bank_ofs; const u16 *idx_map; - void __iomem *base; + struct regmap *map; struct reset_controller_dev rcdev; }; =20 @@ -388,44 +390,44 @@ static u32 en7523_get_div(const struct en_clk_desc *d= esc, u32 val) static int en7523_pci_is_enabled(struct clk_hw *hw) { struct en_clk_gate *cg =3D container_of(hw, struct en_clk_gate, hw); + u32 val; =20 - return !!(readl(cg->base + REG_PCI_CONTROL) & REG_PCI_CONTROL_REFCLK_EN1); + regmap_read(cg->map, REG_PCI_CONTROL, &val); + return !!(val & REG_PCI_CONTROL_REFCLK_EN1); } =20 static int en7523_pci_prepare(struct clk_hw *hw) { struct en_clk_gate *cg =3D container_of(hw, struct en_clk_gate, hw); - void __iomem *np_base =3D cg->base; - u32 val, mask; + struct regmap *map =3D cg->map; + u32 mask; =20 /* Need to pull device low before reset */ - val =3D readl(np_base + REG_PCI_CONTROL); - val &=3D ~(REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT); - writel(val, np_base + REG_PCI_CONTROL); + regmap_clear_bits(map, REG_PCI_CONTROL, + REG_PCI_CONTROL_PERSTOUT1 | + REG_PCI_CONTROL_PERSTOUT); usleep_range(1000, 2000); =20 /* Enable PCIe port 1 */ - val |=3D REG_PCI_CONTROL_REFCLK_EN1; - writel(val, np_base + REG_PCI_CONTROL); + regmap_set_bits(map, REG_PCI_CONTROL, + REG_PCI_CONTROL_REFCLK_EN1); usleep_range(1000, 2000); =20 /* Reset to default */ - val =3D readl(np_base + REG_RESET_CONTROL1); mask =3D REG_RESET_CONTROL_PCIE1 | REG_RESET_CONTROL_PCIE2 | REG_RESET_CONTROL_PCIEHB; - writel(val & ~mask, np_base + REG_RESET_CONTROL1); + regmap_clear_bits(map, REG_RESET_CONTROL1, mask); usleep_range(1000, 2000); - writel(val | mask, np_base + REG_RESET_CONTROL1); + regmap_set_bits(map, REG_RESET_CONTROL1, mask); msleep(100); - writel(val & ~mask, np_base + REG_RESET_CONTROL1); + regmap_clear_bits(map, REG_RESET_CONTROL1, mask); usleep_range(5000, 10000); =20 /* Release device */ mask =3D REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT; - val =3D readl(np_base + REG_PCI_CONTROL); - writel(val & ~mask, np_base + REG_PCI_CONTROL); + regmap_clear_bits(map, REG_PCI_CONTROL, mask); usleep_range(1000, 2000); - writel(val | mask, np_base + REG_PCI_CONTROL); + regmap_set_bits(map, REG_PCI_CONTROL, mask); msleep(250); =20 return 0; @@ -434,16 +436,13 @@ static int en7523_pci_prepare(struct clk_hw *hw) static void en7523_pci_unprepare(struct clk_hw *hw) { struct en_clk_gate *cg =3D container_of(hw, struct en_clk_gate, hw); - void __iomem *np_base =3D cg->base; - u32 val; + struct regmap *map =3D cg->map; =20 - val =3D readl(np_base + REG_PCI_CONTROL); - val &=3D ~REG_PCI_CONTROL_REFCLK_EN1; - writel(val, np_base + REG_PCI_CONTROL); + regmap_clear_bits(map, REG_PCI_CONTROL, REG_PCI_CONTROL_REFCLK_EN1); } =20 static struct clk_hw *en7523_register_pcie_clk(struct device *dev, - void __iomem *np_base) + struct regmap *clk_map) { const struct en_clk_soc_data *soc_data =3D device_get_match_data(dev); struct clk_init_data init =3D { @@ -456,7 +455,7 @@ static struct clk_hw *en7523_register_pcie_clk(struct d= evice *dev, if (!cg) return NULL; =20 - cg->base =3D np_base; + cg->map =3D clk_map; cg->hw.init =3D &init; =20 if (init.ops->unprepare) @@ -474,21 +473,20 @@ static int en7581_pci_is_enabled(struct clk_hw *hw) u32 val, mask; =20 mask =3D REG_PCI_CONTROL_REFCLK_EN0 | REG_PCI_CONTROL_REFCLK_EN1; - val =3D readl(cg->base + REG_PCI_CONTROL); + regmap_read(cg->map, REG_PCI_CONTROL, &val); return (val & mask) =3D=3D mask; } =20 static int en7581_pci_enable(struct clk_hw *hw) { struct en_clk_gate *cg =3D container_of(hw, struct en_clk_gate, hw); - void __iomem *np_base =3D cg->base; - u32 val, mask; + struct regmap *map =3D cg->map; + u32 mask; =20 mask =3D REG_PCI_CONTROL_REFCLK_EN0 | REG_PCI_CONTROL_REFCLK_EN1 | REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT2 | REG_PCI_CONTROL_PERSTOUT; - val =3D readl(np_base + REG_PCI_CONTROL); - writel(val | mask, np_base + REG_PCI_CONTROL); + regmap_set_bits(map, REG_PCI_CONTROL, mask); =20 return 0; } @@ -496,19 +494,18 @@ static int en7581_pci_enable(struct clk_hw *hw) static void en7581_pci_disable(struct clk_hw *hw) { struct en_clk_gate *cg =3D container_of(hw, struct en_clk_gate, hw); - void __iomem *np_base =3D cg->base; - u32 val, mask; + struct regmap *map =3D cg->map; + u32 mask; =20 mask =3D REG_PCI_CONTROL_REFCLK_EN0 | REG_PCI_CONTROL_REFCLK_EN1 | REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT2 | REG_PCI_CONTROL_PERSTOUT; - val =3D readl(np_base + REG_PCI_CONTROL); - writel(val & ~mask, np_base + REG_PCI_CONTROL); + regmap_clear_bits(map, REG_PCI_CONTROL, mask); usleep_range(1000, 2000); } =20 static void en7523_register_clocks(struct device *dev, struct clk_hw_onece= ll_data *clk_data, - void __iomem *base, void __iomem *np_base) + struct regmap *map, struct regmap *clk_map) { struct clk_hw *hw; u32 rate; @@ -517,10 +514,12 @@ static void en7523_register_clocks(struct device *dev= , struct clk_hw_onecell_dat for (i =3D 0; i < ARRAY_SIZE(en7523_base_clks); i++) { const struct en_clk_desc *desc =3D &en7523_base_clks[i]; u32 reg =3D desc->div_reg ? desc->div_reg : desc->base_reg; - u32 val =3D readl(base + desc->base_reg); + u32 val; + + regmap_read(map, desc->base_reg, &val); =20 rate =3D en7523_get_base_rate(desc, val); - val =3D readl(base + reg); + regmap_read(map, reg, &val); rate /=3D en7523_get_div(desc, val); =20 hw =3D clk_hw_register_fixed_rate(dev, desc->name, NULL, 0, rate); @@ -533,30 +532,47 @@ static void en7523_register_clocks(struct device *dev= , struct clk_hw_onecell_dat clk_data->hws[desc->id] =3D hw; } =20 - hw =3D en7523_register_pcie_clk(dev, np_base); + hw =3D en7523_register_pcie_clk(dev, clk_map); clk_data->hws[EN7523_CLK_PCIE] =3D hw; } =20 +static const struct regmap_config en7523_clk_regmap_config =3D { + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_stride =3D 4, +}; + static int en7523_clk_hw_init(struct platform_device *pdev, struct clk_hw_onecell_data *clk_data) { void __iomem *base, *np_base; + struct regmap *map, *clk_map; =20 base =3D devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(base)) return PTR_ERR(base); =20 + map =3D devm_regmap_init_mmio(&pdev->dev, base, + &en7523_clk_regmap_config); + if (IS_ERR(map)) + return PTR_ERR(map); + np_base =3D devm_platform_ioremap_resource(pdev, 1); if (IS_ERR(np_base)) return PTR_ERR(np_base); =20 - en7523_register_clocks(&pdev->dev, clk_data, base, np_base); + clk_map =3D devm_regmap_init_mmio(&pdev->dev, np_base, + &en7523_clk_regmap_config); + if (IS_ERR(clk_map)) + return PTR_ERR(clk_map); + + en7523_register_clocks(&pdev->dev, clk_data, map, clk_map); =20 return 0; } =20 static void en7581_register_clocks(struct device *dev, struct clk_hw_onece= ll_data *clk_data, - struct regmap *map, void __iomem *base) + struct regmap *map, struct regmap *clk_map) { struct clk_hw *hw; u32 rate; @@ -593,7 +609,7 @@ static void en7581_register_clocks(struct device *dev, = struct clk_hw_onecell_dat clk_data->hws[desc->id] =3D hw; } =20 - hw =3D en7523_register_pcie_clk(dev, base); + hw =3D en7523_register_pcie_clk(dev, clk_map); clk_data->hws[EN7523_CLK_PCIE] =3D hw; } =20 @@ -601,15 +617,10 @@ static int en7523_reset_update(struct reset_controlle= r_dev *rcdev, unsigned long id, bool assert) { struct en_rst_data *rst_data =3D container_of(rcdev, struct en_rst_data, = rcdev); - void __iomem *addr =3D rst_data->base + rst_data->bank_ofs[id / RST_NR_PE= R_BANK]; - u32 val; + u32 addr =3D rst_data->bank_ofs[id / RST_NR_PER_BANK]; =20 - val =3D readl(addr); - if (assert) - val |=3D BIT(id % RST_NR_PER_BANK); - else - val &=3D ~BIT(id % RST_NR_PER_BANK); - writel(val, addr); + regmap_update_bits(rst_data->map, addr, BIT(id % RST_NR_PER_BANK), + assert ? BIT(id % RST_NR_PER_BANK) : 0); =20 return 0; } @@ -630,9 +641,11 @@ static int en7523_reset_status(struct reset_controller= _dev *rcdev, unsigned long id) { struct en_rst_data *rst_data =3D container_of(rcdev, struct en_rst_data, = rcdev); - void __iomem *addr =3D rst_data->base + rst_data->bank_ofs[id / RST_NR_PE= R_BANK]; + u32 addr =3D rst_data->bank_ofs[id / RST_NR_PER_BANK]; + u32 val; =20 - return !!(readl(addr) & BIT(id % RST_NR_PER_BANK)); + regmap_read(rst_data->map, addr, &val); + return !!(val & BIT(id % RST_NR_PER_BANK)); } =20 static int en7523_reset_xlate(struct reset_controller_dev *rcdev, @@ -652,7 +665,7 @@ static const struct reset_control_ops en7581_reset_ops = =3D { .status =3D en7523_reset_status, }; =20 -static int en7581_reset_register(struct device *dev, void __iomem *base) +static int en7581_reset_register(struct device *dev, struct regmap *map) { struct en_rst_data *rst_data; =20 @@ -662,7 +675,7 @@ static int en7581_reset_register(struct device *dev, vo= id __iomem *base) =20 rst_data->bank_ofs =3D en7581_rst_ofs; rst_data->idx_map =3D en7581_rst_map; - rst_data->base =3D base; + rst_data->map =3D map; =20 rst_data->rcdev.nr_resets =3D ARRAY_SIZE(en7581_rst_map); rst_data->rcdev.of_xlate =3D en7523_reset_xlate; @@ -678,9 +691,8 @@ static int en7581_reset_register(struct device *dev, vo= id __iomem *base) static int en7581_clk_hw_init(struct platform_device *pdev, struct clk_hw_onecell_data *clk_data) { - struct regmap *map; + struct regmap *map, *clk_map; void __iomem *base; - u32 val; =20 map =3D syscon_regmap_lookup_by_compatible("airoha,en7581-chip-scu"); if (IS_ERR(map)) @@ -690,15 +702,18 @@ static int en7581_clk_hw_init(struct platform_device = *pdev, if (IS_ERR(base)) return PTR_ERR(base); =20 - en7581_register_clocks(&pdev->dev, clk_data, map, base); + clk_map =3D devm_regmap_init_mmio(&pdev->dev, base, &en7523_clk_regmap_co= nfig); + if (IS_ERR(clk_map)) + return PTR_ERR(clk_map); + + en7581_register_clocks(&pdev->dev, clk_data, map, clk_map); =20 - val =3D readl(base + REG_NP_SCU_SSTR); - val &=3D ~(REG_PCIE_XSI0_SEL_MASK | REG_PCIE_XSI1_SEL_MASK); - writel(val, base + REG_NP_SCU_SSTR); - val =3D readl(base + REG_NP_SCU_PCIC); - writel(val | 3, base + REG_NP_SCU_PCIC); + regmap_clear_bits(clk_map, REG_NP_SCU_SSTR, + REG_PCIE_XSI0_SEL_MASK | REG_PCIE_XSI1_SEL_MASK); + regmap_update_bits(clk_map, REG_NP_SCU_PCIC, REG_PCIE_CTRL, + FIELD_PREP(REG_PCIE_CTRL, 3)); =20 - return en7581_reset_register(&pdev->dev, base); + return en7581_reset_register(&pdev->dev, clk_map); } =20 static int en7523_clk_probe(struct platform_device *pdev) --=20 2.48.1