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[93.34.88.225]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-4532e24b0c8sm173809435e9.24.2025.06.17.06.05.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Jun 2025 06:05:24 -0700 (PDT) From: Christian Marangi To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Felix Fietkau , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Christian Marangi Subject: [PATCH v2 01/10] clk: en7523: convert driver to regmap API Date: Tue, 17 Jun 2025 15:04:44 +0200 Message-ID: <20250617130455.32682-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250617130455.32682-1-ansuelsmth@gmail.com> References: <20250617130455.32682-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Convert driver to regmap API, in preparation for support of Airoha AN7523 as the SCU will be an MFD and the regmap will be provided in the parent node. Signed-off-by: Christian Marangi --- drivers/clk/clk-en7523.c | 137 ++++++++++++++++++++++----------------- 1 file changed, 76 insertions(+), 61 deletions(-) diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c index 15bbdeb60b8e..314e7450313f 100644 --- a/drivers/clk/clk-en7523.c +++ b/drivers/clk/clk-en7523.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only =20 +#include #include #include #include @@ -34,6 +35,7 @@ #define REG_RESET_CONTROL_PCIE2 BIT(26) /* EN7581 */ #define REG_NP_SCU_PCIC 0x88 +#define REG_PCIE_CTRL GENMASK(7, 0) #define REG_NP_SCU_SSTR 0x9c #define REG_PCIE_XSI0_SEL_MASK GENMASK(14, 13) #define REG_PCIE_XSI1_SEL_MASK GENMASK(12, 11) @@ -63,14 +65,14 @@ struct en_clk_desc { }; =20 struct en_clk_gate { - void __iomem *base; + struct regmap *map; struct clk_hw hw; }; =20 struct en_rst_data { const u16 *bank_ofs; const u16 *idx_map; - void __iomem *base; + struct regmap *map; struct reset_controller_dev rcdev; }; =20 @@ -388,44 +390,44 @@ static u32 en7523_get_div(const struct en_clk_desc *d= esc, u32 val) static int en7523_pci_is_enabled(struct clk_hw *hw) { struct en_clk_gate *cg =3D container_of(hw, struct en_clk_gate, hw); + u32 val; =20 - return !!(readl(cg->base + REG_PCI_CONTROL) & REG_PCI_CONTROL_REFCLK_EN1); + regmap_read(cg->map, REG_PCI_CONTROL, &val); + return !!(val & REG_PCI_CONTROL_REFCLK_EN1); } =20 static int en7523_pci_prepare(struct clk_hw *hw) { struct en_clk_gate *cg =3D container_of(hw, struct en_clk_gate, hw); - void __iomem *np_base =3D cg->base; - u32 val, mask; + struct regmap *map =3D cg->map; + u32 mask; =20 /* Need to pull device low before reset */ - val =3D readl(np_base + REG_PCI_CONTROL); - val &=3D ~(REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT); - writel(val, np_base + REG_PCI_CONTROL); + regmap_clear_bits(map, REG_PCI_CONTROL, + REG_PCI_CONTROL_PERSTOUT1 | + REG_PCI_CONTROL_PERSTOUT); usleep_range(1000, 2000); =20 /* Enable PCIe port 1 */ - val |=3D REG_PCI_CONTROL_REFCLK_EN1; - writel(val, np_base + REG_PCI_CONTROL); + regmap_set_bits(map, REG_PCI_CONTROL, + REG_PCI_CONTROL_REFCLK_EN1); usleep_range(1000, 2000); =20 /* Reset to default */ - val =3D readl(np_base + REG_RESET_CONTROL1); mask =3D REG_RESET_CONTROL_PCIE1 | REG_RESET_CONTROL_PCIE2 | REG_RESET_CONTROL_PCIEHB; - writel(val & ~mask, np_base + REG_RESET_CONTROL1); + regmap_clear_bits(map, REG_RESET_CONTROL1, mask); usleep_range(1000, 2000); - writel(val | mask, np_base + REG_RESET_CONTROL1); + regmap_set_bits(map, REG_RESET_CONTROL1, mask); msleep(100); - writel(val & ~mask, np_base + REG_RESET_CONTROL1); + regmap_clear_bits(map, REG_RESET_CONTROL1, mask); usleep_range(5000, 10000); =20 /* Release device */ mask =3D REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT; - val =3D readl(np_base + REG_PCI_CONTROL); - writel(val & ~mask, np_base + REG_PCI_CONTROL); + regmap_clear_bits(map, REG_PCI_CONTROL, mask); usleep_range(1000, 2000); - writel(val | mask, np_base + REG_PCI_CONTROL); + regmap_set_bits(map, REG_PCI_CONTROL, mask); msleep(250); =20 return 0; @@ -434,16 +436,13 @@ static int en7523_pci_prepare(struct clk_hw *hw) static void en7523_pci_unprepare(struct clk_hw *hw) { struct en_clk_gate *cg =3D container_of(hw, struct en_clk_gate, hw); - void __iomem *np_base =3D cg->base; - u32 val; + struct regmap *map =3D cg->map; =20 - val =3D readl(np_base + REG_PCI_CONTROL); - val &=3D ~REG_PCI_CONTROL_REFCLK_EN1; - writel(val, np_base + REG_PCI_CONTROL); + regmap_clear_bits(map, REG_PCI_CONTROL, REG_PCI_CONTROL_REFCLK_EN1); } =20 static struct clk_hw *en7523_register_pcie_clk(struct device *dev, - void __iomem *np_base) + struct regmap *clk_map) { const struct en_clk_soc_data *soc_data =3D device_get_match_data(dev); struct clk_init_data init =3D { @@ -456,7 +455,7 @@ static struct clk_hw *en7523_register_pcie_clk(struct d= evice *dev, if (!cg) return NULL; =20 - cg->base =3D np_base; + cg->map =3D clk_map; cg->hw.init =3D &init; =20 if (init.ops->unprepare) @@ -474,21 +473,20 @@ static int en7581_pci_is_enabled(struct clk_hw *hw) u32 val, mask; =20 mask =3D REG_PCI_CONTROL_REFCLK_EN0 | REG_PCI_CONTROL_REFCLK_EN1; - val =3D readl(cg->base + REG_PCI_CONTROL); + regmap_read(cg->map, REG_PCI_CONTROL, &val); return (val & mask) =3D=3D mask; } =20 static int en7581_pci_enable(struct clk_hw *hw) { struct en_clk_gate *cg =3D container_of(hw, struct en_clk_gate, hw); - void __iomem *np_base =3D cg->base; - u32 val, mask; + struct regmap *map =3D cg->map; + u32 mask; =20 mask =3D REG_PCI_CONTROL_REFCLK_EN0 | REG_PCI_CONTROL_REFCLK_EN1 | REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT2 | REG_PCI_CONTROL_PERSTOUT; - val =3D readl(np_base + REG_PCI_CONTROL); - writel(val | mask, np_base + REG_PCI_CONTROL); + regmap_set_bits(map, REG_PCI_CONTROL, mask); =20 return 0; } @@ -496,19 +494,18 @@ static int en7581_pci_enable(struct clk_hw *hw) static void en7581_pci_disable(struct clk_hw *hw) { struct en_clk_gate *cg =3D container_of(hw, struct en_clk_gate, hw); - void __iomem *np_base =3D cg->base; - u32 val, mask; + struct regmap *map =3D cg->map; + u32 mask; =20 mask =3D REG_PCI_CONTROL_REFCLK_EN0 | REG_PCI_CONTROL_REFCLK_EN1 | REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT2 | REG_PCI_CONTROL_PERSTOUT; - val =3D readl(np_base + REG_PCI_CONTROL); - writel(val & ~mask, np_base + REG_PCI_CONTROL); + regmap_clear_bits(map, REG_PCI_CONTROL, mask); usleep_range(1000, 2000); } =20 static void en7523_register_clocks(struct device *dev, struct clk_hw_onece= ll_data *clk_data, - void __iomem *base, void __iomem *np_base) + struct regmap *map, struct regmap *clk_map) { struct clk_hw *hw; u32 rate; @@ -517,10 +514,12 @@ static void en7523_register_clocks(struct device *dev= , struct clk_hw_onecell_dat for (i =3D 0; i < ARRAY_SIZE(en7523_base_clks); i++) { const struct en_clk_desc *desc =3D &en7523_base_clks[i]; u32 reg =3D desc->div_reg ? desc->div_reg : desc->base_reg; - u32 val =3D readl(base + desc->base_reg); + u32 val; + + regmap_read(map, desc->base_reg, &val); =20 rate =3D en7523_get_base_rate(desc, val); - val =3D readl(base + reg); + regmap_read(map, reg, &val); rate /=3D en7523_get_div(desc, val); =20 hw =3D clk_hw_register_fixed_rate(dev, desc->name, NULL, 0, rate); @@ -533,30 +532,47 @@ static void en7523_register_clocks(struct device *dev= , struct clk_hw_onecell_dat clk_data->hws[desc->id] =3D hw; } =20 - hw =3D en7523_register_pcie_clk(dev, np_base); + hw =3D en7523_register_pcie_clk(dev, clk_map); clk_data->hws[EN7523_CLK_PCIE] =3D hw; } =20 +static const struct regmap_config en7523_clk_regmap_config =3D { + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_stride =3D 4, +}; + static int en7523_clk_hw_init(struct platform_device *pdev, struct clk_hw_onecell_data *clk_data) { void __iomem *base, *np_base; + struct regmap *map, *clk_map; =20 base =3D devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(base)) return PTR_ERR(base); =20 + map =3D devm_regmap_init_mmio(&pdev->dev, base, + &en7523_clk_regmap_config); + if (IS_ERR(map)) + return PTR_ERR(map); + np_base =3D devm_platform_ioremap_resource(pdev, 1); if (IS_ERR(np_base)) return PTR_ERR(np_base); =20 - en7523_register_clocks(&pdev->dev, clk_data, base, np_base); + clk_map =3D devm_regmap_init_mmio(&pdev->dev, np_base, + &en7523_clk_regmap_config); + if (IS_ERR(clk_map)) + return PTR_ERR(clk_map); + + en7523_register_clocks(&pdev->dev, clk_data, map, clk_map); =20 return 0; } =20 static void en7581_register_clocks(struct device *dev, struct clk_hw_onece= ll_data *clk_data, - struct regmap *map, void __iomem *base) + struct regmap *map, struct regmap *clk_map) { struct clk_hw *hw; u32 rate; @@ -593,7 +609,7 @@ static void en7581_register_clocks(struct device *dev, = struct clk_hw_onecell_dat clk_data->hws[desc->id] =3D hw; } =20 - hw =3D en7523_register_pcie_clk(dev, base); + hw =3D en7523_register_pcie_clk(dev, clk_map); clk_data->hws[EN7523_CLK_PCIE] =3D hw; } =20 @@ -601,15 +617,10 @@ static int en7523_reset_update(struct reset_controlle= r_dev *rcdev, unsigned long id, bool assert) { struct en_rst_data *rst_data =3D container_of(rcdev, struct en_rst_data, = rcdev); - void __iomem *addr =3D rst_data->base + rst_data->bank_ofs[id / RST_NR_PE= R_BANK]; - u32 val; + u32 addr =3D rst_data->bank_ofs[id / RST_NR_PER_BANK]; =20 - val =3D readl(addr); - if (assert) - val |=3D BIT(id % RST_NR_PER_BANK); - else - val &=3D ~BIT(id % RST_NR_PER_BANK); - writel(val, addr); + regmap_update_bits(rst_data->map, addr, BIT(id % RST_NR_PER_BANK), + assert ? BIT(id % RST_NR_PER_BANK) : 0); =20 return 0; } @@ -630,9 +641,11 @@ static int en7523_reset_status(struct reset_controller= _dev *rcdev, unsigned long id) { struct en_rst_data *rst_data =3D container_of(rcdev, struct en_rst_data, = rcdev); - void __iomem *addr =3D rst_data->base + rst_data->bank_ofs[id / RST_NR_PE= R_BANK]; + u32 addr =3D rst_data->bank_ofs[id / RST_NR_PER_BANK]; + u32 val; =20 - return !!(readl(addr) & BIT(id % RST_NR_PER_BANK)); + regmap_read(rst_data->map, addr, &val); + return !!(val & BIT(id % RST_NR_PER_BANK)); } =20 static int en7523_reset_xlate(struct reset_controller_dev *rcdev, @@ -652,7 +665,7 @@ static const struct reset_control_ops en7581_reset_ops = =3D { .status =3D en7523_reset_status, }; =20 -static int en7581_reset_register(struct device *dev, void __iomem *base) +static int en7581_reset_register(struct device *dev, struct regmap *map) { struct en_rst_data *rst_data; =20 @@ -662,7 +675,7 @@ static int en7581_reset_register(struct device *dev, vo= id __iomem *base) =20 rst_data->bank_ofs =3D en7581_rst_ofs; rst_data->idx_map =3D en7581_rst_map; - rst_data->base =3D base; + rst_data->map =3D map; =20 rst_data->rcdev.nr_resets =3D ARRAY_SIZE(en7581_rst_map); rst_data->rcdev.of_xlate =3D en7523_reset_xlate; @@ -678,9 +691,8 @@ static int en7581_reset_register(struct device *dev, vo= id __iomem *base) static int en7581_clk_hw_init(struct platform_device *pdev, struct clk_hw_onecell_data *clk_data) { - struct regmap *map; + struct regmap *map, *clk_map; void __iomem *base; - u32 val; =20 map =3D syscon_regmap_lookup_by_compatible("airoha,en7581-chip-scu"); if (IS_ERR(map)) @@ -690,15 +702,18 @@ static int en7581_clk_hw_init(struct platform_device = *pdev, if (IS_ERR(base)) return PTR_ERR(base); =20 - en7581_register_clocks(&pdev->dev, clk_data, map, base); + clk_map =3D devm_regmap_init_mmio(&pdev->dev, base, &en7523_clk_regmap_co= nfig); + if (IS_ERR(clk_map)) + return PTR_ERR(clk_map); + + en7581_register_clocks(&pdev->dev, clk_data, map, clk_map); =20 - val =3D readl(base + REG_NP_SCU_SSTR); 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[93.34.88.225]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-4532e24b0c8sm173809435e9.24.2025.06.17.06.05.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Jun 2025 06:05:26 -0700 (PDT) From: Christian Marangi To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Felix Fietkau , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Christian Marangi Subject: [PATCH v2 02/10] clk: en7523: generalize register clocks function Date: Tue, 17 Jun 2025 15:04:45 +0200 Message-ID: <20250617130455.32682-3-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250617130455.32682-1-ansuelsmth@gmail.com> References: <20250617130455.32682-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Generalize register clocks function for Airoha EN7523 and EN7581 clocks driver. The same logic is applied for both clock hence code can be reduced and simplified by putting the base_clocks struct in the soc_data and passing that to a generic register clocks function. While at it rework some function to return error and use devm variant for clk_hw_regiser. Signed-off-by: Christian Marangi --- drivers/clk/clk-en7523.c | 148 +++++++++++++++++---------------------- 1 file changed, 66 insertions(+), 82 deletions(-) diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c index 314e7450313f..b040f0f0d727 100644 --- a/drivers/clk/clk-en7523.c +++ b/drivers/clk/clk-en7523.c @@ -78,8 +78,10 @@ struct en_rst_data { =20 struct en_clk_soc_data { u32 num_clocks; + const struct en_clk_desc *base_clks; const struct clk_ops pcie_ops; int (*hw_init)(struct platform_device *pdev, + const struct en_clk_soc_data *soc_data, struct clk_hw_onecell_data *clk_data); }; =20 @@ -450,10 +452,11 @@ static struct clk_hw *en7523_register_pcie_clk(struct= device *dev, .ops =3D &soc_data->pcie_ops, }; struct en_clk_gate *cg; + int err; =20 cg =3D devm_kzalloc(dev, sizeof(*cg), GFP_KERNEL); if (!cg) - return NULL; + return ERR_PTR(-ENOMEM); =20 cg->map =3D clk_map; cg->hw.init =3D &init; @@ -461,12 +464,62 @@ static struct clk_hw *en7523_register_pcie_clk(struct= device *dev, if (init.ops->unprepare) init.ops->unprepare(&cg->hw); =20 - if (clk_hw_register(dev, &cg->hw)) - return NULL; + err =3D devm_clk_hw_register(dev, &cg->hw); + if (err) + return ERR_PTR(err); =20 return &cg->hw; } =20 +static int en75xx_register_clocks(struct device *dev, + const struct en_clk_soc_data *soc_data, + struct clk_hw_onecell_data *clk_data, + struct regmap *map, struct regmap *clk_map) +{ + struct clk_hw *hw; + u32 rate; + int i; + + for (i =3D 0; i < soc_data->num_clocks - 1; i++) { + const struct en_clk_desc *desc =3D &soc_data->base_clks[i]; + u32 val, reg =3D desc->div_reg ? desc->div_reg : desc->base_reg; + int err; + + err =3D regmap_read(map, desc->base_reg, &val); + if (err) { + pr_err("Failed reading fixed clk rate %s: %d\n", + desc->name, err); + return err; + } + rate =3D en7523_get_base_rate(desc, val); + + err =3D regmap_read(map, reg, &val); + if (err) { + pr_err("Failed reading fixed clk div %s: %d\n", + desc->name, err); + return err; + } + rate /=3D en7523_get_div(desc, val); + + hw =3D clk_hw_register_fixed_rate(dev, desc->name, NULL, 0, rate); + if (IS_ERR(hw)) { + pr_err("Failed to register clk %s: %ld\n", + desc->name, PTR_ERR(hw)); + return PTR_ERR(hw); + } + + clk_data->hws[desc->id] =3D hw; + } + + hw =3D en7523_register_pcie_clk(dev, clk_map); + if (IS_ERR(hw)) + return PTR_ERR(hw); + + clk_data->hws[EN7523_CLK_PCIE] =3D hw; + + return 0; +} + static int en7581_pci_is_enabled(struct clk_hw *hw) { struct en_clk_gate *cg =3D container_of(hw, struct en_clk_gate, hw); @@ -504,38 +557,6 @@ static void en7581_pci_disable(struct clk_hw *hw) usleep_range(1000, 2000); } =20 -static void en7523_register_clocks(struct device *dev, struct clk_hw_onece= ll_data *clk_data, - struct regmap *map, struct regmap *clk_map) -{ - struct clk_hw *hw; - u32 rate; - int i; - - for (i =3D 0; i < ARRAY_SIZE(en7523_base_clks); i++) { - const struct en_clk_desc *desc =3D &en7523_base_clks[i]; - u32 reg =3D desc->div_reg ? desc->div_reg : desc->base_reg; - u32 val; - - regmap_read(map, desc->base_reg, &val); - - rate =3D en7523_get_base_rate(desc, val); - regmap_read(map, reg, &val); - rate /=3D en7523_get_div(desc, val); - - hw =3D clk_hw_register_fixed_rate(dev, desc->name, NULL, 0, rate); - if (IS_ERR(hw)) { - pr_err("Failed to register clk %s: %ld\n", - desc->name, PTR_ERR(hw)); - continue; - } - - clk_data->hws[desc->id] =3D hw; - } - - hw =3D en7523_register_pcie_clk(dev, clk_map); - clk_data->hws[EN7523_CLK_PCIE] =3D hw; -} - static const struct regmap_config en7523_clk_regmap_config =3D { .reg_bits =3D 32, .val_bits =3D 32, @@ -543,6 +564,7 @@ static const struct regmap_config en7523_clk_regmap_con= fig =3D { }; =20 static int en7523_clk_hw_init(struct platform_device *pdev, + const struct en_clk_soc_data *soc_data, struct clk_hw_onecell_data *clk_data) { void __iomem *base, *np_base; @@ -566,51 +588,7 @@ static int en7523_clk_hw_init(struct platform_device *= pdev, if (IS_ERR(clk_map)) return PTR_ERR(clk_map); =20 - en7523_register_clocks(&pdev->dev, clk_data, map, clk_map); - - return 0; -} - -static void en7581_register_clocks(struct device *dev, struct clk_hw_onece= ll_data *clk_data, - struct regmap *map, struct regmap *clk_map) -{ - struct clk_hw *hw; - u32 rate; - int i; - - for (i =3D 0; i < ARRAY_SIZE(en7581_base_clks); i++) { - const struct en_clk_desc *desc =3D &en7581_base_clks[i]; - u32 val, reg =3D desc->div_reg ? desc->div_reg : desc->base_reg; - int err; - - err =3D regmap_read(map, desc->base_reg, &val); - if (err) { - pr_err("Failed reading fixed clk rate %s: %d\n", - desc->name, err); - continue; - } - rate =3D en7523_get_base_rate(desc, val); - - err =3D regmap_read(map, reg, &val); - if (err) { - pr_err("Failed reading fixed clk div %s: %d\n", - desc->name, err); - continue; - } - rate /=3D en7523_get_div(desc, val); - - hw =3D clk_hw_register_fixed_rate(dev, desc->name, NULL, 0, rate); - if (IS_ERR(hw)) { - pr_err("Failed to register clk %s: %ld\n", - desc->name, PTR_ERR(hw)); - continue; - } - - clk_data->hws[desc->id] =3D hw; - } - - hw =3D en7523_register_pcie_clk(dev, clk_map); - clk_data->hws[EN7523_CLK_PCIE] =3D hw; + return en75xx_register_clocks(&pdev->dev, soc_data, clk_data, map, clk_ma= p); } =20 static int en7523_reset_update(struct reset_controller_dev *rcdev, @@ -689,10 +667,12 @@ static int en7581_reset_register(struct device *dev, = struct regmap *map) } =20 static int en7581_clk_hw_init(struct platform_device *pdev, + const struct en_clk_soc_data *soc_data, struct clk_hw_onecell_data *clk_data) { struct regmap *map, *clk_map; void __iomem *base; + int ret; =20 map =3D syscon_regmap_lookup_by_compatible("airoha,en7581-chip-scu"); if (IS_ERR(map)) @@ -706,7 +686,9 @@ static int en7581_clk_hw_init(struct platform_device *p= dev, if (IS_ERR(clk_map)) return PTR_ERR(clk_map); =20 - en7581_register_clocks(&pdev->dev, clk_data, map, clk_map); + ret =3D en75xx_register_clocks(&pdev->dev, soc_data, clk_data, map, clk_m= ap); + if (ret) + return ret; =20 regmap_clear_bits(clk_map, REG_NP_SCU_SSTR, REG_PCIE_XSI0_SEL_MASK | REG_PCIE_XSI1_SEL_MASK); @@ -732,7 +714,7 @@ static int en7523_clk_probe(struct platform_device *pde= v) return -ENOMEM; =20 clk_data->num =3D soc_data->num_clocks; - r =3D soc_data->hw_init(pdev, clk_data); + r =3D soc_data->hw_init(pdev, soc_data, clk_data); if (r) return r; =20 @@ -740,6 +722,7 @@ static int en7523_clk_probe(struct platform_device *pde= v) } =20 static const struct en_clk_soc_data en7523_data =3D { + .base_clks =3D en7523_base_clks, .num_clocks =3D ARRAY_SIZE(en7523_base_clks) + 1, .pcie_ops =3D { .is_enabled =3D en7523_pci_is_enabled, @@ -750,6 +733,7 @@ static const struct en_clk_soc_data en7523_data =3D { }; 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[93.34.88.225]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-4532e24b0c8sm173809435e9.24.2025.06.17.06.05.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Jun 2025 06:05:28 -0700 (PDT) From: Christian Marangi To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Felix Fietkau , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Christian Marangi Subject: [PATCH v2 03/10] clk: en7523: convert to full clk_hw implementation Date: Tue, 17 Jun 2025 15:04:46 +0200 Message-ID: <20250617130455.32682-4-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250617130455.32682-1-ansuelsmth@gmail.com> References: <20250617130455.32682-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In preparation for support of .set_rate, convert the clock register logic from fixed clock implementation to full clk_hw implementation with dedicated OPs. This is just a rework and no behaviour change is expected. Signed-off-by: Christian Marangi --- drivers/clk/clk-en7523.c | 83 ++++++++++++++++++++++++++++------------ 1 file changed, 59 insertions(+), 24 deletions(-) diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c index b040f0f0d727..10fb0dcdc88b 100644 --- a/drivers/clk/clk-en7523.c +++ b/drivers/clk/clk-en7523.c @@ -69,6 +69,12 @@ struct en_clk_gate { struct clk_hw hw; }; =20 +struct en_clk { + struct regmap *map; + const struct en_clk_desc *desc; + struct clk_hw hw; +}; + struct en_rst_data { const u16 *bank_ofs; const u16 *idx_map; @@ -471,44 +477,73 @@ static struct clk_hw *en7523_register_pcie_clk(struct= device *dev, return &cg->hw; } =20 +static unsigned long en75xx_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct en_clk *c =3D container_of(hw, struct en_clk, hw); + const struct en_clk_desc *desc =3D c->desc; + struct regmap *map =3D c->map; + u32 val, reg; + u32 rate; + int err; + + err =3D regmap_read(map, desc->base_reg, &val); + if (err) { + pr_err("Failed reading fixed clk rate %s: %d\n", + desc->name, err); + return err; + } + rate =3D en7523_get_base_rate(desc, val); + + reg =3D desc->div_reg ? desc->div_reg : desc->base_reg; + err =3D regmap_read(map, reg, &val); + if (err) { + pr_err("Failed reading fixed clk div %s: %d\n", + desc->name, err); + return err; + } + + return rate / en7523_get_div(desc, val); +} + +static const struct clk_ops en75xx_clk_ops =3D { + .recalc_rate =3D en75xx_recalc_rate, +}; + static int en75xx_register_clocks(struct device *dev, const struct en_clk_soc_data *soc_data, struct clk_hw_onecell_data *clk_data, struct regmap *map, struct regmap *clk_map) { struct clk_hw *hw; - u32 rate; int i; =20 for (i =3D 0; i < soc_data->num_clocks - 1; i++) { const struct en_clk_desc *desc =3D &soc_data->base_clks[i]; - u32 val, reg =3D desc->div_reg ? desc->div_reg : desc->base_reg; + struct clk_init_data init =3D { + .ops =3D &en75xx_clk_ops, + }; + struct en_clk *en_clk; int err; =20 - err =3D regmap_read(map, desc->base_reg, &val); - if (err) { - pr_err("Failed reading fixed clk rate %s: %d\n", - desc->name, err); - return err; - } - rate =3D en7523_get_base_rate(desc, val); + en_clk =3D devm_kzalloc(dev, sizeof(*en_clk), GFP_KERNEL); + if (!en_clk) + return -ENOMEM; =20 - err =3D regmap_read(map, reg, &val); + init.name =3D desc->name; + + en_clk->map =3D map; + en_clk->desc =3D desc; + en_clk->hw.init =3D &init; + + err =3D devm_clk_hw_register(dev, &en_clk->hw); if (err) { - pr_err("Failed reading fixed clk div %s: %d\n", + pr_err("Failed to register clk %s: %d\n", desc->name, err); return err; } - rate /=3D en7523_get_div(desc, val); - - hw =3D clk_hw_register_fixed_rate(dev, desc->name, NULL, 0, rate); - if (IS_ERR(hw)) { - pr_err("Failed to register clk %s: %ld\n", - desc->name, PTR_ERR(hw)); - return PTR_ERR(hw); - } =20 - clk_data->hws[desc->id] =3D hw; + clk_data->hws[desc->id] =3D &en_clk->hw; } =20 hw =3D en7523_register_pcie_clk(dev, clk_map); @@ -672,7 +707,7 @@ static int en7581_clk_hw_init(struct platform_device *p= dev, { struct regmap *map, *clk_map; void __iomem *base; - int ret; + int err; =20 map =3D syscon_regmap_lookup_by_compatible("airoha,en7581-chip-scu"); if (IS_ERR(map)) @@ -686,9 +721,9 @@ static int en7581_clk_hw_init(struct platform_device *p= dev, if (IS_ERR(clk_map)) return PTR_ERR(clk_map); =20 - ret =3D en75xx_register_clocks(&pdev->dev, soc_data, clk_data, map, clk_m= ap); - if (ret) - return ret; + err =3D en75xx_register_clocks(&pdev->dev, soc_data, clk_data, map, clk_m= ap); + if (err) + return err; =20 regmap_clear_bits(clk_map, REG_NP_SCU_SSTR, REG_PCIE_XSI0_SEL_MASK | REG_PCIE_XSI1_SEL_MASK); --=20 2.48.1 From nobody Fri Oct 10 09:48:03 2025 Received: from mail-wm1-f48.google.com (mail-wm1-f48.google.com [209.85.128.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B535D2E973A; Tue, 17 Jun 2025 13:05:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.48 ARC-Seal: i=1; a=rsa-sha256; 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[93.34.88.225]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-4532e24b0c8sm173809435e9.24.2025.06.17.06.05.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Jun 2025 06:05:29 -0700 (PDT) From: Christian Marangi To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Felix Fietkau , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Christian Marangi Subject: [PATCH v2 04/10] clk: en7523: add support for .set_rate Date: Tue, 17 Jun 2025 15:04:47 +0200 Message-ID: <20250617130455.32682-5-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250617130455.32682-1-ansuelsmth@gmail.com> References: <20250617130455.32682-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for EN7523 driver to configure rate. The SoC expose both base clock selector and clock divisor hence it's possible to change the rate. This will be especially needed for new SoC AN7583 that require changes for the MDIO and the eMMC. The clock were assumed correctly configured by the bootloader but this goes against the rule of "kernel should not depend on external configuration". Signed-off-by: Christian Marangi --- drivers/clk/clk-en7523.c | 141 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 141 insertions(+) diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c index 10fb0dcdc88b..54c0462c0dee 100644 --- a/drivers/clk/clk-en7523.c +++ b/drivers/clk/clk-en7523.c @@ -506,8 +506,149 @@ static unsigned long en75xx_recalc_rate(struct clk_hw= *hw, return rate / en7523_get_div(desc, val); } =20 +static int en75xx_get_base_val_for_rate(const struct en_clk_desc *desc, + int div, unsigned long rate) +{ + int i; + + /* Single base rate */ + if (!desc->base_bits) { + if (rate !=3D desc->base_value / div) + goto err; + + return 0; + } + + /* Check every base rate with provided divisor */ + for (i =3D 0; i < desc->n_base_values; i++) + if (rate =3D=3D desc->base_values[i] / div) + return i; + +err: + return -EINVAL; +} + +static int en75xx_get_vals_for_rate(const struct en_clk_desc *desc, + unsigned long rate, + u32 *base_val, u32 *div_val) +{ + int tmp_base_val =3D 0; + int tmp_div_val =3D 0; + + if (!desc->base_bits && !desc->div_bits) + return -EINVAL; + + /* Divisor not supported, just search in base rate */ + if (!desc->div_bits) { + tmp_base_val =3D en75xx_get_base_val_for_rate(desc, 1, rate); + if (tmp_base_val < 0) { + pr_err("Invalid rate for clock %s\n", + desc->name); + return -EINVAL; + } + + goto exit; + } + + /* Check if div0 satisfy the request */ + if (desc->div_val0) { + tmp_base_val =3D en75xx_get_base_val_for_rate(desc, + desc->div_val0, + rate); + if (tmp_base_val >=3D 0) + goto exit; + + /* Skip checking first divisor val */ + tmp_div_val =3D 1; + } + + /* Simulate rate with every divisor supported */ + for (; tmp_div_val < BIT(desc->div_bits) - 1; tmp_div_val++) { + int div =3D (tmp_div_val + desc->div_offset) * desc->div_step; + + tmp_base_val =3D en75xx_get_base_val_for_rate(desc, div, + rate); + if (tmp_base_val >=3D 0) + goto exit; + } + + if (tmp_div_val =3D=3D BIT(desc->div_bits) - 1) { + pr_err("Invalid rate for clock %s\n", + desc->name); + return -EINVAL; + } + +exit: + *base_val =3D tmp_base_val; + *div_val =3D tmp_div_val; + + return 0; +} + +static long en75xx_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + struct en_clk *en_clk =3D container_of(hw, struct en_clk, hw); + u32 div_val, base_val; + int err; + + /* Just check if the rate is possible */ + err =3D en75xx_get_vals_for_rate(en_clk->desc, rate, + &base_val, &div_val); + if (err) + return err; + + return rate; +} + +static int en75xx_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct en_clk *en_clk =3D container_of(hw, struct en_clk, hw); + const struct en_clk_desc *desc =3D en_clk->desc; + struct regmap *map =3D en_clk->map; + u32 base_val, div_val; + u32 reg, val, mask; + int err; + + err =3D en75xx_get_vals_for_rate(en_clk->desc, rate, + &base_val, &div_val); + if (err) + return err; + + if (desc->div_bits) { + reg =3D desc->div_reg ? desc->div_reg : desc->base_reg; + + mask =3D (BIT(desc->div_bits) - 1) << desc->div_shift; + val =3D div_val << desc->div_shift; + + err =3D regmap_update_bits(map, reg, mask, val); + if (err) { + pr_err("Failed to update div reg for clock %s\n", + desc->name); + return -EINVAL; + } + } + + if (desc->base_bits) { + mask =3D (BIT(desc->base_bits) - 1) << desc->base_shift; + val =3D base_val << desc->base_shift; + + err =3D regmap_update_bits(map, desc->base_reg, mask, val); + if (err) { + pr_err("Failed to update reg for clock %s\n", + desc->name); + return -EINVAL; + } + } + + return 0; +} + static const struct clk_ops en75xx_clk_ops =3D { .recalc_rate =3D en75xx_recalc_rate, + .round_rate =3D en75xx_round_rate, + .set_rate =3D en75xx_set_rate, }; =20 static int en75xx_register_clocks(struct device *dev, --=20 2.48.1 From nobody Fri Oct 10 09:48:03 2025 Received: from mail-wm1-f41.google.com (mail-wm1-f41.google.com [209.85.128.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 92D912E9739; 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[93.34.88.225]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-4532e24b0c8sm173809435e9.24.2025.06.17.06.05.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Jun 2025 06:05:30 -0700 (PDT) From: Christian Marangi To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Felix Fietkau , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Christian Marangi Subject: [PATCH v2 05/10] clk: en7523: permit to reference Chip SCU from phandle Date: Tue, 17 Jun 2025 15:04:48 +0200 Message-ID: <20250617130455.32682-6-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250617130455.32682-1-ansuelsmth@gmail.com> References: <20250617130455.32682-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In preparation for support of AN7583 and to make Chip SCU reference more robust, permit to reference the Chip SCU syscon regmap also with the "airoha,chip-scu" property in DT. Legacy implementation is kept by fallbacking in the absence of "airoha,chip-scu" property. Signed-off-by: Christian Marangi --- drivers/clk/clk-en7523.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c index 54c0462c0dee..a768ba71feec 100644 --- a/drivers/clk/clk-en7523.c +++ b/drivers/clk/clk-en7523.c @@ -846,11 +846,16 @@ static int en7581_clk_hw_init(struct platform_device = *pdev, const struct en_clk_soc_data *soc_data, struct clk_hw_onecell_data *clk_data) { + struct device *dev =3D &pdev->dev; struct regmap *map, *clk_map; void __iomem *base; int err; =20 - map =3D syscon_regmap_lookup_by_compatible("airoha,en7581-chip-scu"); + if (of_property_present(dev->of_node, "airoha,chip-scu")) + map =3D syscon_regmap_lookup_by_phandle(dev->of_node, + "airoha,chip-scu"); + else + map =3D syscon_regmap_lookup_by_compatible("airoha,en7581-chip-scu"); if (IS_ERR(map)) return PTR_ERR(map); =20 --=20 2.48.1 From nobody Fri Oct 10 09:48:03 2025 Received: from mail-wm1-f41.google.com (mail-wm1-f41.google.com [209.85.128.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AB35D2E9745; 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[93.34.88.225]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-4532e24b0c8sm173809435e9.24.2025.06.17.06.05.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Jun 2025 06:05:31 -0700 (PDT) From: Christian Marangi To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Felix Fietkau , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Christian Marangi Subject: [PATCH v2 06/10] dt-bindings: clock: airoha: Document new property airoha,chip-scu Date: Tue, 17 Jun 2025 15:04:49 +0200 Message-ID: <20250617130455.32682-7-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250617130455.32682-1-ansuelsmth@gmail.com> References: <20250617130455.32682-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Document new property airoha,chip-scu used on new Airoha SoC to reference the Chip SCU syscon node used for PCIe configuration. Signed-off-by: Christian Marangi --- .../devicetree/bindings/clock/airoha,en7523-scu.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml= b/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml index fe2c5c1baf43..bce77a14c938 100644 --- a/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml +++ b/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml @@ -49,6 +49,11 @@ properties: description: ID of the controller reset line const: 1 =20 + airoha,chip-scu: + $ref: /schemas/types.yaml#/definitions/phandle + description: Phandle to the Chip SCU syscon node for PCIe + configuration + required: - compatible - reg @@ -66,6 +71,8 @@ allOf: =20 '#reset-cells': false =20 + airoha,chip-scu: false + - if: properties: compatible: @@ -97,5 +104,6 @@ examples: reg =3D <0x0 0x1fb00000 0x0 0x970>; #clock-cells =3D <1>; #reset-cells =3D <1>; + airoha,chip-scu =3D <&chip_scu>; }; }; --=20 2.48.1 From nobody Fri Oct 10 09:48:03 2025 Received: from mail-wm1-f45.google.com (mail-wm1-f45.google.com [209.85.128.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 646642ECD2E; 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[93.34.88.225]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-4532e24b0c8sm173809435e9.24.2025.06.17.06.05.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Jun 2025 06:05:33 -0700 (PDT) From: Christian Marangi To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Felix Fietkau , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Christian Marangi Subject: [PATCH v2 07/10] clk: en7523: reword and clean clk_probe variables Date: Tue, 17 Jun 2025 15:04:50 +0200 Message-ID: <20250617130455.32682-8-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250617130455.32682-1-ansuelsmth@gmail.com> References: <20250617130455.32682-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Rework and clean en7523_clk_probe variables to make them consistent with the rest of the source. Also apply some minor cleanup for pdev variables. Signed-off-by: Christian Marangi --- drivers/clk/clk-en7523.c | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c index a768ba71feec..5236119bca83 100644 --- a/drivers/clk/clk-en7523.c +++ b/drivers/clk/clk-en7523.c @@ -881,25 +881,27 @@ static int en7581_clk_hw_init(struct platform_device = *pdev, =20 static int en7523_clk_probe(struct platform_device *pdev) { - struct device_node *node =3D pdev->dev.of_node; const struct en_clk_soc_data *soc_data; struct clk_hw_onecell_data *clk_data; - int r; + struct device *dev =3D &pdev->dev; + int err; =20 - soc_data =3D device_get_match_data(&pdev->dev); + soc_data =3D device_get_match_data(dev); =20 - clk_data =3D devm_kzalloc(&pdev->dev, - struct_size(clk_data, hws, soc_data->num_clocks), + clk_data =3D devm_kzalloc(dev, + struct_size(clk_data, hws, + soc_data->num_clocks), GFP_KERNEL); if (!clk_data) return -ENOMEM; =20 clk_data->num =3D soc_data->num_clocks; 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[93.34.88.225]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-4532e24b0c8sm173809435e9.24.2025.06.17.06.05.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Jun 2025 06:05:34 -0700 (PDT) From: Christian Marangi To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Felix Fietkau , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Christian Marangi Subject: [PATCH v2 08/10] clk: en7523: add support for probing SCU child Date: Tue, 17 Jun 2025 15:04:51 +0200 Message-ID: <20250617130455.32682-9-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250617130455.32682-1-ansuelsmth@gmail.com> References: <20250617130455.32682-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" On new Airoha SoC in the SCU register space additional pheriperal might be present aside from the clock/reset. The Airoha AN7583 SoC is an example of this where 2 MDIO controller are present. Introduce a bool "probe_child" to trigger probe of child node of the SCU node. Signed-off-by: Christian Marangi --- drivers/clk/clk-en7523.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c index 5236119bca83..00c80221a274 100644 --- a/drivers/clk/clk-en7523.c +++ b/drivers/clk/clk-en7523.c @@ -5,6 +5,7 @@ #include #include #include +#include #include #include #include @@ -83,6 +84,7 @@ struct en_rst_data { }; =20 struct en_clk_soc_data { + bool probe_child; u32 num_clocks; const struct en_clk_desc *base_clks; const struct clk_ops pcie_ops; @@ -900,8 +902,19 @@ static int en7523_clk_probe(struct platform_device *pd= ev) if (err) return err; =20 - return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, - clk_data); + err =3D of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, + clk_data); + if (err) + return err; + + if (soc_data->probe_child) { + err =3D of_platform_populate(dev->of_node, NULL, NULL, + dev); + if (err) + return err; + } + + return 0; } =20 static const struct en_clk_soc_data en7523_data =3D { --=20 2.48.1 From nobody Fri Oct 10 09:48:03 2025 Received: from mail-wm1-f45.google.com (mail-wm1-f45.google.com [209.85.128.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0FBC22ED85C; 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[93.34.88.225]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-4532e24b0c8sm173809435e9.24.2025.06.17.06.05.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Jun 2025 06:05:36 -0700 (PDT) From: Christian Marangi To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Felix Fietkau , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Christian Marangi Subject: [PATCH v2 09/10] dt-bindings: clock: airoha: Document support for AN7583 clock Date: Tue, 17 Jun 2025 15:04:52 +0200 Message-ID: <20250617130455.32682-10-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250617130455.32682-1-ansuelsmth@gmail.com> References: <20250617130455.32682-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Document support for Airoha AN7583 clock. This is based on the EN7523 clock schema with the new requirement of the "airoha,chip-scu" (previously optional for EN7581). Add additional binding for additional clock and reset lines. Signed-off-by: Christian Marangi --- .../bindings/clock/airoha,en7523-scu.yaml | 9 +++ include/dt-bindings/clock/en7523-clk.h | 3 + .../dt-bindings/reset/airoha,an7583-reset.h | 61 +++++++++++++++++++ 3 files changed, 73 insertions(+) create mode 100644 include/dt-bindings/reset/airoha,an7583-reset.h diff --git a/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml= b/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml index bce77a14c938..be9759b86fdc 100644 --- a/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml +++ b/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml @@ -32,6 +32,7 @@ properties: - enum: - airoha,en7523-scu - airoha,en7581-scu + - airoha,an7583-scu =20 reg: items: @@ -82,6 +83,14 @@ allOf: reg: maxItems: 1 =20 + - if: + properties: + compatible: + const: airoha,an7583-scu + then: + required: + - airoha,chip-scu + additionalProperties: false =20 examples: diff --git a/include/dt-bindings/clock/en7523-clk.h b/include/dt-bindings/c= lock/en7523-clk.h index edfa64045f52..0fbbcb7b1b25 100644 --- a/include/dt-bindings/clock/en7523-clk.h +++ b/include/dt-bindings/clock/en7523-clk.h @@ -14,4 +14,7 @@ =20 #define EN7581_CLK_EMMC 8 =20 +#define AN7583_CLK_MDIO0 9 +#define AN7583_CLK_MDIO1 10 + #endif /* _DT_BINDINGS_CLOCK_AIROHA_EN7523_H_ */ diff --git a/include/dt-bindings/reset/airoha,an7583-reset.h b/include/dt-b= indings/reset/airoha,an7583-reset.h new file mode 100644 index 000000000000..96cfe11d2943 --- /dev/null +++ b/include/dt-bindings/reset/airoha,an7583-reset.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2024 AIROHA Inc + * Author: Christian Marangi + */ + +#ifndef __DT_BINDINGS_RESET_CONTROLLER_AIROHA_AN7583_H_ +#define __DT_BINDINGS_RESET_CONTROLLER_AIROHA_AN7583_H_ + +/* RST_CTRL2 */ +#define AN7583_XPON_PHY_RST 0 +#define AN7583_GPON_OLT_RST 1 +#define AN7583_CPU_TIMER2_RST 2 +#define AN7583_HSUART_RST 3 +#define AN7583_UART4_RST 4 +#define AN7583_UART5_RST 5 +#define AN7583_I2C2_RST 6 +#define AN7583_XSI_MAC_RST 7 +#define AN7583_XSI_PHY_RST 8 +#define AN7583_NPU_RST 9 +#define AN7583_TRNG_MSTART_RST 10 +#define AN7583_DUAL_HSI0_RST 11 +#define AN7583_DUAL_HSI1_RST 12 +#define AN7583_DUAL_HSI0_MAC_RST 13 +#define AN7583_DUAL_HSI1_MAC_RST 14 +#define AN7583_WDMA_RST 15 +#define AN7583_WOE0_RST 16 +#define AN7583_HSDMA_RST 17 +#define AN7583_TDMA_RST 18 +#define AN7583_EMMC_RST 19 +#define AN7583_SOE_RST 20 +#define AN7583_XFP_MAC_RST 21 +#define AN7583_MDIO0 22 +#define AN7583_MDIO1 23 +/* RST_CTRL1 */ +#define AN7583_PCM1_ZSI_ISI_RST 24 +#define AN7583_FE_PDMA_RST 25 +#define AN7583_FE_QDMA_RST 26 +#define AN7583_PCM_SPIWP_RST 27 +#define AN7583_CRYPTO_RST 28 +#define AN7583_TIMER_RST 29 +#define AN7583_PCM1_RST 30 +#define AN7583_UART_RST 31 +#define AN7583_GPIO_RST 32 +#define AN7583_GDMA_RST 33 +#define AN7583_I2C_MASTER_RST 34 +#define AN7583_PCM2_ZSI_ISI_RST 35 +#define AN7583_SFC_RST 36 +#define AN7583_UART2_RST 37 +#define AN7583_GDMP_RST 38 +#define AN7583_FE_RST 39 +#define AN7583_USB_HOST_P0_RST 40 +#define AN7583_GSW_RST 41 +#define AN7583_SFC2_PCM_RST 42 +#define AN7583_PCIE0_RST 43 +#define AN7583_PCIE1_RST 44 +#define AN7583_CPU_TIMER_RST 45 +#define AN7583_PCIE_HB_RST 46 +#define AN7583_XPON_MAC_RST 47 + +#endif /* __DT_BINDINGS_RESET_CONTROLLER_AIROHA_AN7583_H_ */ --=20 2.48.1 From nobody Fri Oct 10 09:48:03 2025 Received: from mail-wm1-f52.google.com (mail-wm1-f52.google.com [209.85.128.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 475F12F2C6B; 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[93.34.88.225]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-4532e24b0c8sm173809435e9.24.2025.06.17.06.05.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Jun 2025 06:05:37 -0700 (PDT) From: Christian Marangi To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Felix Fietkau , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Christian Marangi Subject: [PATCH v2 10/10] clk: en7523: add support for Airoha AN7583 clock Date: Tue, 17 Jun 2025 15:04:53 +0200 Message-ID: <20250617130455.32682-11-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250617130455.32682-1-ansuelsmth@gmail.com> References: <20250617130455.32682-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for Airoha AN7583 clock and reset. Airoha AN7583 SoC have the same register address of EN7581 but implement different bits and additional base clocks. Also reset are different with the introduction of 2 dedicated MDIO line and drop of some reset lines. Signed-off-by: Christian Marangi --- drivers/clk/clk-en7523.c | 264 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 264 insertions(+) diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c index 00c80221a274..b3c57aac8480 100644 --- a/drivers/clk/clk-en7523.c +++ b/drivers/clk/clk-en7523.c @@ -12,6 +12,7 @@ #include #include #include +#include =20 #define RST_NR_PER_BANK 32 =20 @@ -104,6 +105,14 @@ static const u32 bus7581_base[] =3D { 600000000, 54000= 0000 }; static const u32 npu7581_base[] =3D { 800000000, 750000000, 720000000, 600= 000000 }; static const u32 crypto_base[] =3D { 540000000, 480000000 }; static const u32 emmc7581_base[] =3D { 200000000, 150000000 }; +/* AN7583 */ +static const u32 gsw7583_base[] =3D { 540672000, 270336000, 400000000, 200= 000000 }; +static const u32 emi7583_base[] =3D { 540672000, 480000000, 400000000, 300= 000000 }; +static const u32 bus7583_base[] =3D { 600000000, 540672000, 480000000, 400= 000000 }; +static const u32 spi7583_base[] =3D { 100000000, 12500000 }; +static const u32 npu7583_base[] =3D { 666000000, 800000000, 720000000, 600= 000000 }; +static const u32 crypto7583_base[] =3D { 540672000, 400000000 }; +static const u32 emmc7583_base[] =3D { 150000000, 200000000 }; =20 static const struct en_clk_desc en7523_base_clks[] =3D { { @@ -306,6 +315,138 @@ static const struct en_clk_desc en7581_base_clks[] = =3D { } }; =20 +static const struct en_clk_desc an7583_base_clks[] =3D { + { + .id =3D EN7523_CLK_GSW, + .name =3D "gsw", + + .base_reg =3D REG_GSW_CLK_DIV_SEL, + .base_bits =3D 2, + .base_shift =3D 8, + .base_values =3D gsw7583_base, + .n_base_values =3D ARRAY_SIZE(gsw7583_base), + + .div_bits =3D 3, + .div_shift =3D 0, + .div_step =3D 1, + .div_offset =3D 1, + }, { + .id =3D EN7523_CLK_EMI, + .name =3D "emi", + + .base_reg =3D REG_EMI_CLK_DIV_SEL, + .base_bits =3D 2, + .base_shift =3D 8, + .base_values =3D emi7583_base, + .n_base_values =3D ARRAY_SIZE(emi7583_base), + + .div_bits =3D 3, + .div_shift =3D 0, + .div_step =3D 1, + .div_offset =3D 1, + }, { + .id =3D EN7523_CLK_BUS, + .name =3D "bus", + + .base_reg =3D REG_BUS_CLK_DIV_SEL, + .base_bits =3D 2, + .base_shift =3D 8, + .base_values =3D bus7583_base, + .n_base_values =3D ARRAY_SIZE(bus7583_base), + + .div_bits =3D 3, + .div_shift =3D 0, + .div_step =3D 1, + .div_offset =3D 1, + }, { + .id =3D EN7523_CLK_SLIC, + .name =3D "slic", + + .base_reg =3D REG_SPI_CLK_FREQ_SEL, + .base_bits =3D 1, + .base_shift =3D 0, + .base_values =3D slic_base, + .n_base_values =3D ARRAY_SIZE(slic_base), + + .div_reg =3D REG_SPI_CLK_DIV_SEL, + .div_bits =3D 5, + .div_shift =3D 24, + .div_val0 =3D 20, + .div_step =3D 2, + }, { + .id =3D EN7523_CLK_SPI, + .name =3D "spi", + + .base_reg =3D REG_SPI_CLK_FREQ_SEL, + .base_bits =3D 1, + .base_shift =3D 1, + .base_values =3D spi7583_base, + .n_base_values =3D ARRAY_SIZE(spi7583_base), + + .div_reg =3D REG_SPI_CLK_DIV_SEL, + .div_bits =3D 5, + .div_shift =3D 8, + .div_val0 =3D 40, + .div_step =3D 2, + }, { + .id =3D EN7523_CLK_NPU, + .name =3D "npu", + + .base_reg =3D REG_NPU_CLK_DIV_SEL, + .base_bits =3D 2, + .base_shift =3D 9, + .base_values =3D npu7583_base, + .n_base_values =3D ARRAY_SIZE(npu7583_base), + + .div_bits =3D 3, + .div_shift =3D 0, + .div_step =3D 1, + .div_offset =3D 1, + }, { + .id =3D EN7523_CLK_CRYPTO, + .name =3D "crypto", + + .base_reg =3D REG_CRYPTO_CLKSRC2, + .base_bits =3D 1, + .base_shift =3D 0, + .base_values =3D crypto7583_base, + .n_base_values =3D ARRAY_SIZE(crypto7583_base), + }, { + .id =3D EN7581_CLK_EMMC, + .name =3D "emmc", + + .base_reg =3D REG_CRYPTO_CLKSRC2, + .base_bits =3D 1, + .base_shift =3D 13, + .base_values =3D emmc7583_base, + .n_base_values =3D ARRAY_SIZE(emmc7583_base), + }, { + .id =3D AN7583_CLK_MDIO0, + .name =3D "mdio0", + + .base_reg =3D REG_CRYPTO_CLKSRC2, + + .base_value =3D 25000000, + + .div_bits =3D 4, + .div_shift =3D 15, + .div_step =3D 1, + .div_offset =3D 1, + }, { + .id =3D AN7583_CLK_MDIO1, + .name =3D "mdio1", + + .base_reg =3D REG_CRYPTO_CLKSRC2, + + .base_value =3D 25000000, + + .div_bits =3D 4, + .div_shift =3D 19, + .div_step =3D 1, + .div_offset =3D 1, + } +}; + static const u16 en7581_rst_ofs[] =3D { REG_RST_CTRL2, REG_RST_CTRL1, @@ -369,6 +510,59 @@ static const u16 en7581_rst_map[] =3D { [EN7581_XPON_MAC_RST] =3D RST_NR_PER_BANK + 31, }; =20 +static const u16 an7583_rst_map[] =3D { + /* RST_CTRL2 */ + [AN7583_XPON_PHY_RST] =3D 0, + [AN7583_GPON_OLT_RST] =3D 1, + [AN7583_CPU_TIMER2_RST] =3D 2, + [AN7583_HSUART_RST] =3D 3, + [AN7583_UART4_RST] =3D 4, + [AN7583_UART5_RST] =3D 5, + [AN7583_I2C2_RST] =3D 6, + [AN7583_XSI_MAC_RST] =3D 7, + [AN7583_XSI_PHY_RST] =3D 8, + [AN7583_NPU_RST] =3D 9, + [AN7583_TRNG_MSTART_RST] =3D 12, + [AN7583_DUAL_HSI0_RST] =3D 13, + [AN7583_DUAL_HSI1_RST] =3D 14, + [AN7583_DUAL_HSI0_MAC_RST] =3D 16, + [AN7583_DUAL_HSI1_MAC_RST] =3D 17, + [AN7583_WDMA_RST] =3D 19, + [AN7583_WOE0_RST] =3D 20, + [AN7583_HSDMA_RST] =3D 22, + [AN7583_TDMA_RST] =3D 24, + [AN7583_EMMC_RST] =3D 25, + [AN7583_SOE_RST] =3D 26, + [AN7583_XFP_MAC_RST] =3D 28, + [AN7583_MDIO0] =3D 30, + [AN7583_MDIO1] =3D 31, + /* RST_CTRL1 */ + [AN7583_PCM1_ZSI_ISI_RST] =3D RST_NR_PER_BANK + 0, + [AN7583_FE_PDMA_RST] =3D RST_NR_PER_BANK + 1, + [AN7583_FE_QDMA_RST] =3D RST_NR_PER_BANK + 2, + [AN7583_PCM_SPIWP_RST] =3D RST_NR_PER_BANK + 4, + [AN7583_CRYPTO_RST] =3D RST_NR_PER_BANK + 6, + [AN7583_TIMER_RST] =3D RST_NR_PER_BANK + 8, + [AN7583_PCM1_RST] =3D RST_NR_PER_BANK + 11, + [AN7583_UART_RST] =3D RST_NR_PER_BANK + 12, + [AN7583_GPIO_RST] =3D RST_NR_PER_BANK + 13, + [AN7583_GDMA_RST] =3D RST_NR_PER_BANK + 14, + [AN7583_I2C_MASTER_RST] =3D RST_NR_PER_BANK + 16, + [AN7583_PCM2_ZSI_ISI_RST] =3D RST_NR_PER_BANK + 17, + [AN7583_SFC_RST] =3D RST_NR_PER_BANK + 18, + [AN7583_UART2_RST] =3D RST_NR_PER_BANK + 19, + [AN7583_GDMP_RST] =3D RST_NR_PER_BANK + 20, + [AN7583_FE_RST] =3D RST_NR_PER_BANK + 21, + [AN7583_USB_HOST_P0_RST] =3D RST_NR_PER_BANK + 22, + [AN7583_GSW_RST] =3D RST_NR_PER_BANK + 23, + [AN7583_SFC2_PCM_RST] =3D RST_NR_PER_BANK + 25, + [AN7583_PCIE0_RST] =3D RST_NR_PER_BANK + 26, + [AN7583_PCIE1_RST] =3D RST_NR_PER_BANK + 27, + [AN7583_CPU_TIMER_RST] =3D RST_NR_PER_BANK + 28, + [AN7583_PCIE_HB_RST] =3D RST_NR_PER_BANK + 29, + [AN7583_XPON_MAC_RST] =3D RST_NR_PER_BANK + 31, +}; + static u32 en7523_get_base_rate(const struct en_clk_desc *desc, u32 val) { if (!desc->base_bits) @@ -881,6 +1075,62 @@ static int en7581_clk_hw_init(struct platform_device = *pdev, return en7581_reset_register(&pdev->dev, clk_map); } =20 +static int an7583_reset_register(struct device *dev, struct regmap *map) +{ + struct en_rst_data *rst_data; + + rst_data =3D devm_kzalloc(dev, sizeof(*rst_data), GFP_KERNEL); + if (!rst_data) + return -ENOMEM; + + rst_data->bank_ofs =3D en7581_rst_ofs; + rst_data->idx_map =3D an7583_rst_map; + rst_data->map =3D map; + + rst_data->rcdev.nr_resets =3D ARRAY_SIZE(an7583_rst_map); + rst_data->rcdev.of_xlate =3D en7523_reset_xlate; + rst_data->rcdev.ops =3D &en7581_reset_ops; + rst_data->rcdev.of_node =3D dev->of_node; + rst_data->rcdev.of_reset_n_cells =3D 1; + rst_data->rcdev.owner =3D THIS_MODULE; + rst_data->rcdev.dev =3D dev; + + return devm_reset_controller_register(dev, &rst_data->rcdev); +} + +static int an7583_clk_hw_init(struct platform_device *pdev, + const struct en_clk_soc_data *soc_data, + struct clk_hw_onecell_data *clk_data) +{ + struct device *dev =3D &pdev->dev; + struct regmap *map, *clk_map; + void __iomem *base; + int err; + + map =3D syscon_regmap_lookup_by_phandle(dev->of_node, "airoha,chip-scu"); + if (IS_ERR(map)) + return PTR_ERR(map); + + base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + clk_map =3D devm_regmap_init_mmio(&pdev->dev, base, &en7523_clk_regmap_co= nfig); + if (IS_ERR(clk_map)) + return PTR_ERR(clk_map); + + err =3D en75xx_register_clocks(dev, soc_data, clk_data, map, clk_map); + if (err) + return err; + + regmap_clear_bits(clk_map, REG_NP_SCU_SSTR, + REG_PCIE_XSI0_SEL_MASK | REG_PCIE_XSI1_SEL_MASK); + regmap_update_bits(clk_map, REG_NP_SCU_PCIC, REG_PCIE_CTRL, + FIELD_PREP(REG_PCIE_CTRL, 3)); + + return an7583_reset_register(dev, clk_map); +} + static int en7523_clk_probe(struct platform_device *pdev) { const struct en_clk_soc_data *soc_data; @@ -940,9 +1190,23 @@ static const struct en_clk_soc_data en7581_data =3D { .hw_init =3D en7581_clk_hw_init, }; =20 +static const struct en_clk_soc_data an7583_data =3D { + .probe_child =3D true, + .base_clks =3D an7583_base_clks, + /* We increment num_clocks by 1 to account for additional PCIe clock */ + .num_clocks =3D ARRAY_SIZE(an7583_base_clks) + 1, + .pcie_ops =3D { + .is_enabled =3D en7581_pci_is_enabled, + .enable =3D en7581_pci_enable, + .disable =3D en7581_pci_disable, + }, + .hw_init =3D an7583_clk_hw_init, +}; + static const struct of_device_id of_match_clk_en7523[] =3D { { .compatible =3D "airoha,en7523-scu", .data =3D &en7523_data }, { .compatible =3D "airoha,en7581-scu", .data =3D &en7581_data }, + { .compatible =3D "airoha,an7583-scu", .data =3D &an7583_data }, { /* sentinel */ } }; =20 --=20 2.48.1