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([144.202.86.13]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b2fe1680c5fsm8301764a12.49.2025.06.17.02.00.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Jun 2025 02:01:00 -0700 (PDT) From: Pengyu Luo To: Vinod Koul , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Dmitry Baryshkov Cc: linux-arm-msm@vger.kernel.org, dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Pengyu Luo Subject: [PATCH v3 1/2] dt-bindings: dma: qcom,gpi: Document the sc8280xp GPI DMA engine Date: Tue, 17 Jun 2025 17:00:31 +0800 Message-ID: <20250617090032.1487382-2-mitltlatltl@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250617090032.1487382-1-mitltlatltl@gmail.com> References: <20250617090032.1487382-1-mitltlatltl@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Document the GPI DMA engine on the sc8280xp platform. Signed-off-by: Pengyu Luo Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/dma/qcom,gpi.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/dma/qcom,gpi.yaml b/Document= ation/devicetree/bindings/dma/qcom,gpi.yaml index 7052468b1..19764452d 100644 --- a/Documentation/devicetree/bindings/dma/qcom,gpi.yaml +++ b/Documentation/devicetree/bindings/dma/qcom,gpi.yaml @@ -30,6 +30,7 @@ properties: - qcom,sa8775p-gpi-dma - qcom,sar2130p-gpi-dma - qcom,sc7280-gpi-dma + - qcom,sc8280xp-gpi-dma - qcom,sdx75-gpi-dma - qcom,sm6115-gpi-dma - qcom,sm6375-gpi-dma --=20 2.49.0 From nobody Fri Oct 10 09:49:28 2025 Received: from mail-pg1-f181.google.com (mail-pg1-f181.google.com [209.85.215.181]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DB484292B4E; Tue, 17 Jun 2025 09:01:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.181 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750150868; cv=none; b=L+76lZIrViupjuJRiaWqf0W4tOICfVpSc6k/5152lldUDv+57vxtN2BW/m3jcsFwallb46Fvxx8l7aAwJq7WKsU0J2GdoHkSIFQkBJiaIf7O/a+SLxAddnbgmY5kfu9w2VE0fYKx5mNArfhI3xm2UWVFiZn5U7SWYsKM6qv4DeY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750150868; c=relaxed/simple; bh=jQJFIcnet17puDVJquDf632zY0ugyrMCbo1J8Pf6LVw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=uNtn6Dmn7M0fA8U9epEPec2NF2HIdENFqs0jYr4VlW6JiMjlcVtDyDdMSTKM1prXg1yQMNhDsP++tUqNaJ8QtiCA7OVhpEWerIio3w2uqBjAdQMX1fxkfB0wIqIpDtf1PSAXo6ymBUatPXJlTs4oQO0R+UKlI+1pctnxuQO7os0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=PO0bW68W; arc=none smtp.client-ip=209.85.215.181 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="PO0bW68W" Received: by mail-pg1-f181.google.com with SMTP id 41be03b00d2f7-b26f5f47ba1so4448125a12.1; Tue, 17 Jun 2025 02:01:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1750150865; x=1750755665; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8xk0vWPJp0UoI4wa9bfHksdLTaLUSobn+WBq8Y9slD4=; b=PO0bW68WsRJ//jaNOyZaUybpYGylsuP/0gB/IcYhjWbGPu6V6v/qpFoy7Ndy2S5x+N /wMZNQmQ0jTCMCYqY/i67AeMeVdXcmbm760KI54PbnL6oUsLftLWsyX+1QfGJrWvAsMv iPvXVLvLdqav9UCqzlBIxMZxy6DR81sJ24tguiwRUBn9L9mJVoJaPRR3++PYu/K/9rLA t0NGhLzeq/EeTY1zseGxdXv1yOxPRQnCPg9oNDhcGeBy4tYXG86KuJK2xlkFiYL0lyy8 oTJAenXMEPBVErN9unD0XicsQ9tPKFo+OHkYkjvzCuBpVnYqPQyQFK1Xft0AiyGipEZl Jb1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1750150865; x=1750755665; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8xk0vWPJp0UoI4wa9bfHksdLTaLUSobn+WBq8Y9slD4=; b=BvZ4ep5YvwtiViGMbcZ56Pmny4xoKIl6FV2tcfReayPg4c0rbsrAKEKZJvdfctgmnD 20lOLxT/9S/v31CAqGakbIRpewKxF3HHTLJWytKS62advi8htSw1HB+3IGq37+XpNDg6 3LXMWGlcnBkutFVEJE6Iqgu87EWyGcrgT4zbSdwnbYODim/nUyNFGxLYCjv1oKltHTZZ CHw2vxWcijP5eGJoDHXKjdxbd/YeJba9RgbSW9DWQRIXFU46ENK2SaqdCdme0HdZp8T0 ElUI2KedGniL1tQjTiRrrpBrzJmh6J/G7OvLH44htvMnWJECDRVQigRk1ruUd2g3DXO5 uLog== X-Forwarded-Encrypted: i=1; AJvYcCVVZPyoaX691I9EX7Cp4RMddOzptqYSRQzfdPWxIIqW310jTrgrUu3OhzXLxJA+43SjMJ7qyeu0tPFYYSGm@vger.kernel.org, AJvYcCVuV5g89eDPzcyOzyzizhG7pzCEv7piKHz7AR9KeWQF/WrmUr6cgDPpuKNmElmyxQzMjioHcn0lGzCA@vger.kernel.org, AJvYcCW0SaYkxjqbA4sa9ya18Y9iLMmKIL8Za+xdEfwEhkp02RDHWreT1J86fsgveQg+wu4S9tXn49EQWC4/@vger.kernel.org X-Gm-Message-State: AOJu0YxpaF+J3gAKZuRevy1f1aVXtqX/o24FPFGLDucQo/2Z1vtqenqM tMYtDgdSDKUQNdpQU/9bGBplVlnWUlXyVaO2wOeUQSrf/4sdGZ4NEZzJ X-Gm-Gg: ASbGncs7gRf73WuJThlCn+8h0VOyL7BWzg7ASNdKXc1MNapd0bS4lUI+bKaOdrBEHSO kNupPXyddvsS3+vj0zWAVRgEvLsjPdyOz4uQcEwU+8txnt0MFppxgMyTEEJtzmVpQmOAQizofz0 WHvaWeNyH67vw/HDhOF+OXHc3XS0k5ApQDs/q/XPjEcHNe04S4Qffaw41hmdOIVvVrBz0UH3mWS roMIaDlhyBhwAALZ/USouE5U+6RANJun1WmdwlnUqkHYMskhSG7Ha5GJqea7bhXC1+jYUCjlYf4 yRYkI0IYthljucKkCBf8T78rDZfKdkiVdYXIb/F1G2rJpVgfBVSDsd2qHiwv X-Google-Smtp-Source: AGHT+IFysbPHSDpW0a9Dw7zOwz9GKIkU4pc1rUB+zbjuJDSR/LB1t7s16iF1ZCkuf5QyTgqfQ0WpMw== X-Received: by 2002:a05:6300:41:b0:1f5:591b:4f7a with SMTP id adf61e73a8af0-21fbd5e0f84mr17264606637.38.1750150865002; Tue, 17 Jun 2025 02:01:05 -0700 (PDT) Received: from nuvole.. ([144.202.86.13]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b2fe1680c5fsm8301764a12.49.2025.06.17.02.01.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Jun 2025 02:01:04 -0700 (PDT) From: Pengyu Luo To: Vinod Koul , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Dmitry Baryshkov Cc: linux-arm-msm@vger.kernel.org, dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Pengyu Luo Subject: [PATCH v3 2/2] arm64: dts: qcom: sc8280xp: Describe GPI DMA controller nodes Date: Tue, 17 Jun 2025 17:00:32 +0800 Message-ID: <20250617090032.1487382-3-mitltlatltl@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250617090032.1487382-1-mitltlatltl@gmail.com> References: <20250617090032.1487382-1-mitltlatltl@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" SPI on SC8280XP requires DMA (GSI) mode to function properly. Without it, SPI controllers fall back to FIFO mode, which causes: [ 0.901296] geni_spi 898000.spi: error -ENODEV: Failed to get tx DMA ch [ 0.901305] geni_spi 898000.spi: FIFO mode disabled, but couldn't get DM= A, fall back to FIFO mode ... [ 45.605974] goodix-spi-hid spi0.0: SPI transfer timed out [ 45.605988] geni_spi 898000.spi: Can't set CS when prev xfer running [ 46.621555] spi_master spi0: failed to transfer one message from queue [ 46.621568] spi_master spi0: noqueue transfer failed [ 46.621577] goodix-spi-hid spi0.0: spi transfer error: -110 [ 46.621585] goodix-spi-hid spi0.0: probe with driver goodix-spi-hid fail= ed with error -110 Therefore, describe GPI DMA controller nodes for qup{0,1,2}, and describe DMA channels for SPI and I2C, UART is excluded for now, as it does not yet support this mode. Note that, since there is no public schematic, this is derived from Windows drivers. The drivers do not expose any DMA channel mask information, so all available channels are enabled. Signed-off-by: Pengyu Luo --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 368 +++++++++++++++++++++++++ 1 file changed, 368 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/q= com/sc8280xp.dtsi index 87555a119..5b2e62356 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -912,6 +913,32 @@ gpu_speed_bin: gpu-speed-bin@18b { }; }; =20 + gpi_dma2: dma-controller@800000 { + compatible =3D "qcom,sc8280xp-gpi-dma", "qcom,sm6350-gpi-dma"; + reg =3D <0 0x00800000 0 0x60000>; + + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + ; + + dma-channels =3D <12>; + dma-channel-mask =3D <0xfff>; + #dma-cells =3D <3>; + + iommus =3D <&apps_smmu 0xb6 0x0>; + + status =3D "disabled"; + }; + qup2: geniqup@8c0000 { compatible =3D "qcom,geni-se-qup"; reg =3D <0 0x008c0000 0 0x2000>; @@ -939,6 +966,12 @@ i2c16: i2c@880000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 = 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma2 0 0 QCOM_GPI_I2C>, + <&gpi_dma2 1 0 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -955,6 +988,12 @@ spi16: spi@880000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 = 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma2 0 0 QCOM_GPI_SPI>, + <&gpi_dma2 1 0 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -971,6 +1010,12 @@ i2c17: i2c@884000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 = 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma2 0 1 QCOM_GPI_I2C>, + <&gpi_dma2 1 1 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -987,6 +1032,12 @@ spi17: spi@884000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 = 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma2 0 1 QCOM_GPI_SPI>, + <&gpi_dma2 1 1 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1017,6 +1068,12 @@ i2c18: i2c@888000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 = 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma2 0 2 QCOM_GPI_I2C>, + <&gpi_dma2 1 2 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1033,6 +1090,12 @@ spi18: spi@888000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 = 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma2 0 2 QCOM_GPI_SPI>, + <&gpi_dma2 1 2 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1067,6 +1130,12 @@ i2c19: i2c@88c000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 = 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma2 0 3 QCOM_GPI_I2C>, + <&gpi_dma2 1 3 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1083,6 +1152,12 @@ spi19: spi@88c000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 = 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma2 0 3 QCOM_GPI_SPI>, + <&gpi_dma2 1 3 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1099,6 +1174,12 @@ i2c20: i2c@890000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 = 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma2 0 4 QCOM_GPI_I2C>, + <&gpi_dma2 1 4 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1115,6 +1196,12 @@ spi20: spi@890000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 = 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma2 0 4 QCOM_GPI_SPI>, + <&gpi_dma2 1 4 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1131,6 +1218,12 @@ i2c21: i2c@894000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma2 0 5 QCOM_GPI_I2C>, + <&gpi_dma2 1 5 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1147,6 +1240,12 @@ spi21: spi@894000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 = 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma2 0 5 QCOM_GPI_SPI>, + <&gpi_dma2 1 5 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1163,6 +1262,12 @@ i2c22: i2c@898000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma2 0 6 QCOM_GPI_I2C>, + <&gpi_dma2 1 6 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1179,6 +1284,12 @@ spi22: spi@898000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 = 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma2 0 6 QCOM_GPI_SPI>, + <&gpi_dma2 1 6 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1195,6 +1306,12 @@ i2c23: i2c@89c000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma2 0 7 QCOM_GPI_I2C>, + <&gpi_dma2 1 7 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1211,10 +1328,43 @@ spi23: spi@89c000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 = 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma2 0 7 QCOM_GPI_SPI>, + <&gpi_dma2 1 7 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; }; =20 + gpi_dma0: dma-controller@900000 { + compatible =3D "qcom,sc8280xp-gpi-dma", "qcom,sm6350-gpi-dma"; + reg =3D <0 0x00900000 0 0x60000>; + + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + ; + + dma-channels =3D <13>; + dma-channel-mask =3D <0x1fff>; + #dma-cells =3D <3>; + + iommus =3D <&apps_smmu 0x576 0x0>; + + status =3D "disabled"; + }; + qup0: geniqup@9c0000 { compatible =3D "qcom,geni-se-qup"; reg =3D <0 0x009c0000 0 0x6000>; @@ -1242,6 +1392,12 @@ i2c0: i2c@980000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma0 0 0 QCOM_GPI_I2C>, + <&gpi_dma0 1 0 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1258,6 +1414,12 @@ spi0: spi@980000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma0 0 0 QCOM_GPI_SPI>, + <&gpi_dma0 1 0 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1274,6 +1436,12 @@ i2c1: i2c@984000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma0 0 1 QCOM_GPI_I2C>, + <&gpi_dma0 1 1 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1290,6 +1458,12 @@ spi1: spi@984000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma0 0 1 QCOM_GPI_SPI>, + <&gpi_dma0 1 1 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1306,6 +1480,12 @@ i2c2: i2c@988000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma0 0 2 QCOM_GPI_I2C>, + <&gpi_dma0 1 2 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1322,6 +1502,12 @@ spi2: spi@988000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma0 0 2 QCOM_GPI_SPI>, + <&gpi_dma0 1 2 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1352,6 +1538,12 @@ i2c3: i2c@98c000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma0 0 3 QCOM_GPI_I2C>, + <&gpi_dma0 1 3 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1368,6 +1560,12 @@ spi3: spi@98c000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma0 0 3 QCOM_GPI_SPI>, + <&gpi_dma0 1 3 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1384,6 +1582,12 @@ i2c4: i2c@990000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma0 0 4 QCOM_GPI_I2C>, + <&gpi_dma0 1 4 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1400,6 +1604,12 @@ spi4: spi@990000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma0 0 4 QCOM_GPI_SPI>, + <&gpi_dma0 1 4 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1416,6 +1626,12 @@ i2c5: i2c@994000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma0 0 5 QCOM_GPI_I2C>, + <&gpi_dma0 1 5 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1432,6 +1648,12 @@ spi5: spi@994000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma0 0 5 QCOM_GPI_SPI>, + <&gpi_dma0 1 5 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1448,6 +1670,12 @@ i2c6: i2c@998000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma0 0 6 QCOM_GPI_I2C>, + <&gpi_dma0 1 6 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1464,6 +1692,12 @@ spi6: spi@998000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma0 0 6 QCOM_GPI_SPI>, + <&gpi_dma0 1 6 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1480,6 +1714,12 @@ i2c7: i2c@99c000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma0 0 7 QCOM_GPI_I2C>, + <&gpi_dma0 1 7 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1496,10 +1736,42 @@ spi7: spi@99c000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma0 0 7 QCOM_GPI_SPI>, + <&gpi_dma0 1 7 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; }; =20 + gpi_dma1: dma-controller@a00000 { + compatible =3D "qcom,sc8280xp-gpi-dma", "qcom,sm6350-gpi-dma"; + reg =3D <0 0x00a00000 0 0x60000>; + + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + ; + + dma-channels =3D <12>; + dma-channel-mask =3D <0xfff>; + #dma-cells =3D <3>; + + iommus =3D <&apps_smmu 0x96 0x0>; + + status =3D "disabled"; + }; + qup1: geniqup@ac0000 { compatible =3D "qcom,geni-se-qup"; reg =3D <0 0x00ac0000 0 0x6000>; @@ -1527,6 +1799,12 @@ i2c8: i2c@a80000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma1 0 0 QCOM_GPI_I2C>, + <&gpi_dma1 1 0 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1543,6 +1821,12 @@ spi8: spi@a80000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma1 0 0 QCOM_GPI_SPI>, + <&gpi_dma1 1 0 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1559,6 +1843,12 @@ i2c9: i2c@a84000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma1 0 1 QCOM_GPI_I2C>, + <&gpi_dma1 1 1 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1575,6 +1865,12 @@ spi9: spi@a84000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma1 0 1 QCOM_GPI_SPI>, + <&gpi_dma1 1 1 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1591,6 +1887,12 @@ i2c10: i2c@a88000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma1 0 2 QCOM_GPI_I2C>, + <&gpi_dma1 1 2 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1607,6 +1909,12 @@ spi10: spi@a88000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma1 0 2 QCOM_GPI_SPI>, + <&gpi_dma1 1 2 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1623,6 +1931,12 @@ i2c11: i2c@a8c000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma1 0 3 QCOM_GPI_I2C>, + <&gpi_dma1 1 3 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1639,6 +1953,12 @@ spi11: spi@a8c000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma1 0 3 QCOM_GPI_SPI>, + <&gpi_dma1 1 3 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1655,6 +1975,12 @@ i2c12: i2c@a90000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma1 0 4 QCOM_GPI_I2C>, + <&gpi_dma1 1 4 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1671,6 +1997,12 @@ spi12: spi@a90000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma1 0 4 QCOM_GPI_SPI>, + <&gpi_dma1 1 4 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1687,6 +2019,12 @@ i2c13: i2c@a94000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma1 0 5 QCOM_GPI_I2C>, + <&gpi_dma1 1 5 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1703,6 +2041,12 @@ spi13: spi@a94000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma1 0 5 QCOM_GPI_SPI>, + <&gpi_dma1 1 5 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1719,6 +2063,12 @@ i2c14: i2c@a98000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma1 0 6 QCOM_GPI_I2C>, + <&gpi_dma1 1 6 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1735,6 +2085,12 @@ spi14: spi@a98000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma1 0 6 QCOM_GPI_SPI>, + <&gpi_dma1 1 6 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1751,6 +2107,12 @@ i2c15: i2c@a9c000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma1 0 7 QCOM_GPI_I2C>, + <&gpi_dma1 1 7 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1767,6 +2129,12 @@ spi15: spi@a9c000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma1 0 7 QCOM_GPI_SPI>, + <&gpi_dma1 1 7 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; }; --=20 2.49.0