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([188.163.112.61]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-553ac1ab9c8sm1800427e87.114.2025.06.17.00.03.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Jun 2025 00:03:42 -0700 (PDT) From: Svyatoslav Ryhel To: Rob Herring , Conor Dooley , Thierry Reding , Thierry Reding , Jonathan Hunter , Svyatoslav Ryhel , David Heidelberg , Ion Agorria Cc: devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 1/2] dt-bindings: arm: tegra: Add Asus VivoTab RT TF600T Date: Tue, 17 Jun 2025 10:03:19 +0300 Message-ID: <20250617070320.9153-2-clamor95@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250617070320.9153-1-clamor95@gmail.com> References: <20250617070320.9153-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Maxim Schwalm Add a compatible for the Asus VivoTab RT TF600T. Signed-off-by: Maxim Schwalm Signed-off-by: Svyatoslav Ryhel Acked-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/arm/tegra.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/tegra.yaml b/Documentati= on/devicetree/bindings/arm/tegra.yaml index 79b027740694..534197a87439 100644 --- a/Documentation/devicetree/bindings/arm/tegra.yaml +++ b/Documentation/devicetree/bindings/arm/tegra.yaml @@ -65,6 +65,10 @@ properties: - asus,tf300tl - asus,tf700t - const: nvidia,tegra30 + - description: Asus VivoTab RT + items: + - const: asus,tf600t + - const: nvidia,tegra30 - description: LG Optimus 4X P880 items: - const: lg,p880 --=20 2.48.1 From nobody Fri Oct 10 09:48:03 2025 Received: from mail-lf1-f44.google.com (mail-lf1-f44.google.com [209.85.167.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B9A5628C5AD; Tue, 17 Jun 2025 07:03:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750143833; cv=none; b=Yi6S2DBoUZJSVv49PgkKbQXWzmyGbY1Xq0bmJVCNfHQ5aAYmm6HRIg142KauAiEq0j3NjE6dpAPTwvazfSkSx2Trs30JLodyntGs95fYuPXmELzjO54z4Fuw+AUKAZyq/ASeXHzJ5L8lWEhO62Pbpio5oJQWUNdAtVmLL6GSlPA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750143833; c=relaxed/simple; bh=ir6KLSwWMa8p3R8JR4+iUEe9NedgI6mkJQmmtN6rwuo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=smiMeSZHTKjcr0DJaDFfwup9u2oA7c5tvqcMNDDVzaA1+guRVW6StSf7R+k/WUypNs9TFtmy0TYHTIboH7YU6YNJQVzUDKb3fjKQejPzdLgqP/gq3fc4ck6/GY+3X2jHiPZU5VzDee5CRfygTmJjCR9N2ORdp0/RaW8KJeIQi5Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=FE9ED7hI; arc=none smtp.client-ip=209.85.167.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="FE9ED7hI" Received: by mail-lf1-f44.google.com with SMTP id 2adb3069b0e04-553b5165cf5so3877458e87.0; Tue, 17 Jun 2025 00:03:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1750143827; x=1750748627; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LATLqUKa8K6xPJwNw3izKhLfLOuI9SPfx8OoLgmSMLs=; b=FE9ED7hI4iljrN1wtFCIU2dA+k5LhqDg2FFwGj3igwlovk8nDQ2+TKWyjs3iF5RkvD 41yFW7RvKtdaLddkbdnBP0S291KgEmpSSl3AzQHbjSFuLGPp+QCBO3INDBn9yD4t7Anf e7q9+s5FTAHdcq84mH8TWdQ4GuLVsbwgLvDM35BZKd3chG57xMzyP8Gu/uEDISYByK/z D8LnduDpliVQ5aSQEEOiNhbyxU/ozUal840vccTa+T39Nh+IKuFYQD7TEG3ceFp1+lm6 sb9KY9C1lHtV9K7FPczP9KsIxIJHjZ3kjIxZXVjFI6rpk3NDPyGFCmiZcGAgm0PnZA7P n2GA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1750143827; x=1750748627; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LATLqUKa8K6xPJwNw3izKhLfLOuI9SPfx8OoLgmSMLs=; b=Cb9C/d9GQmkeBCgzM45EPcCBKW/lK2XUzznlTQiPQUMomAmgjnFwb5TBOlo9v9k/jn 9L6L2qEDfMx/gs++a+yn4ILNRup3uYLiTgPTECqZEeceIv7W+JVdnERSJCLmD+5egPiN O/XpPqn3jyV70IgaypA7bGI8zLtw85lN84CKXIsUgLhl7LY4aysjnJ24FRK/9+k5VWCV +Qv3tMnMHeGdpxO/M3+V4Z8lUWLbO5/E09sLWg1XNckqEOIHMUnaLoM0z2sRKi0nBH96 nQ0IaCMbbwcjTu8ethQAsizG3+neWKEh17r0WbsUfqnKD/fhh965oleV/93f0dz5XN8F rSMg== X-Forwarded-Encrypted: i=1; AJvYcCUOXYn7IW3kjH+bbazxKbpM1WBWWmO4UmbozMAVJGceTGKupwlUAIgdU2YkG2GeW85P6rF5hMKobaB7Iek=@vger.kernel.org, AJvYcCVgJYkVq7HDPNA7FwQu8NzFBviBUhMmYG98/JV0Dm7M/3CgaP3EUbccjn6s48fnTLmeoBcwiPoH3wDdA0s=@vger.kernel.org X-Gm-Message-State: AOJu0YyDIXfqG5vynz7lrvNMmFY8VH5LXGU9buFOli1MbDv7KtO5ye/l YoZ5HNVQSCWCzNHaXW2NSKFL2tm2vNLqYivdMINDu/ITm7167kXFOWCk X-Gm-Gg: ASbGncv75SPXd6CvShhQnu15J1smcIDfhngNNX2TgnbKswbh4rbJQ0Qw9WiRfnbGnzm jWBW4ktoRQoCoMRZe0x2vqBH6BVWCS6SX3f1hag7j26XHIGZlQVujKuKZdT97f5eAi3JdrHsgyC rBEPOfhXjbwEx8kM3bgQ2TEAgZnyfyrigBHtpTP3ZOG8BvTK10uK3dkrc0O2IWECACZRGB68FhO MVBcHUniPfE1BFLrVg54LhsElssC9f9fG5Mxv+h0ESidhnTy14eX3RElisyu+kAt/1yeBDuHO6m YsCBQZ/KtQ1U4aTQ9mmOQnas2R1BfPQTRQlDGN120BLjApjP5GBXNw== X-Google-Smtp-Source: AGHT+IHuoxFwb1MdcT+4+XQJPjykq0f89E5ajdHyaca/SUpjF0AdhjOzglMr23k7D0hp6dRT/omgkw== X-Received: by 2002:a05:6512:10d1:b0:550:e608:410b with SMTP id 2adb3069b0e04-553b6f1a12cmr3043928e87.33.1750143825982; Tue, 17 Jun 2025 00:03:45 -0700 (PDT) Received: from xeon.. ([188.163.112.61]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-553ac1ab9c8sm1800427e87.114.2025.06.17.00.03.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Jun 2025 00:03:45 -0700 (PDT) From: Svyatoslav Ryhel To: Rob Herring , Conor Dooley , Thierry Reding , Thierry Reding , Jonathan Hunter , Svyatoslav Ryhel , David Heidelberg , Ion Agorria Cc: devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 2/2] ARM: tegra: Add device-tree for ASUS VivoTab RT TF600T Date: Tue, 17 Jun 2025 10:03:20 +0300 Message-ID: <20250617070320.9153-3-clamor95@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250617070320.9153-1-clamor95@gmail.com> References: <20250617070320.9153-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add device-tree for ASUS VivoTab RT TF600T, which is NVIDIA Tegra30-based tablet device with Windows RT. Signed-off-by: Svyatoslav Ryhel --- arch/arm/boot/dts/nvidia/Makefile | 1 + .../boot/dts/nvidia/tegra30-asus-tf600t.dts | 2500 +++++++++++++++++ 2 files changed, 2501 insertions(+) create mode 100644 arch/arm/boot/dts/nvidia/tegra30-asus-tf600t.dts diff --git a/arch/arm/boot/dts/nvidia/Makefile b/arch/arm/boot/dts/nvidia/M= akefile index 1890d9075a87..7c1d3cb5dcf0 100644 --- a/arch/arm/boot/dts/nvidia/Makefile +++ b/arch/arm/boot/dts/nvidia/Makefile @@ -36,6 +36,7 @@ dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) +=3D \ tegra30-asus-tf300t.dtb \ tegra30-asus-tf300tg.dtb \ tegra30-asus-tf300tl.dtb \ + tegra30-asus-tf600t.dtb \ tegra30-asus-tf700t.dtb \ tegra30-beaver.dtb \ tegra30-cardhu-a02.dtb \ diff --git a/arch/arm/boot/dts/nvidia/tegra30-asus-tf600t.dts b/arch/arm/bo= ot/dts/nvidia/tegra30-asus-tf600t.dts new file mode 100644 index 000000000000..5d9e23a43820 --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra30-asus-tf600t.dts @@ -0,0 +1,2500 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include +#include +#include +#include + +#include "tegra30.dtsi" +#include "tegra30-cpu-opp.dtsi" +#include "tegra30-cpu-opp-microvolt.dtsi" + +/ { + model =3D "Asus VivoTab RT TF600T"; + compatible =3D "asus,tf600t", "nvidia,tegra30"; + chassis-type =3D "convertible"; + + aliases { + mmc0 =3D &sdmmc4; /* eMMC */ + mmc1 =3D &sdmmc1; /* uSD slot */ + mmc2 =3D &sdmmc3; /* WiFi */ + + rtc0 =3D &pmic; + rtc1 =3D "/rtc@7000e000"; + + display1 =3D &hdmi; + + serial1 =3D &uartc; /* Bluetooth */ + serial2 =3D &uartb; /* GPS */ + }; + + /* + * The decompressor and also some bootloaders rely on a + * pre-existing /chosen node to be available to insert the + * command line and merge other ATAGS info. + */ + chosen {}; + + memory@80000000 { + reg =3D <0x80000000 0x80000000>; + }; + + reserved-memory { + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + + linux,cma@80000000 { + compatible =3D "shared-dma-pool"; + alloc-ranges =3D <0x80000000 0x30000000>; + size =3D <0x10000000>; /* 256MiB */ + linux,cma-default; + reusable; + }; + }; + + host1x@50000000 { + hdmi: hdmi@54280000 { + status =3D "okay"; + + hdmi-supply =3D <&hdmi_5v0_sys>; + pll-supply =3D <&vdd_1v8_vio>; + vdd-supply =3D <&vdd_3v3_sys>; + + nvidia,hpd-gpio =3D <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; + nvidia,ddc-i2c-bus =3D <&hdmi_ddc>; + }; + }; + + vde@6001a000 { + assigned-clocks =3D <&tegra_car TEGRA30_CLK_VDE>; + assigned-clock-parents =3D <&tegra_car TEGRA30_CLK_PLL_P>; + assigned-clock-rates =3D <408000000>; + }; + + pinmux@70000868 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&state_default>; + + state_default: pinmux { + /* SDMMC1 pinmux */ + sdmmc1-clk { + nvidia,pins =3D "sdmmc1_clk_pz0"; + nvidia,function =3D "sdmmc1"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + }; + sdmmc1-cmd { + nvidia,pins =3D "sdmmc1_dat3_py4", + "sdmmc1_dat2_py5", + "sdmmc1_dat1_py6", + "sdmmc1_dat0_py7", + "sdmmc1_cmd_pz1"; + nvidia,function =3D "sdmmc1"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + }; + sdmmc1-cd { + nvidia,pins =3D "gmi_iordy_pi5"; + nvidia,function =3D "rsvd1"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + }; + sdmmc1-wp { + nvidia,pins =3D "vi_d11_pt3"; + nvidia,function =3D "rsvd2"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + }; + + /* SDMMC2 pinmux */ + vi-d1-pd5 { + nvidia,pins =3D "vi_d1_pd5", + "vi_d2_pl0", + "vi_d3_pl1", + "vi_d5_pl3", + "vi_d7_pl5"; + nvidia,function =3D "sdmmc2"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + }; + vi-d8-pl6 { + nvidia,pins =3D "vi_d8_pl6", + "vi_d9_pl7"; + nvidia,function =3D "sdmmc2"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + nvidia,lock =3D <0>; + nvidia,io-reset =3D <0>; + }; + + /* SDMMC3 pinmux */ + sdmmc3-clk { + nvidia,pins =3D "sdmmc3_clk_pa6"; + nvidia,function =3D "sdmmc3"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + }; + sdmmc3-cmd { + nvidia,pins =3D "sdmmc3_cmd_pa7", + "sdmmc3_dat0_pb7", + "sdmmc3_dat1_pb6", + "sdmmc3_dat2_pb5", + "sdmmc3_dat3_pb4", + "sdmmc3_dat4_pd1", + "sdmmc3_dat5_pd0", + "sdmmc3_dat6_pd3", + "sdmmc3_dat7_pd4"; + nvidia,function =3D "sdmmc3"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + }; + + /* SDMMC4 pinmux */ + sdmmc4-clk { + nvidia,pins =3D "sdmmc4_clk_pcc4"; + nvidia,function =3D "sdmmc4"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + }; + sdmmc4-cmd { + nvidia,pins =3D "sdmmc4_cmd_pt7", + "sdmmc4_dat0_paa0", + "sdmmc4_dat1_paa1", + "sdmmc4_dat2_paa2", + "sdmmc4_dat3_paa3", + "sdmmc4_dat4_paa4", + "sdmmc4_dat5_paa5", + "sdmmc4_dat6_paa6", + "sdmmc4_dat7_paa7"; + nvidia,function =3D "sdmmc4"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + }; + sdmmc4-rst-n { + nvidia,pins =3D "sdmmc4_rst_n_pcc3"; + nvidia,function =3D "rsvd2"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + }; + cam-mclk { + nvidia,pins =3D "cam_mclk_pcc0"; + nvidia,function =3D "vi_alt3"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + }; + + /* I2C pinmux */ + gen1-i2c { + nvidia,pins =3D "gen1_i2c_scl_pc4", + "gen1_i2c_sda_pc5"; + nvidia,function =3D "i2c1"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + nvidia,open-drain =3D ; + nvidia,lock =3D ; + }; + gen2-i2c { + nvidia,pins =3D "gen2_i2c_scl_pt5", + "gen2_i2c_sda_pt6"; + nvidia,function =3D "i2c2"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + nvidia,open-drain =3D ; + nvidia,lock =3D ; + }; + cam-i2c { + nvidia,pins =3D "cam_i2c_scl_pbb1", + "cam_i2c_sda_pbb2"; + nvidia,function =3D "i2c3"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + nvidia,open-drain =3D ; + nvidia,lock =3D ; + }; + ddc-i2c { + nvidia,pins =3D "ddc_scl_pv4", + "ddc_sda_pv5"; + nvidia,function =3D "i2c4"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + nvidia,lock =3D ; + }; + pwr-i2c { + nvidia,pins =3D "pwr_i2c_scl_pz6", + "pwr_i2c_sda_pz7"; + nvidia,function =3D "i2cpwr"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + nvidia,open-drain =3D ; + nvidia,lock =3D ; + }; + hotplug-i2c { + nvidia,pins =3D "pu4"; + nvidia,function =3D "rsvd4"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + }; + + /* HDMI pinmux */ + hdmi-cec { + nvidia,pins =3D "hdmi_cec_pee3"; + nvidia,function =3D "cec"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + nvidia,open-drain =3D ; + nvidia,lock =3D ; + }; + hdmi-hpd { + nvidia,pins =3D "hdmi_int_pn7"; + nvidia,function =3D "hdmi"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + }; + + /* UART-A */ + ulpi-data0-po1 { + nvidia,pins =3D "ulpi_data0_po1"; + nvidia,function =3D "uarta"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + }; + ulpi-data1-po2 { + nvidia,pins =3D "ulpi_data1_po2"; + nvidia,function =3D "uarta"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + }; + ulpi-data5-po6 { + nvidia,pins =3D "ulpi_data5_po6"; + nvidia,function =3D "uarta"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + }; + ulpi-data7-po0 { + nvidia,pins =3D "ulpi_data7_po0", + "ulpi_data2_po3", + "ulpi_data3_po4", + "ulpi_data4_po5", + "ulpi_data6_po7"; + nvidia,function =3D "uarta"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + }; + + /* UART-B */ + uartb-txd-rts { + nvidia,pins =3D "uart2_txd_pc2", + "uart2_rts_n_pj6"; + nvidia,function =3D "uartb"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + }; + uartb-rxd-cts { + nvidia,pins =3D "uart2_rxd_pc3", + "uart2_cts_n_pj5"; + nvidia,function =3D "uartb"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + }; + + /* UART-C */ + uartc-rxd-cts { + nvidia,pins =3D "uart3_cts_n_pa1", + "uart3_rxd_pw7"; + nvidia,function =3D "uartc"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + }; + uartc-txd-rts { + nvidia,pins =3D "uart3_rts_n_pc0", + "uart3_txd_pw6"; + nvidia,function =3D "uartc"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + }; + + /* UART-D */ + ulpi-nxt-py2 { + nvidia,pins =3D "ulpi_nxt_py2"; + nvidia,function =3D "uartd"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + }; + ulpi-clk-py0 { + nvidia,pins =3D "ulpi_clk_py0", + "ulpi_dir_py1", + "ulpi_stp_py3"; + nvidia,function =3D "uartd"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + }; + + /* I2S pinmux */ + dap-i2s0 { + nvidia,pins =3D "dap1_fs_pn0", + "dap1_din_pn1", + "dap1_dout_pn2", + "dap1_sclk_pn3"; + nvidia,function =3D "i2s0"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + }; + dap-i2s1 { + nvidia,pins =3D "dap2_fs_pa2", + "dap2_sclk_pa3", + "dap2_din_pa4", + "dap2_dout_pa5"; + nvidia,function =3D "i2s1"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + }; + dap3-fs { + nvidia,pins =3D "dap3_fs_pp0"; + nvidia,function =3D "i2s2"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + }; + dap3-din { + nvidia,pins =3D "dap3_din_pp1"; + nvidia,function =3D "i2s2"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + }; + dap3-dout { + nvidia,pins =3D "dap3_dout_pp2", + "dap3_sclk_pp3"; + nvidia,function =3D "i2s2"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + }; + dap-i2s3 { + nvidia,pins =3D "dap4_fs_pp4", + "dap4_din_pp5", + "dap4_dout_pp6", + "dap4_sclk_pp7"; + nvidia,function =3D "i2s3"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + }; + i2s4 { + nvidia,pins =3D "pbb7"; + nvidia,function =3D "i2s4"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + }; + + /* Sensors pinmux */ + nct-irq { + nvidia,pins =3D "pcc2"; + nvidia,function =3D "i2s4"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + }; + hall { + nvidia,pins =3D "pbb6"; + nvidia,function =3D "vgp6"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + }; + + /* Asus EC pinmux */ + ec-irqs { + nvidia,pins =3D "kb_row10_ps2", + "kb_row15_ps7"; + nvidia,function =3D "kbc"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + }; + ec-reqs { + nvidia,pins =3D "kb_col1_pq1"; + nvidia,function =3D "kbc"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + }; + + /* Memory type bootstrap */ + mem-boostraps { + nvidia,pins =3D "gmi_ad4_pg4", + "gmi_ad5_pg5"; + nvidia,function =3D "nand"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + }; + + /* PCI-e pinmux */ + pex-l2-rst-n { + nvidia,pins =3D "pex_l2_rst_n_pcc6", + "pex_l0_rst_n_pdd1", + "pex_l1_rst_n_pdd5"; + nvidia,function =3D "pcie"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + }; + pex-l2-clkreq-n { + nvidia,pins =3D "pex_l2_clkreq_n_pcc7", + "pex_l0_prsnt_n_pdd0", + "pex_l0_clkreq_n_pdd2", + "pex_wake_n_pdd3", + "pex_l1_prsnt_n_pdd4", + "pex_l1_clkreq_n_pdd6", + "pex_l2_prsnt_n_pdd7"; + nvidia,function =3D "pcie"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + }; + + /* Display A pinmux */ + lcd-pwr0-pb2 { + nvidia,pins =3D "lcd_pwr0_pb2", + "lcd_pclk_pb3", + "lcd_pwr1_pc1", + "lcd_d0_pe0", + "lcd_d1_pe1", + "lcd_d2_pe2", + "lcd_d3_pe3", + "lcd_d4_pe4", + "lcd_d5_pe5", + "lcd_d6_pe6", + "lcd_d7_pe7", + "lcd_d8_pf0", + "lcd_d9_pf1", + "lcd_d10_pf2", + "lcd_d11_pf3", + "lcd_d12_pf4", + "lcd_d13_pf5", + "lcd_d14_pf6", + "lcd_d15_pf7", + "lcd_de_pj1", + "lcd_hsync_pj3", + "lcd_vsync_pj4", + "lcd_d16_pm0", + "lcd_d17_pm1", + "lcd_d18_pm2", + "lcd_d19_pm3", + "lcd_d20_pm4", + "lcd_d21_pm5", + "lcd_d22_pm6", + "lcd_d23_pm7", + "lcd_dc0_pn6", + "lcd_sdin_pz2"; + nvidia,function =3D "displaya"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + }; + lcd-cs0-n-pn4 { + nvidia,pins =3D "lcd_sdout_pn5", + "lcd_wr_n_pz3", + "lcd_pwr2_pc6", + "lcd_dc1_pd2"; + nvidia,function =3D "displaya"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + }; + + blink { + nvidia,pins =3D "clk_32k_out_pa0"; + nvidia,function =3D "blink"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + }; + + /* KBC keys */ + kb-col0 { + nvidia,pins =3D "kb_col0_pq0", + "kb_row1_pr1", + "kb_row3_pr3", + "kb_row7_pr7", + "kb_row8_ps0"; + nvidia,function =3D "kbc"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + }; + kb-col5 { + nvidia,pins =3D "kb_col5_pq5", + "kb_col7_pq7", + "kb_row2_pr2", + "kb_row4_pr4", + "kb_row5_pr5", + "kb_row13_ps5"; + nvidia,function =3D "kbc"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + }; + + gmi-cs0-n-pj0 { + nvidia,pins =3D "gmi_wp_n_pc7", + "gmi_wait_pi7", + "gmi_cs0_n_pj0", + "gmi_cs1_n_pj2", + "gmi_cs2_n_pk3", + "gmi_cs3_n_pk4"; + nvidia,function =3D "rsvd1"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + }; + + vi-pclk-pt0 { + nvidia,pins =3D "vi_pclk_pt0"; + nvidia,function =3D "rsvd1"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + nvidia,lock =3D <0>; + nvidia,io-reset =3D <0>; + }; + + /* GPIO keys pinmux */ + power-key { + nvidia,pins =3D "pv0"; + nvidia,function =3D "rsvd1"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + }; + vol-keys { + nvidia,pins =3D "kb_col3_pq3", + "kb_col4_pq4"; + nvidia,function =3D "rsvd4"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + }; + + /* Bluetooth */ + bt-shutdown { + nvidia,pins =3D "pu0"; + nvidia,function =3D "rsvd4"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + }; + bt-dev-wake { + nvidia,pins =3D "pu1"; + nvidia,function =3D "rsvd1"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + }; + bt-host-wake { + nvidia,pins =3D "pu6"; + nvidia,function =3D "rsvd4"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + }; + + pu2 { + nvidia,pins =3D "pu2"; + nvidia,function =3D "rsvd1"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + }; + pu3 { + nvidia,pins =3D "pu3"; + nvidia,function =3D "rsvd4"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + }; + pcc1 { + nvidia,pins =3D "pcc1"; + nvidia,function =3D "rsvd2"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + }; + pv2 { + nvidia,pins =3D "pv2"; + nvidia,function =3D "rsvd2"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + }; + pv3 { + nvidia,pins =3D "pv3"; + nvidia,function =3D "rsvd2"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + }; + + vi-vsync-pd6 { + nvidia,pins =3D "vi_vsync_pd6", + "vi_hsync_pd7"; + nvidia,function =3D "rsvd2"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + nvidia,lock =3D <0>; + nvidia,io-reset =3D <0>; + }; + vi-d10-pt2 { + nvidia,pins =3D "vi_d10_pt2", + "vi_d0_pt4", + "pbb0"; + nvidia,function =3D "rsvd2"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + }; + kb-row0-pr0 { + nvidia,pins =3D "kb_row0_pr0"; + nvidia,function =3D "rsvd4"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + }; + gmi-ad0-pg0 { + nvidia,pins =3D "gmi_ad0_pg0", + "gmi_ad1_pg1", + "gmi_ad2_pg2", + "gmi_ad3_pg3", + "gmi_ad6_pg6", + "gmi_ad7_pg7", + "gmi_wr_n_pi0", + "gmi_oe_n_pi1", + "gmi_dqs_pi2", + "gmi_adv_n_pk0", + "gmi_clk_pk1"; + nvidia,function =3D "nand"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + }; + gmi-ad13-ph5 { + nvidia,pins =3D "gmi_ad13_ph5"; + nvidia,function =3D "nand"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + }; + gmi-ad10-ph2 { + nvidia,pins =3D "gmi_ad10_ph2", + "gmi_ad11_ph3", + "gmi_ad14_ph6"; + nvidia,function =3D "nand"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + }; + gmi-ad12-ph4 { + nvidia,pins =3D "gmi_ad12_ph4", + "gmi_rst_n_pi4", + "gmi_cs7_n_pi6"; + nvidia,function =3D "nand"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + }; + + /* Vibrator control */ + vibrator { + nvidia,pins =3D "gmi_ad11_ph3"; + nvidia,function =3D "nand"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + }; + + /* PWM pinmux */ + pwm-0 { + nvidia,pins =3D "gmi_ad8_ph0"; + nvidia,function =3D "pwm0"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + }; + pwm-2 { + nvidia,pins =3D "pu5"; + nvidia,function =3D "pwm2"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + }; + + gmi-cs-n { + nvidia,pins =3D "gmi_cs4_n_pk2", + "gmi_cs6_n_pi3"; + nvidia,function =3D "gmi"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + }; + + /* Spdif pinmux */ + spdif-out { + nvidia,pins =3D "spdif_out_pk5"; + nvidia,function =3D "spdif"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + }; + spdif-in { + nvidia,pins =3D "spdif_in_pk6"; + nvidia,function =3D "spdif"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + }; + + vi-d4-pl2 { + nvidia,pins =3D "vi_d4_pl2"; + nvidia,function =3D "vi"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + }; + vi-d6-pl4 { + nvidia,pins =3D "vi_d6_pl4"; + nvidia,function =3D "vi"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + nvidia,lock =3D <0>; + nvidia,io-reset =3D <0>; + }; + vi-mclk-pt1 { + nvidia,pins =3D "vi_mclk_pt1"; + nvidia,function =3D "vi"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + }; + + jtag { + nvidia,pins =3D "jtag_rtck_pu7"; + nvidia,function =3D "rtck"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + }; + + crt-sync { + nvidia,pins =3D "crt_hsync_pv6", + "crt_vsync_pv7"; + nvidia,function =3D "crt"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + }; + + clk1-out { + nvidia,pins =3D "clk1_out_pw4"; + nvidia,function =3D "extperiph1"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + }; + clk2-out { + nvidia,pins =3D "clk2_out_pw5"; + nvidia,function =3D "extperiph2"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + }; + clk3-out { + nvidia,pins =3D "clk3_out_pee0"; + nvidia,function =3D "extperiph3"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + }; + sys-clk-req { + nvidia,pins =3D "sys_clk_req_pz5"; + nvidia,function =3D "sysclk"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + }; + + pbb3 { + nvidia,pins =3D "pbb3"; + nvidia,function =3D "vgp3"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + }; + pbb4 { + nvidia,pins =3D "pbb4"; + nvidia,function =3D "vgp4"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + }; + pbb5 { + nvidia,pins =3D "pbb5"; + nvidia,function =3D "vgp5"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + }; + + clk2-req-pcc5 { + nvidia,pins =3D "clk2_req_pcc5", + "clk1_req_pee2"; + nvidia,function =3D "dap"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + }; + clk3-req-pee1 { + nvidia,pins =3D "clk3_req_pee1"; + nvidia,function =3D "dev3"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + }; + + owr { + nvidia,pins =3D "owr"; + nvidia,function =3D "owr"; + nvidia,pull =3D ; + nvidia,tristate =3D ; + nvidia,enable-input =3D ; + }; + + /* GPIO power/drive control */ + drive-dap1 { + nvidia,pins =3D "drive_dap1", + "drive_dap2", + "drive_dbg", + "drive_at5", + "drive_gme", + "drive_ddc", + "drive_ao1", + "drive_uart3"; + nvidia,high-speed-mode =3D ; + nvidia,schmitt =3D ; + nvidia,low-power-mode =3D ; + nvidia,pull-down-strength =3D <31>; + nvidia,pull-up-strength =3D <31>; + nvidia,slew-rate-rising =3D ; + nvidia,slew-rate-falling =3D ; + }; + drive-sdio1 { + nvidia,pins =3D "drive_sdio1", + "drive_sdio3"; + nvidia,high-speed-mode =3D ; + nvidia,schmitt =3D ; + nvidia,pull-down-strength =3D <46>; + nvidia,pull-up-strength =3D <42>; + nvidia,slew-rate-rising =3D ; + nvidia,slew-rate-falling =3D ; + }; + drive-sdmmc4 { + nvidia,pins =3D "drive_gma", + "drive_gmb", + "drive_gmc", + "drive_gmd"; + nvidia,pull-down-strength =3D <9>; + nvidia,pull-up-strength =3D <9>; + nvidia,slew-rate-rising =3D ; + nvidia,slew-rate-falling =3D ; + }; + }; + }; + + uartb: serial@70006040 { + compatible =3D "nvidia,tegra30-hsuart"; + reset-names =3D "serial"; + /delete-property/ reg-shift; + status =3D "okay"; + + /* Broadcom GPS BCM47511 */ + }; + + uartc: serial@70006200 { + compatible =3D "nvidia,tegra30-hsuart"; + reset-names =3D "serial"; + /delete-property/ reg-shift; + status =3D "okay"; + + nvidia,adjust-baud-rates =3D <0 9600 100>, + <9600 115200 200>, + <1000000 4000000 136>; + + /* Azurewave AW-NH665 BCM4330B1 */ + bluetooth { + compatible =3D "brcm,bcm4330-bt"; + max-speed =3D <4000000>; + + clocks =3D <&tegra_pmc TEGRA_PMC_CLK_BLINK>; + clock-names =3D "txco"; + + interrupt-parent =3D <&gpio>; + interrupts =3D ; + interrupt-names =3D "host-wakeup"; + + device-wakeup-gpios =3D <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>; + shutdown-gpios =3D <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>; + + vbat-supply =3D <&vdd_3v3_com>; + vddio-supply =3D <&vdd_1v8_vio>; + }; + }; + + pwm@7000a000 { + status =3D "okay"; + }; + + gen1_i2c: i2c@7000c000 { + status =3D "okay"; + clock-frequency =3D <100000>; + + /* Nuvoton NPCE698LA0BX embedded controller */ + }; + + i2c@7000c400 { + status =3D "okay"; + clock-frequency =3D <400000>; + + /* Atmel Maxtouch MXT1664 HID over I2C */ + touchscreen@4b { + compatible =3D "hid-over-i2c"; + reg =3D <0x4b>; + + hid-descr-addr =3D <0x0000>; + + interrupt-parent =3D <&gpio>; + interrupts =3D ; + + vdd-supply =3D <&vdd_3v3_sys>; + vddl-supply =3D <&vdd_1v8_vio>; + }; + }; + + i2c@7000c500 { + status =3D "okay"; + clock-frequency =3D <100000>; + + /* TI TPS61050/61052 Boost Converter */ + flash-led@33 { + compatible =3D "ti,tps61052"; + reg =3D <0x33>; + + led { + color =3D ; + }; + }; + + imu@69 { + compatible =3D "invensense,mpu6050"; + reg =3D <0x69>; + + interrupt-parent =3D <&gpio>; + interrupts =3D ; + + vdd-supply =3D <&vdd_3v3_sys>; + vddio-supply =3D <&vdd_1v8_vio>; + + mount-matrix =3D "0", "-1", "0", + "-1", "0", "0", + "0", "0", "-1"; + + /* External I2C interface */ + i2c-gate { + #address-cells =3D <1>; + #size-cells =3D <0>; + + magnetometer@d { + compatible =3D "asahi-kasei,ak8975"; + reg =3D <0x0d>; + + interrupt-parent =3D <&gpio>; + interrupts =3D ; + + vdd-supply =3D <&vdd_3v3_sys>; + vid-supply =3D <&vdd_1v8_vio>; + + mount-matrix =3D "0", "-1", "0", + "-1", "0", "0", + "0", "0", "-1"; + }; + }; + }; + }; + + hdmi_ddc: i2c@7000c700 { + status =3D "okay"; + clock-frequency =3D <93750>; + }; + + i2c@7000d000 { + status =3D "okay"; + clock-frequency =3D <400000>; + + rt5640: audio-codec@1c { + compatible =3D "realtek,rt5640"; + reg =3D <0x1c>; + + interrupt-parent =3D <&gpio>; + interrupts =3D ; + + clocks =3D <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + clock-names =3D "mclk"; + }; + + /* Texas Instruments TPS659110 PMIC */ + pmic: pmic@2d { + compatible =3D "ti,tps65911"; + reg =3D <0x2d>; + + interrupts =3D ; + #interrupt-cells =3D <2>; + interrupt-controller; + + ti,en-gpio-sleep =3D <0 0 1 0 0 0 0 0 0>; + ti,system-power-controller; + ti,sleep-keep-ck32k; + ti,sleep-enable; + + #gpio-cells =3D <2>; + gpio-controller; + + vcc1-supply =3D <&vdd_5v0_bat>; + vcc2-supply =3D <&vdd_5v0_bat>; + vcc3-supply =3D <&vdd_1v8_vio>; + vcc4-supply =3D <&vdd_5v0_sys>; + vcc5-supply =3D <&vdd_5v0_bat>; + vcc6-supply =3D <&vdd_3v3_sys>; + vcc7-supply =3D <&vdd_5v0_bat>; + vccio-supply =3D <&vdd_5v0_bat>; + + pmic-sleep-hog { + gpio-hog; + gpios =3D <2 GPIO_ACTIVE_HIGH>; + output-high; + }; + + regulators { + vdd_lcd: vdd1 { + regulator-name =3D "vddio_ddr_1v2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-always-on; + regulator-boot-on; + ti,regulator-ext-sleep-control =3D <8>; + }; + + vddio_ddr: vdd2 { + regulator-name =3D "vddio_ddr"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_cpu: vddctrl { + regulator-name =3D "vdd_cpu,vdd_sys"; + regulator-min-microvolt =3D <600000>; + regulator-max-microvolt =3D <1400000>; + regulator-coupled-with =3D <&vdd_core>; + regulator-coupled-max-spread =3D <300000>; + regulator-max-step-microvolt =3D <100000>; + regulator-always-on; + regulator-boot-on; + ti,regulator-ext-sleep-control =3D <1>; + + nvidia,tegra-cpu-regulator; + }; + + vdd_1v8_vio: vio { + regulator-name =3D "vdd_1v8_gen"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + /* eMMC VDD */ + vcore_emmc: ldo1 { + regulator-name =3D "vdd_emmc_core"; + regulator-min-microvolt =3D <1000000>; + regulator-max-microvolt =3D <3300000>; + regulator-always-on; + }; + + /* ldo2 and ldo3 are not used by TF600T */ + + ldo4 { + regulator-name =3D "vdd_rtc"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-always-on; + }; + + /* uSD slot VDDIO */ + vddio_usd: ldo5 { + regulator-name =3D "vddio_sdmmc"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + regulator-always-on; + }; + + avdd_dsi_csi: ldo6 { + regulator-name =3D "avdd_dsi_csi"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + }; + + ldo7 { + regulator-name =3D "vdd_pllm,x,u,a_p_c_s"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-always-on; + regulator-boot-on; + ti,regulator-ext-sleep-control =3D <8>; + }; + + ldo8 { + regulator-name =3D "vdd_ddr_hs"; + regulator-min-microvolt =3D <1000000>; + regulator-max-microvolt =3D <1000000>; + regulator-always-on; + ti,regulator-ext-sleep-control =3D <8>; + }; + }; + }; + + /* Capella CM3218 ambient light sensor */ + light-sensor@48 { + compatible =3D "capella,cm32181"; + reg =3D <0x48>; + + interrupt-parent =3D <&gpio>; + interrupts =3D ; + + vdd-supply =3D <&vdd_3v3_als>; + }; + + nct72: temperature-sensor@4c { + compatible =3D "onnn,nct1008"; + reg =3D <0x4c>; + + interrupt-parent =3D <&gpio>; + interrupts =3D ; + + vcc-supply =3D <&vdd_3v3_sys>; + #thermal-sensor-cells =3D <1>; + }; + + vdd_core: core-regulator@60 { + compatible =3D "ti,tps62361"; + reg =3D <0x60>; + + regulator-name =3D "tps62361-vout"; + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <1770000>; + regulator-coupled-with =3D <&vdd_cpu>; + regulator-coupled-max-spread =3D <300000>; + regulator-max-step-microvolt =3D <100000>; + regulator-boot-on; + regulator-always-on; + ti,enable-vout-discharge; + ti,vsel0-state-high; + ti,vsel1-state-high; + + nvidia,tegra-core-regulator; + }; + }; + + pmc@7000e400 { + status =3D "okay"; + nvidia,invert-interrupt; + nvidia,suspend-mode =3D <2>; + nvidia,cpu-pwr-good-time =3D <2000>; + nvidia,cpu-pwr-off-time =3D <200>; + nvidia,core-pwr-good-time =3D <3845 3845>; + nvidia,core-pwr-off-time =3D <0>; + nvidia,core-power-req-active-high; + nvidia,sys-clock-req-active-high; + core-supply =3D <&vdd_core>; + + i2c-thermtrip { + nvidia,i2c-controller-id =3D <4>; + nvidia,bus-addr =3D <0x2d>; + nvidia,reg-addr =3D <0x3f>; + nvidia,reg-data =3D <0x81>; + }; + }; + + spi@7000da00 { + status =3D "okay"; + spi-max-frequency =3D <25000000>; + + flash@1 { + compatible =3D "winbond,w25q32", "jedec,spi-nor"; + reg =3D <1>; + + spi-max-frequency =3D <20000000>; + vcc-supply =3D <&vdd_3v3_sys>; + }; + }; + + memory-controller@7000f000 { + emc-timings-0 { + /* Elpida 2GB 750 MHZ */ + nvidia,ram-code =3D <0>; + + timing-25500000 { + clock-frequency =3D <25500000>; + + nvidia,emem-configuration =3D < 0x00020001 0xc0000010 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0502 0x75e30303 0x001f0000 >; + }; + + timing-51000000 { + clock-frequency =3D <51000000>; + + nvidia,emem-configuration =3D < 0x00010001 0xc0000010 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0502 0x74e30303 0x001f0000 >; + }; + + timing-102000000 { + clock-frequency =3D <102000000>; + + nvidia,emem-configuration =3D < 0x00000001 0xc0000018 + 0x00000001 0x00000001 0x00000003 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0503 0x74430504 0x001f0000 >; + }; + + timing-204000000 { + clock-frequency =3D <204000000>; + + nvidia,emem-configuration =3D < 0x00000003 0xc0000025 + 0x00000001 0x00000001 0x00000005 0x00000002 + 0x00000003 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0505 0x74040a06 0x001f0000 >; + }; + + timing-375000000 { + clock-frequency =3D <375000000>; + + nvidia,emem-configuration =3D < 0x00000005 0xc0000044 + 0x00000001 0x00000002 0x00000009 0x00000005 + 0x00000005 0x00000001 0x00000002 0x00000008 + 0x00000002 0x00000002 0x00000003 0x00000006 + 0x06030202 0x000d0709 0x7086110a 0x001f0000 >; + }; + + timing-750000000 { + clock-frequency =3D <750000000>; + + nvidia,emem-configuration =3D < 0x0000000b 0xc0000087 + 0x00000004 0x00000005 0x00000012 0x0000000c + 0x0000000b 0x00000002 0x00000003 0x0000000c + 0x00000002 0x00000002 0x00000004 0x00000008 + 0x08040202 0x00160d12 0x710c2213 0x001f0000 >; + }; + }; + + emc-timings-1 { + /* Hynix 2GB 750 MHZ */ + nvidia,ram-code =3D <1>; + + timing-51000000 { + clock-frequency =3D <51000000>; + + nvidia,emem-configuration =3D < 0x00010003 0xc0000010 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0502 0x74630303 0x001f0000 >; + }; + + timing-102000000 { + clock-frequency =3D <102000000>; + + nvidia,emem-configuration =3D < 0x00000003 0xc0000018 + 0x00000001 0x00000001 0x00000003 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0503 0x73c30504 0x001f0000 >; + }; + + timing-204000000 { + clock-frequency =3D <204000000>; + + nvidia,emem-configuration =3D < 0x00000006 0xc0000025 + 0x00000001 0x00000001 0x00000005 0x00000002 + 0x00000003 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0505 0x73840a06 0x001f0000 >; + }; + + timing-375000000 { + clock-frequency =3D <375000000>; + + nvidia,emem-configuration =3D < 0x0000000b 0xc0000044 + 0x00000001 0x00000002 0x00000009 0x00000005 + 0x00000005 0x00000001 0x00000002 0x00000008 + 0x00000002 0x00000002 0x00000003 0x00000006 + 0x06030202 0x000c0609 0x7086110a 0x001f0000 >; + }; + + timing-750000000 { + clock-frequency =3D <750000000>; + + nvidia,emem-configuration =3D < 0x00000016 0xc0000087 + 0x00000003 0x00000004 0x00000012 0x0000000c + 0x0000000b 0x00000002 0x00000003 0x0000000c + 0x00000002 0x00000002 0x00000004 0x00000008 + 0x08040202 0x00150c12 0x710c2213 0x001f0000 >; + }; + }; + + emc-timings-2 { + /* Micron 2GB 750 MHZ */ + nvidia,ram-code =3D <2>; + + timing-51000000 { + clock-frequency =3D <51000000>; + + nvidia,emem-configuration =3D < 0x00010003 0xc0000010 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0502 0x73430303 0x001f0000 >; + }; + + timing-102000000 { + clock-frequency =3D <102000000>; + + nvidia,emem-configuration =3D < 0x00000003 0xc0000018 + 0x00000001 0x00000001 0x00000003 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0503 0x74430504 0x001f0000 >; + }; + + timing-204000000 { + clock-frequency =3D <204000000>; + + nvidia,emem-configuration =3D < 0x00000006 0xc0000025 + 0x00000001 0x00000001 0x00000005 0x00000002 + 0x00000003 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0505 0x74040a06 0x001f0000 >; + }; + + timing-375000000 { + clock-frequency =3D <375000000>; + + nvidia,emem-configuration =3D < 0x0000000b 0xc0000044 + 0x00000001 0x00000002 0x00000009 0x00000005 + 0x00000005 0x00000001 0x00000002 0x00000008 + 0x00000002 0x00000002 0x00000003 0x00000006 + 0x06030202 0x000d0709 0x7086110a 0x001f0000 >; + }; + + timing-750000000 { + clock-frequency =3D <750000000>; + + nvidia,emem-configuration =3D < 0x00000016 0xc0000087 + 0x00000004 0x00000005 0x00000012 0x0000000c + 0x0000000b 0x00000003 0x00000003 0x0000000c + 0x00000002 0x00000002 0x00000004 0x00000008 + 0x08040202 0x00160d12 0x710c2213 0x001f0000 >; + }; + }; + }; + + memory-controller@7000f400 { + emc-timings-0 { + /* Elpida 2GB 750 MHZ */ + nvidia,ram-code =3D <0>; + + timing-25500000 { + clock-frequency =3D <25500000>; + + nvidia,emc-auto-cal-interval =3D <0x001fffff>; + nvidia,emc-mode-1 =3D <0x80100003>; + nvidia,emc-mode-2 =3D <0x80200048>; + nvidia,emc-mode-reset =3D <0x80001221>; + nvidia,emc-zcal-cnt-long =3D <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + + nvidia,emc-configuration =3D < 0x00000001 + 0x00000007 0x00000000 0x00000000 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000000 + 0x00000000 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x000000c0 0x00000000 0x00000030 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000008 0x00000008 + 0x00000004 0x00000001 0x00000000 0x00000004 + 0x00000005 0x000000c7 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000287 0xe8000000 0xff00ff00 >; + }; + + timing-51000000 { + clock-frequency =3D <51000000>; + + nvidia,emc-auto-cal-interval =3D <0x001fffff>; + nvidia,emc-mode-1 =3D <0x80100003>; + nvidia,emc-mode-2 =3D <0x80200048>; + nvidia,emc-mode-reset =3D <0x80001221>; + nvidia,emc-zcal-cnt-long =3D <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + + nvidia,emc-configuration =3D < 0x00000002 + 0x0000000f 0x00000001 0x00000000 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000000 + 0x00000000 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x00000181 0x00000000 0x00000060 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000010 0x00000010 + 0x00000004 0x00000002 0x00000000 0x00000004 + 0x00000005 0x0000018e 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x8000040b 0xe8000000 0xff00ff00 >; + }; + + timing-102000000 { + clock-frequency =3D <102000000>; + + nvidia,emc-auto-cal-interval =3D <0x001fffff>; + nvidia,emc-mode-1 =3D <0x80100003>; + nvidia,emc-mode-2 =3D <0x80200048>; + nvidia,emc-mode-reset =3D <0x80001221>; + nvidia,emc-zcal-cnt-long =3D <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + + nvidia,emc-configuration =3D < 0x00000004 + 0x0000001e 0x00000003 0x00000001 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000001 + 0x00000001 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x00000303 0x00000000 0x000000c0 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000020 0x00000020 + 0x00000004 0x00000004 0x00000000 0x00000004 + 0x00000005 0x0000031c 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000713 0xe8000000 0xff00ff00 >; + }; + + timing-204000000 { + clock-frequency =3D <204000000>; + + nvidia,emc-auto-cal-interval =3D <0x001fffff>; + nvidia,emc-mode-1 =3D <0x80100003>; + nvidia,emc-mode-2 =3D <0x80200048>; + nvidia,emc-mode-reset =3D <0x80001221>; + nvidia,emc-zcal-cnt-long =3D <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + + nvidia,emc-configuration =3D < 0x00000009 + 0x0000003d 0x00000007 0x00000002 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000002 + 0x00000002 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000006 0x00000004 0x0000000a + 0x0000000b 0x00000607 0x00000000 0x00000181 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000040 0x00000040 + 0x00000004 0x00000007 0x00000000 0x00000004 + 0x00000005 0x00000638 0x00000007 0x00000004 + 0x00000000 0x00000000 0x00004288 0x004400a4 + 0x00008000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00020000 + 0x00000100 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000d22 0xe8000000 0xff00ff00 >; + }; + + timing-375000000 { + clock-frequency =3D <375000000>; + + nvidia,emc-auto-cal-interval =3D <0x001fffff>; + nvidia,emc-mode-1 =3D <0x80100002>; + nvidia,emc-mode-2 =3D <0x80200040>; + nvidia,emc-mode-reset =3D <0x80000521>; + nvidia,emc-zcal-cnt-long =3D <0x00000040>; + + nvidia,emc-configuration =3D < 0x00000011 + 0x0000006f 0x0000000c 0x00000004 0x00000003 + 0x00000008 0x00000002 0x0000000a 0x00000004 + 0x00000004 0x00000002 0x00000001 0x00000000 + 0x00000004 0x00000006 0x00000004 0x0000000a + 0x0000000c 0x00000b2d 0x00000000 0x000002cb + 0x00000001 0x00000008 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000075 0x00000200 + 0x00000004 0x0000000c 0x00000000 0x00000004 + 0x00000005 0x00000b6d 0x00000000 0x00000004 + 0x00000000 0x00000000 0x00007088 0x00200084 + 0x00008000 0x00034000 0x00034000 0x00034000 + 0x00034000 0x00014000 0x00014000 0x00014000 + 0x00014000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00048000 0x00048000 0x00048000 + 0x00048000 0x000002a0 0x0600013d 0x00000000 + 0x77fff884 0x01f1f508 0x05057404 0x54000007 + 0x080001e8 0x06000021 0x00000802 0x00020000 + 0x00000100 0x0150000c 0xa0f10000 0x00000000 + 0x00000000 0x8000174b 0xe8000000 0xff00ff89 >; + }; + + timing-750000000 { + clock-frequency =3D <750000000>; + + nvidia,emc-auto-cal-interval =3D <0x001fffff>; + nvidia,emc-mode-1 =3D <0x80100002>; + nvidia,emc-mode-2 =3D <0x80200058>; + nvidia,emc-mode-reset =3D <0x80000d71>; + nvidia,emc-zcal-cnt-long =3D <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration =3D < 0x00000023 + 0x000000df 0x00000019 0x00000009 0x00000005 + 0x0000000d 0x00000004 0x00000013 0x00000009 + 0x00000009 0x00000003 0x00000001 0x00000000 + 0x00000007 0x0000000b 0x00000009 0x0000000b + 0x00000011 0x0000169a 0x00000000 0x000005a6 + 0x00000003 0x00000010 0x00000001 0x00000000 + 0x0000000e 0x00000018 0x000000e9 0x00000200 + 0x00000005 0x00000017 0x00000000 0x00000007 + 0x00000008 0x000016da 0x0000000c 0x00000004 + 0x00000000 0x00000000 0x00005088 0xf0080191 + 0x00008000 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x00000008 0x00000008 0x00000008 + 0x00000008 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x000002a0 0x0600013d 0x22220000 + 0x77fff884 0x01f1f501 0x07077404 0x54000000 + 0x080001e8 0x06000021 0x00000802 0x00020000 + 0x00000100 0x00df000c 0xa0f10000 0x00000000 + 0x00000000 0x80002d93 0xf8000000 0xff00ff49 >; + }; + }; + + emc-timings-1 { + /* Hynix 2GB 750 MHZ */ + nvidia,ram-code =3D <1>; + + timing-51000000 { + clock-frequency =3D <51000000>; + + nvidia,emc-auto-cal-interval =3D <0x001fffff>; + nvidia,emc-mode-1 =3D <0x80100003>; + nvidia,emc-mode-2 =3D <0x80200048>; + nvidia,emc-mode-reset =3D <0x80001221>; + nvidia,emc-zcal-cnt-long =3D <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + + nvidia,emc-configuration =3D < 0x00000002 + 0x0000000d 0x00000001 0x00000000 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000000 + 0x00000000 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x00000181 0x00000000 0x00000060 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x0000000e 0x0000000e + 0x00000004 0x00000002 0x00000000 0x00000004 + 0x00000005 0x0000018e 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x8000040b 0xe8000000 0xff00ff00 >; + }; + + timing-102000000 { + clock-frequency =3D <102000000>; + + nvidia,emc-auto-cal-interval =3D <0x001fffff>; + nvidia,emc-mode-1 =3D <0x80100003>; + nvidia,emc-mode-2 =3D <0x80200048>; + nvidia,emc-mode-reset =3D <0x80001221>; + nvidia,emc-zcal-cnt-long =3D <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + + nvidia,emc-configuration =3D < 0x00000004 + 0x0000001a 0x00000003 0x00000001 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000001 + 0x00000001 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x00000303 0x00000000 0x000000c0 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x0000001c 0x0000001c + 0x00000004 0x00000004 0x00000000 0x00000004 + 0x00000005 0x0000031c 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000713 0xe8000000 0xff00ff00 >; + }; + + timing-204000000 { + clock-frequency =3D <204000000>; + + nvidia,emc-auto-cal-interval =3D <0x001fffff>; + nvidia,emc-mode-1 =3D <0x80100003>; + nvidia,emc-mode-2 =3D <0x80200048>; + nvidia,emc-mode-reset =3D <0x80001221>; + nvidia,emc-zcal-cnt-long =3D <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + + nvidia,emc-configuration =3D < 0x00000009 + 0x00000035 0x00000007 0x00000002 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000002 + 0x00000002 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000006 0x00000004 0x0000000a + 0x0000000b 0x00000607 0x00000000 0x00000181 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000038 0x00000038 + 0x00000004 0x00000007 0x00000000 0x00000004 + 0x00000005 0x00000638 0x00000007 0x00000004 + 0x00000000 0x00000000 0x00004288 0x004400a4 + 0x00008000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00020000 + 0x00000100 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000d22 0xe8000000 0xff00ff00 >; + }; + + timing-375000000 { + clock-frequency =3D <375000000>; + + nvidia,emc-auto-cal-interval =3D <0x001fffff>; + nvidia,emc-mode-1 =3D <0x80100003>; + nvidia,emc-mode-2 =3D <0x80200040>; + nvidia,emc-mode-reset =3D <0x80000521>; + nvidia,emc-zcal-cnt-long =3D <0x00000040>; + + nvidia,emc-configuration =3D < 0x00000011 + 0x00000060 0x0000000c 0x00000003 0x00000004 + 0x00000008 0x00000002 0x0000000a 0x00000003 + 0x00000003 0x00000002 0x00000001 0x00000000 + 0x00000004 0x00000006 0x00000004 0x0000000a + 0x0000000c 0x00000b2d 0x00000000 0x000002cb + 0x00000001 0x00000008 0x00000001 0x00000000 + 0x00000007 0x00000010 0x00000066 0x00000200 + 0x00000004 0x0000000c 0x00000000 0x00000004 + 0x00000005 0x00000b6d 0x00000000 0x00000004 + 0x00000000 0x00000000 0x00007288 0x00200084 + 0x00008000 0x00044000 0x00044000 0x00044000 + 0x00044000 0x00014000 0x00014000 0x00014000 + 0x00014000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00048000 0x00048000 0x00048000 + 0x00048000 0x000002a0 0x0600013d 0x00000000 + 0x77fff884 0x01f1f508 0x05057404 0x54000007 + 0x08000168 0x06000021 0x00000802 0x00020000 + 0x00000100 0x015f000c 0xa0f10000 0x00000000 + 0x00000000 0x8000174b 0xe8000000 0xff00ff89 >; + }; + + timing-750000000 { + clock-frequency =3D <750000000>; + + nvidia,emc-auto-cal-interval =3D <0x001fffff>; + nvidia,emc-mode-1 =3D <0x80100002>; + nvidia,emc-mode-2 =3D <0x80200058>; + nvidia,emc-mode-reset =3D <0x80000d71>; + nvidia,emc-zcal-cnt-long =3D <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration =3D < 0x00000023 + 0x000000c1 0x00000019 0x00000008 0x00000005 + 0x0000000d 0x00000004 0x00000013 0x00000008 + 0x00000008 0x00000003 0x00000001 0x00000000 + 0x00000007 0x0000000b 0x00000009 0x0000000b + 0x00000011 0x0000169a 0x00000000 0x000005a6 + 0x00000003 0x00000010 0x00000001 0x00000000 + 0x0000000e 0x00000018 0x000000cb 0x00000200 + 0x00000005 0x00000017 0x00000000 0x00000007 + 0x00000008 0x000016da 0x0000000c 0x00000004 + 0x00000000 0x00000000 0x00005088 0xf0080191 + 0x00008000 0x00008008 0x00000008 0x00000008 + 0x00000008 0x00000008 0x00000008 0x00000008 + 0x00000008 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x000002a0 0x0800013d 0x22220000 + 0x77fff884 0x01f1f501 0x07077404 0x54000000 + 0x080001e8 0x08000021 0x00000802 0x00020000 + 0x00000100 0x00fd000c 0xa0f10000 0x00000000 + 0x00000000 0x80002d93 0xe8000000 0xff00ff49 >; + }; + }; + + emc-timings-2 { + /* Micron 2GB 750 MHZ */ + nvidia,ram-code =3D <2>; + + timing-51000000 { + clock-frequency =3D <51000000>; + + nvidia,emc-auto-cal-interval =3D <0x001fffff>; + nvidia,emc-mode-1 =3D <0x80100003>; + nvidia,emc-mode-2 =3D <0x80200008>; + nvidia,emc-mode-reset =3D <0x80001221>; + nvidia,emc-zcal-cnt-long =3D <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + + nvidia,emc-configuration =3D < 0x00000002 + 0x00000008 0x00000001 0x00000000 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000000 + 0x00000000 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x00000181 0x00000000 0x00000060 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000009 0x00000009 + 0x00000004 0x00000002 0x00000000 0x00000004 + 0x00000005 0x0000018e 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x8000040b 0xe8000000 0xff00ff00 >; + }; + + timing-102000000 { + clock-frequency =3D <102000000>; + + nvidia,emc-auto-cal-interval =3D <0x001fffff>; + nvidia,emc-mode-1 =3D <0x80100003>; + nvidia,emc-mode-2 =3D <0x80200048>; + nvidia,emc-mode-reset =3D <0x80001221>; + nvidia,emc-zcal-cnt-long =3D <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + + nvidia,emc-configuration =3D < 0x00000004 + 0x0000001e 0x00000003 0x00000001 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000001 + 0x00000001 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x00000303 0x00000000 0x000000c0 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000020 0x00000020 + 0x00000004 0x00000004 0x00000000 0x00000004 + 0x00000005 0x0000031c 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000713 0xe8000000 0xff00ff00 >; + }; + + timing-204000000 { + clock-frequency =3D <204000000>; + + nvidia,emc-auto-cal-interval =3D <0x001fffff>; + nvidia,emc-mode-1 =3D <0x80100003>; + nvidia,emc-mode-2 =3D <0x80200048>; + nvidia,emc-mode-reset =3D <0x80001221>; + nvidia,emc-zcal-cnt-long =3D <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + + nvidia,emc-configuration =3D < 0x00000009 + 0x0000003d 0x00000007 0x00000002 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000002 + 0x00000002 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000006 0x00000004 0x0000000a + 0x0000000b 0x00000607 0x00000000 0x00000181 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000040 0x00000040 + 0x00000004 0x00000007 0x00000000 0x00000004 + 0x00000005 0x00000638 0x00000007 0x00000004 + 0x00000000 0x00000000 0x00004288 0x004400a4 + 0x00008000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00020000 + 0x00000100 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000d22 0xe8000000 0xff00ff00 >; + }; + + timing-375000000 { + clock-frequency =3D <375000000>; + + nvidia,emc-auto-cal-interval =3D <0x001fffff>; + nvidia,emc-mode-1 =3D <0x80100002>; + nvidia,emc-mode-2 =3D <0x80200040>; + nvidia,emc-mode-reset =3D <0x80000521>; + nvidia,emc-zcal-cnt-long =3D <0x00000040>; + + nvidia,emc-configuration =3D < 0x00000011 + 0x0000006f 0x0000000c 0x00000004 0x00000003 + 0x00000008 0x00000002 0x0000000a 0x00000004 + 0x00000004 0x00000002 0x00000001 0x00000000 + 0x00000004 0x00000006 0x00000004 0x0000000a + 0x0000000c 0x00000b2d 0x00000000 0x000002cb + 0x00000001 0x00000008 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000075 0x00000200 + 0x00000004 0x0000000c 0x00000000 0x00000004 + 0x00000005 0x00000b6d 0x00000000 0x00000004 + 0x00000000 0x00000000 0x00007088 0x00200084 + 0x00008000 0x00044000 0x00044000 0x00044000 + 0x00044000 0x00014000 0x00014000 0x00014000 + 0x00014000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00048000 0x00048000 0x00048000 + 0x00048000 0x000002a0 0x0800013d 0x00000000 + 0x77fff884 0x01f1f508 0x05057404 0x54000007 + 0x080001e8 0x08000021 0x00000802 0x00020000 + 0x00000100 0x0150000c 0xa0f10000 0x00000000 + 0x00000000 0x8000174b 0xe8000000 0xff00ff89 >; + }; + + timing-750000000 { + clock-frequency =3D <750000000>; + + nvidia,emc-auto-cal-interval =3D <0x001fffff>; + nvidia,emc-mode-1 =3D <0x80100002>; + nvidia,emc-mode-2 =3D <0x80200058>; + nvidia,emc-mode-reset =3D <0x80000d71>; + nvidia,emc-zcal-cnt-long =3D <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration =3D < 0x00000023 + 0x000000df 0x00000019 0x00000009 0x00000005 + 0x0000000d 0x00000004 0x00000013 0x00000009 + 0x00000009 0x00000006 0x00000001 0x00000000 + 0x00000007 0x0000000b 0x00000009 0x0000000b + 0x00000011 0x0000169a 0x00000000 0x000005a6 + 0x00000003 0x00000010 0x00000001 0x00000000 + 0x0000000e 0x00000018 0x000000e9 0x00000200 + 0x00000005 0x00000017 0x00000000 0x00000007 + 0x00000008 0x000016da 0x0000000c 0x00000004 + 0x00000000 0x00000000 0x00005088 0xf0080191 + 0x00008000 0x0000800a 0x0000000a 0x0000000a + 0x0000000a 0x00000008 0x00000008 0x00000008 + 0x00000008 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x007fc00a 0x0000000a 0x0000000a + 0x0000000a 0x000002a0 0x0800013d 0x22220000 + 0x77fff884 0x01f1f501 0x07077404 0x54000000 + 0x080001e8 0x08000021 0x00000802 0x00020000 + 0x00000100 0x00df000c 0xa0f10000 0x00000000 + 0x00000000 0x80002d93 0xf8000000 0xff00ff49 >; + }; + }; + }; + + hda@70030000 { + status =3D "okay"; + }; + + ahub@70080000 { + i2s@70080400 { /* i2s1 */ + status =3D "okay"; + }; + + /* BT SCO */ + i2s@70080600 { /* i2s3 */ + status =3D "okay"; + }; + }; + + sdmmc1: mmc@78000000 { + status =3D "okay"; + bus-width =3D <4>; + + cd-gpios =3D <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; + power-gpios =3D <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>; + + vmmc-supply =3D <&vdd_3v3_sys>; + vqmmc-supply =3D <&vddio_usd>; + }; + + sdmmc3: mmc@78000400 { + status =3D "okay"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + assigned-clocks =3D <&tegra_car TEGRA30_CLK_SDMMC3>; + assigned-clock-parents =3D <&tegra_car TEGRA30_CLK_PLL_C>; + assigned-clock-rates =3D <50000000>; + + max-frequency =3D <50000000>; + keep-power-in-suspend; + bus-width =3D <4>; + non-removable; + + mmc-pwrseq =3D <&brcm_wifi_pwrseq>; + vmmc-supply =3D <&vdd_3v3_com>; + vqmmc-supply =3D <&vdd_1v8_vio>; + + /* Azurewave AW-NH665 BCM4330B1 */ + wifi@1 { + compatible =3D "brcm,bcm4329-fmac"; + reg =3D <1>; + + interrupt-parent =3D <&gpio>; + interrupts =3D ; + interrupt-names =3D "host-wake"; + }; + }; + + sdmmc4: mmc@78000600 { + status =3D "okay"; + bus-width =3D <8>; + + non-removable; + mmc-ddr-1_8v; + + vmmc-supply =3D <&vcore_emmc>; + vqmmc-supply =3D <&vdd_1v8_vio>; + }; + + /* USB via ASUS connector */ + usb@7d000000 { + compatible =3D "nvidia,tegra30-udc"; + status =3D "okay"; + dr_mode =3D "peripheral"; + }; + + usb-phy@7d000000 { + status =3D "okay"; + dr_mode =3D "peripheral"; + nvidia,hssync-start-delay =3D <0>; + nvidia,xcvr-lsfslew =3D <2>; + nvidia,xcvr-lsrslew =3D <2>; + vbus-supply =3D <&vdd_5v0_sys>; + }; + + /* Dock's USB port */ + usb@7d008000 { + status =3D "okay"; + }; + + usb-phy@7d008000 { + status =3D "okay"; + vbus-supply =3D <&vdd_5v0_bat>; + }; + + backlight: backlight { + compatible =3D "pwm-backlight"; + + enable-gpios =3D <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; + power-supply =3D <&vdd_5v0_bl>; + pwms =3D <&pwm 0 71428>; + + brightness-levels =3D <1 255>; + num-interpolated-steps =3D <254>; + default-brightness-level =3D <15>; + }; + + pad_battery: battery-pad { + compatible =3D "simple-battery"; + device-chemistry =3D "lithium-ion-polymer"; + charge-full-design-microamp-hours =3D <6760000>; + energy-full-design-microwatt-hours =3D <25000000>; + operating-range-celsius =3D <0 45>; + }; + + dock_battery: battery-dock { + compatible =3D "simple-battery"; + device-chemistry =3D "lithium-ion-polymer"; + charge-full-design-microamp-hours =3D <2980000>; + energy-full-design-microwatt-hours =3D <22000000>; + operating-range-celsius =3D <0 45>; + }; + + /* PMIC has a built-in 32KHz oscillator which is used by PMC */ + clk32k_in: clock-32k { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <32768>; + clock-output-names =3D "pmic-oscillator"; + }; + + cpus { + cpu0: cpu@0 { + cpu-supply =3D <&vdd_cpu>; + operating-points-v2 =3D <&cpu0_opp_table>; + #cooling-cells =3D <2>; + }; + cpu1: cpu@1 { + cpu-supply =3D <&vdd_cpu>; + operating-points-v2 =3D <&cpu0_opp_table>; + #cooling-cells =3D <2>; + }; + cpu2: cpu@2 { + cpu-supply =3D <&vdd_cpu>; + operating-points-v2 =3D <&cpu0_opp_table>; + #cooling-cells =3D <2>; + }; + cpu3: cpu@3 { + cpu-supply =3D <&vdd_cpu>; + operating-points-v2 =3D <&cpu0_opp_table>; + #cooling-cells =3D <2>; + }; + }; + + extcon-keys { + compatible =3D "gpio-keys"; + + switch-dock-hall-sensor { + label =3D "Lid sensor"; + gpios =3D <&gpio TEGRA_GPIO(BB, 6) GPIO_ACTIVE_LOW>; + linux,input-type =3D ; + linux,code =3D ; + debounce-interval =3D <500>; + wakeup-event-action =3D ; + wakeup-source; + }; + + switch-lineout-detect { + label =3D "Audio dock line-out detect"; + gpios =3D <&gpio TEGRA_GPIO(X, 3) GPIO_ACTIVE_LOW>; + linux,input-type =3D ; + linux,code =3D ; + debounce-interval =3D <10>; + wakeup-event-action =3D ; + wakeup-source; + }; + }; + + gpio-keys { + compatible =3D "gpio-keys"; + + key-power { + label =3D "Power"; + gpios =3D <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; + linux,code =3D ; + debounce-interval =3D <10>; + wakeup-event-action =3D ; + wakeup-source; + }; + + key-volume-down { + label =3D "Volume Down"; + gpios =3D <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; + linux,code =3D ; + debounce-interval =3D <10>; + wakeup-event-action =3D ; + wakeup-source; + }; + + key-volume-up { + label =3D "Volume Up"; + gpios =3D <&gpio TEGRA_GPIO(Q, 3) GPIO_ACTIVE_LOW>; + linux,code =3D ; + debounce-interval =3D <10>; + wakeup-event-action =3D ; + wakeup-source; + }; + }; + + haptic-feedback { + compatible =3D "gpio-vibrator"; + enable-gpios =3D <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>; + vcc-supply =3D <&vdd_3v3_sys>; + }; + + opp-table-actmon { + /delete-node/ opp-800000000; + /delete-node/ opp-900000000; + }; + + opp-table-emc { + /delete-node/ opp-800000000-1300; + /delete-node/ opp-900000000-1350; + }; + + brcm_wifi_pwrseq: pwrseq-wifi { + compatible =3D "mmc-pwrseq-simple"; + + clocks =3D <&tegra_pmc TEGRA_PMC_CLK_BLINK>; + clock-names =3D "ext_clock"; + + reset-gpios =3D <&gpio TEGRA_GPIO(P, 1) GPIO_ACTIVE_LOW>; + post-power-on-delay-ms =3D <300>; + power-off-delay-us =3D <300>; + }; + + vdd_5v0_bat: regulator-bat { + compatible =3D "regulator-fixed"; + regulator-name =3D "vdd_ac_bat"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_5v0_cp: regulator-sby { + compatible =3D "regulator-fixed"; + regulator-name =3D "vdd_5v0_sby"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + regulator-always-on; + regulator-boot-on; + gpio =3D <&pmic 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply =3D <&vdd_5v0_bat>; + }; + + vdd_5v0_sys: regulator-5v { + compatible =3D "regulator-fixed"; + regulator-name =3D "vdd_5v0_sys"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + regulator-always-on; + regulator-boot-on; + gpio =3D <&pmic 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply =3D <&vdd_5v0_bat>; + }; + + vdd_1v5_ddr: regulator-ddr { + compatible =3D "regulator-fixed"; + regulator-name =3D "vdd_ddr"; + regulator-min-microvolt =3D <1500000>; + regulator-max-microvolt =3D <1500000>; + regulator-always-on; + regulator-boot-on; + gpio =3D <&pmic 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply =3D <&vdd_5v0_bat>; + }; + + vdd_3v3_sys: regulator-3v { + compatible =3D "regulator-fixed"; + regulator-name =3D "vdd_3v3_sys"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-always-on; + regulator-boot-on; + gpio =3D <&pmic 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply =3D <&vdd_5v0_bat>; + }; + + vdd_3v3_com: regulator-com { + compatible =3D "regulator-fixed"; + regulator-name =3D "vdd_3v3_com"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-always-on; + gpio =3D <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply =3D <&vdd_3v3_sys>; + }; + + vdd_3v3_als: regulator-als { + compatible =3D "regulator-fixed"; + regulator-name =3D "vdd_3v3_als"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-always-on; + gpio =3D <&gpio TEGRA_GPIO(L, 5) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply =3D <&vdd_3v3_sys>; + }; + + vdd_5v0_bl: regulator-bl { + compatible =3D "regulator-fixed"; + regulator-name =3D "vdd_5v0_bl"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + regulator-boot-on; + gpio =3D <&gpio TEGRA_GPIO(H, 0) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply =3D <&vdd_5v0_bat>; + }; + + hdmi_5v0_sys: regulator-hdmi { + compatible =3D "regulator-fixed"; + regulator-name =3D "hdmi_5v0_sys"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + gpio =3D <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply =3D <&vdd_5v0_sys>; + }; + + sound { + compatible =3D "asus,tegra-audio-rt5640-tf600t", + "nvidia,tegra-audio-rt5640"; + nvidia,model =3D "Asus VivoTab RT TF600T RT5640"; + + nvidia,audio-routing =3D + "Headphones", "HPOR", + "Headphones", "HPOL", + "Speakers", "SPORP", + "Speakers", "SPORN", + "Speakers", "SPOLP", + "Speakers", "SPOLN", + "DMIC1", "Mic Jack"; + + nvidia,i2s-controller =3D <&tegra_i2s1>; + nvidia,audio-codec =3D <&rt5640>; + + nvidia,hp-det-gpios =3D <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; + nvidia,mic-det-gpios =3D <&gpio TEGRA_GPIO(X, 2) GPIO_ACTIVE_LOW>; + nvidia,coupled-mic-hp-det; + + clocks =3D <&tegra_car TEGRA30_CLK_PLL_A>, + <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + clock-names =3D "pll_a", "pll_a_out0", "mclk"; + + assigned-clocks =3D <&tegra_car TEGRA30_CLK_EXTERN1>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + + assigned-clock-parents =3D <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA30_CLK_EXTERN1>; + }; + + thermal-zones { + /* + * NCT72 has two sensors: + * + * 0: internal that monitors ambient/skin temperature + * 1: external that is connected to the CPU's diode + * + * Ideally we should use userspace thermal governor, + * but it's a much more complex solution. The "skin" + * zone exists as a simpler solution which prevents + * Transformers from getting too hot from a user's + * tactile perspective. The CPU zone is intended to + * protect silicon from damage. + */ + + skin-thermal { + polling-delay-passive =3D <1000>; /* milliseconds */ + polling-delay =3D <5000>; /* milliseconds */ + + thermal-sensors =3D <&nct72 0>; + + trips { + trip0: skin-alert { + /* throttle at 57C until temperature drops to 56.8C */ + temperature =3D <57000>; + hysteresis =3D <200>; + type =3D "passive"; + }; + + trip1: skin-crit { + /* shut down at 65C */ + temperature =3D <65000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&trip0>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&actmon THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu-thermal { + polling-delay-passive =3D <1000>; /* milliseconds */ + polling-delay =3D <5000>; /* milliseconds */ + + thermal-sensors =3D <&nct72 1>; + + trips { + trip2: cpu-alert { + /* throttle at 75C until temperature drops to 74.8C */ + temperature =3D <75000>; + hysteresis =3D <200>; + type =3D "passive"; + }; + + trip3: cpu-crit { + /* shut down at 90C */ + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + + cooling-maps { + map1 { + trip =3D <&trip2>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&actmon THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + }; +}; --=20 2.48.1