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charset="utf-8" The gcc_aux_clk is required by the PCIe controller but not by the PCIe PHY. In PCIe PHY, the source of aux_clk used in low-power mode should be gcc_phy_aux_clk. Hence, remove gcc_aux_clk and replace it with gcc_phy_aux_clk. Signed-off-by: Ziyue Zhang --- .../devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-p= hy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.= yaml index 2c6c9296e4c0..17fd6547d3b4 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml @@ -176,6 +176,8 @@ allOf: contains: enum: - qcom,qcs615-qmp-gen3x1-pcie-phy + - qcom,sa8775p-qmp-gen4x2-pcie-phy + - qcom,sa8775p-qmp-gen4x4-pcie-phy - qcom,sc8280xp-qmp-gen3x1-pcie-phy - qcom,sc8280xp-qmp-gen3x2-pcie-phy - qcom,sc8280xp-qmp-gen3x4-pcie-phy @@ -197,8 +199,6 @@ allOf: contains: enum: - qcom,qcs8300-qmp-gen4x2-pcie-phy - - qcom,sa8775p-qmp-gen4x2-pcie-phy - - qcom,sa8775p-qmp-gen4x4-pcie-phy then: properties: clocks: --=20 2.34.1 From nobody Thu Oct 9 16:43:22 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AB447205502; 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charset="utf-8" Each PCIe controller on sa8775p includes 'link_down'reset on hardware, document it. Signed-off-by: Ziyue Zhang --- .../devicetree/bindings/pci/qcom,pcie-sa8775p.yaml | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml b= /Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml index e3fa232da2ca..b7cae2e556e3 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml @@ -61,11 +61,14 @@ properties: - const: global =20 resets: - maxItems: 1 + items: + - description: PCIe controller reset + - description: link_down reset =20 reset-names: items: - - const: pci + - const: pci # PCIe core reset + - const: link_down # PCIe link down reset =20 required: - interconnects @@ -161,8 +164,10 @@ examples: =20 power-domains =3D <&gcc PCIE_0_GDSC>; =20 - resets =3D <&gcc GCC_PCIE_0_BCR>; - reset-names =3D "pci"; + resets =3D <&gcc GCC_PCIE_0_BCR>, + <&gcc GCC_PCIE_0_LINK_DOWN_BCR>; + reset-names =3D "pci", + "link_down"; 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charset="utf-8" gcc_aux_clk is used in PCIe RC and it is not required in pcie phy, in pcie phy it should be gcc_phy_aux_clk, so remove gcc_aux_clk and replace it with gcc_phy_aux_clk. Signed-off-by: Ziyue Zhang --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 28 +++++++++++++++------------ 1 file changed, 16 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qc= om/sa8775p.dtsi index 45f536633f64..d7248014368b 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -7224,16 +7224,18 @@ pcie0_phy: phy@1c04000 { compatible =3D "qcom,sa8775p-qmp-gen4x2-pcie-phy"; reg =3D <0x0 0x1c04000 0x0 0x2000>; =20 - clocks =3D <&gcc GCC_PCIE_0_AUX_CLK>, + clocks =3D <&gcc GCC_PCIE_0_PHY_AUX_CLK>, <&gcc GCC_PCIE_0_CFG_AHB_CLK>, <&gcc GCC_PCIE_CLKREF_EN>, <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, <&gcc GCC_PCIE_0_PIPE_CLK>, - <&gcc GCC_PCIE_0_PIPEDIV2_CLK>, - <&gcc GCC_PCIE_0_PHY_AUX_CLK>; - - clock-names =3D "aux", "cfg_ahb", "ref", "rchng", "pipe", - "pipediv2", "phy_aux"; + <&gcc GCC_PCIE_0_PIPEDIV2_CLK>; + clock-names =3D "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe", + "pipediv2"; =20 assigned-clocks =3D <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 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Tue, 17 Jun 2025 02:16:31 +0000 (GMT) Received: from pps.filterd (APTAIPPMTA01.qualcomm.com [127.0.0.1]) by APTAIPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTP id 55H2GTIS014424; Tue, 17 Jun 2025 02:16:29 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APTAIPPMTA01.qualcomm.com (PPS) with ESMTPS id 479jt4gb0f-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 17 Jun 2025 02:16:29 +0000 Received: from APTAIPPMTA01.qualcomm.com (APTAIPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 55H2GSxY014406; Tue, 17 Jun 2025 02:16:28 GMT Received: from cse-cd02-lnx.ap.qualcomm.com (cse-cd02-lnx.qualcomm.com [10.64.75.246]) by APTAIPPMTA01.qualcomm.com (PPS) with ESMTPS id 55H2GSgK014398 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 17 Jun 2025 02:16:28 +0000 Received: by cse-cd02-lnx.ap.qualcomm.com (Postfix, from userid 4438065) id D86B2365F; Tue, 17 Jun 2025 10:16:26 +0800 (CST) From: Ziyue Zhang To: andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, jingoohan1@gmail.com, mani@kernel.org, lpieralisi@kernel.org, kwilczynski@kernel.org, bhelgaas@google.com, johan+linaro@kernel.org, vkoul@kernel.org, kishon@kernel.org, neil.armstrong@linaro.org, abel.vesa@linaro.org, kw@linux.com Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-phy@lists.infradead.org, qiang.yu@oss.qualcomm.com, quic_krichai@quicinc.com, quic_vbadigan@quicinc.com, Ziyue Zhang , Konrad Dybcio Subject: [PATCH v2 4/4] arm64: dts: qcom: sa8775p: add link_down reset for pcie Date: Tue, 17 Jun 2025 10:16:17 +0800 Message-Id: <20250617021617.2793902-5-quic_ziyuzhan@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250617021617.2793902-1-quic_ziyuzhan@quicinc.com> References: <20250617021617.2793902-1-quic_ziyuzhan@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 55xi-o5Q5aD3wGlIU2KhuoyFd0gCW1HS X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNjE3MDAxOSBTYWx0ZWRfX6iV6m1gPECdG tWaEfsT5BeTDowgTlMYUpZUGMk/onRB8RcD9jiICzv4+BFn5QFo0qusALwSxVU/h8NxtRih+Sz+ JH2mnczdQ/07oxdXKvlcNFuQ5BEb/G/lx+gpIIWPB+QHYcU4zGD1nG+jBXCGdtShvKHbiagP6J7 VTbjQCGpxala2mYYpjL/17P1fZwQCuNvJi5Npd48ZQhFl5McKPNsMvbZ9adEh5kxirLMPYx01/2 X+S2BaYB4fminOae+21/2CZCU9J8r6a8uuzY0wQiP9NMUeUNf1VrSS9luDld5ge5Xv49vjTP1ms 1mWTtnM3SD//975bcOOYESUqd54tup7LMZGgem8FTljt3ViZCC1cF6t0PJ4l0xD6c7+3sm8aNYy plbLi6OQ1rCe0wGCEK8i76EATTBe8ZLHRhkqsjr4YYGBZhqDPVfWvQwI7G7TsfEccCLrhbqM X-Proofpoint-ORIG-GUID: 55xi-o5Q5aD3wGlIU2KhuoyFd0gCW1HS X-Authority-Analysis: v=2.4 cv=etffzppX c=1 sm=1 tr=0 ts=6850cfff cx=c_pps a=nuhDOHQX5FNHPW3J6Bj6AA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=6IFa9wvqVegA:10 a=EUspDBNiAAAA:8 a=COk6AnOGAAAA:8 a=UMluCPnEzjiUAf4N7sYA:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-06-17_01,2025-06-13_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 impostorscore=0 adultscore=0 spamscore=0 malwarescore=0 priorityscore=1501 suspectscore=0 phishscore=0 mlxlogscore=999 lowpriorityscore=0 bulkscore=0 mlxscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2506170019 Content-Type: text/plain; charset="utf-8" SA8775p supports 'link_down' reset on hardware, so add it for both pcie0 and pcie1, which can provide a better user experience. Reviewed-by: Konrad Dybcio Signed-off-by: Ziyue Zhang --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qc= om/sa8775p.dtsi index d7248014368b..c8ce3d42c894 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -7152,8 +7152,11 @@ pcie0: pcie@1c00000 { iommu-map =3D <0x0 &pcie_smmu 0x0000 0x1>, <0x100 &pcie_smmu 0x0001 0x1>; =20 - resets =3D <&gcc GCC_PCIE_0_BCR>; - reset-names =3D "pci"; + resets =3D <&gcc GCC_PCIE_0_BCR>, + <&gcc GCC_PCIE_0_LINK_DOWN_BCR>; + reset-names =3D "pci", + "link_down"; + power-domains =3D <&gcc PCIE_0_GDSC>; =20 phys =3D <&pcie0_phy>; @@ -7312,8 +7315,11 @@ pcie1: pcie@1c10000 { iommu-map =3D <0x0 &pcie_smmu 0x0080 0x1>, <0x100 &pcie_smmu 0x0081 0x1>; =20 - resets =3D <&gcc GCC_PCIE_1_BCR>; - reset-names =3D "pci"; + resets =3D <&gcc GCC_PCIE_1_BCR>, + <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; + reset-names =3D "pci", + "link_down"; + power-domains =3D <&gcc PCIE_1_GDSC>; =20 phys =3D <&pcie1_phy>; --=20 2.34.1