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These will be used by the gcc-ipq5424 driver that provides the interconnect services by using the icc-clk framework. Signed-off-by: Luo Jie --- include/dt-bindings/interconnect/qcom,ipq5424.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/dt-bindings/interconnect/qcom,ipq5424.h b/include/dt-b= indings/interconnect/qcom,ipq5424.h index a770356112ee..66cd9a9ece03 100644 --- a/include/dt-bindings/interconnect/qcom,ipq5424.h +++ b/include/dt-bindings/interconnect/qcom,ipq5424.h @@ -20,5 +20,11 @@ #define SLAVE_CNOC_PCIE3 15 #define MASTER_CNOC_USB 16 #define SLAVE_CNOC_USB 17 +#define MASTER_NSSNOC_NSSCC 18 +#define SLAVE_NSSNOC_NSSCC 19 +#define MASTER_NSSNOC_SNOC_0 20 +#define SLAVE_NSSNOC_SNOC_0 21 +#define MASTER_NSSNOC_SNOC_1 22 +#define SLAVE_NSSNOC_SNOC_1 23 =20 #endif /* INTERCONNECT_QCOM_IPQ5424_H */ --=20 2.34.1 From nobody Fri Oct 10 09:53:02 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E1F412206A6; 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The network subsystem (NSS) can be connected to these NoCs. Also update to use the expected icc_first_node_id for registering the icc clocks. Signed-off-by: Luo Jie --- drivers/clk/qcom/gcc-ipq5424.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/gcc-ipq5424.c b/drivers/clk/qcom/gcc-ipq5424.c index 3d42f3d85c7a..3a01cb277cac 100644 --- a/drivers/clk/qcom/gcc-ipq5424.c +++ b/drivers/clk/qcom/gcc-ipq5424.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2018,2020 The Linux Foundation. All rights reserved. - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. 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Signed-off-by: Luo Jie --- include/dt-bindings/clock/qcom,ipq5424-gcc.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/dt-bindings/clock/qcom,ipq5424-gcc.h b/include/dt-bind= ings/clock/qcom,ipq5424-gcc.h index c15ad16923bd..ab23c6844a06 100644 --- a/include/dt-bindings/clock/qcom,ipq5424-gcc.h +++ b/include/dt-bindings/clock/qcom,ipq5424-gcc.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ /* * Copyright (c) 2018,2020 The Linux Foundation. All rights reserved. - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. 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Signed-off-by: Luo Jie --- drivers/clk/qcom/gcc-ipq5424.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/clk/qcom/gcc-ipq5424.c b/drivers/clk/qcom/gcc-ipq5424.c index 3a01cb277cac..370e2e775044 100644 --- a/drivers/clk/qcom/gcc-ipq5424.c +++ b/drivers/clk/qcom/gcc-ipq5424.c @@ -79,6 +79,20 @@ static struct clk_fixed_factor gpll0_div2 =3D { }, }; =20 +static struct clk_alpha_pll_postdiv gpll0_out_aux =3D { + .offset =3D 0x20000, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gpll0_out_aux", + .parent_hws =3D (const struct clk_hw *[]) { + &gpll0.clkr.hw + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_postdiv_ro_ops, + }, +}; + static struct clk_alpha_pll gpll2 =3D { .offset =3D 0x21000, .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_NSS_HUAYRA], @@ -2934,6 +2948,7 @@ static struct clk_regmap *gcc_ipq5424_clocks[] =3D { [GPLL2] =3D &gpll2.clkr, [GPLL2_OUT_MAIN] =3D &gpll2_out_main.clkr, [GPLL4] =3D &gpll4.clkr, + [GPLL0_OUT_AUX] =3D &gpll0_out_aux.clkr, }; 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Add the compatible "qcom,ipq5424-nsscc" support based on the current IPQ9574 NSS clock controller DT binding file. ICC clocks are always provided by the NSS clock controller of IPQ9574 and IPQ5424, so add interconnect-cells as required DT property. Also add master/slave ids for IPQ5424 networking interfaces, which is used by nss-ipq5424 driver for providing interconnect services using icc-clk framework. Signed-off-by: Luo Jie --- .../bindings/clock/qcom,ipq9574-nsscc.yaml | 66 ++++++++++++++++++= +--- include/dt-bindings/clock/qcom,ipq5424-nsscc.h | 65 ++++++++++++++++++= +++ include/dt-bindings/interconnect/qcom,ipq5424.h | 13 +++++ include/dt-bindings/reset/qcom,ipq5424-nsscc.h | 46 +++++++++++++++ 4 files changed, 182 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yam= l b/Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml index 17252b6ea3be..5bc2fe049b26 100644 --- a/Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/clock/qcom,ipq9574-nsscc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: Qualcomm Networking Sub System Clock & Reset Controller on IPQ9574 +title: Qualcomm Networking Sub System Clock & Reset Controller on IPQ9574 = and IPQ5424 =20 maintainers: - Bjorn Andersson @@ -12,21 +12,25 @@ maintainers: =20 description: | Qualcomm networking sub system clock control module provides the clocks, - resets on IPQ9574 + resets on IPQ9574 and IPQ5424 =20 - See also:: + See also: + include/dt-bindings/clock/qcom,ipq5424-nsscc.h include/dt-bindings/clock/qcom,ipq9574-nsscc.h + include/dt-bindings/reset/qcom,ipq5424-nsscc.h include/dt-bindings/reset/qcom,ipq9574-nsscc.h =20 properties: compatible: - const: qcom,ipq9574-nsscc + enum: + - qcom,ipq5424-nsscc + - qcom,ipq9574-nsscc =20 clocks: items: - description: Board XO source - - description: CMN_PLL NSS 1200MHz (Bias PLL cc) clock source - - description: CMN_PLL PPE 353MHz (Bias PLL ubi nc) clock source + - description: CMN_PLL NSS 1200 MHz or 300 MHZ (Bias PLL cc) clock s= ource + - description: CMN_PLL PPE 353 MHz or 375 MHZ (Bias PLL ubi nc) clo= ck source - description: GCC GPLL0 OUT AUX clock source - description: Uniphy0 NSS Rx clock source - description: Uniphy0 NSS Tx clock source @@ -42,8 +46,12 @@ properties: clock-names: items: - const: xo - - const: nss_1200 - - const: ppe_353 + - enum: + - nss_1200 + - nss_300 + - enum: + - ppe_353 + - ppe_375 - const: gpll0_out - const: uniphy0_rx - const: uniphy0_tx @@ -57,9 +65,50 @@ required: - compatible - clocks - clock-names + - '#interconnect-cells' =20 allOf: - $ref: qcom,gcc.yaml# + - if: + properties: + compatible: + contains: + const: qcom,ipq9574-nsscc + then: + properties: + clock-names: + items: + - const: xo + - const: nss_1200 + - const: ppe_353 + - const: gpll0_out + - const: uniphy0_rx + - const: uniphy0_tx + - const: uniphy1_rx + - const: uniphy1_tx + - const: uniphy2_rx + - const: uniphy2_tx + - const: bus + - if: + properties: + compatible: + contains: + const: qcom,ipq5424-nsscc + then: + properties: + clock-names: + items: + - const: xo + - const: nss_300 + - const: ppe_375 + - const: gpll0_out + - const: uniphy0_rx + - const: uniphy0_tx + - const: uniphy1_rx + - const: uniphy1_tx + - const: uniphy2_rx + - const: uniphy2_tx + - const: bus =20 unevaluatedProperties: false =20 @@ -94,5 +143,6 @@ examples: "bus"; #clock-cells =3D <1>; #reset-cells =3D <1>; + #interconnect-cells =3D <1>; }; ... diff --git a/include/dt-bindings/clock/qcom,ipq5424-nsscc.h b/include/dt-bi= ndings/clock/qcom,ipq5424-nsscc.h new file mode 100644 index 000000000000..59ce056ead93 --- /dev/null +++ b/include/dt-bindings/clock/qcom,ipq5424-nsscc.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserve= d. + */ + +#ifndef _DT_BINDINGS_CLOCK_QCOM_IPQ5424_NSSCC_H +#define _DT_BINDINGS_CLOCK_QCOM_IPQ5424_NSSCC_H + +/* NSS_CC clocks */ +#define NSS_CC_CE_APB_CLK 0 +#define NSS_CC_CE_AXI_CLK 1 +#define NSS_CC_CE_CLK_SRC 2 +#define NSS_CC_CFG_CLK_SRC 3 +#define NSS_CC_DEBUG_CLK 4 +#define NSS_CC_EIP_BFDCD_CLK_SRC 5 +#define NSS_CC_EIP_CLK 6 +#define NSS_CC_NSS_CSR_CLK 7 +#define NSS_CC_NSSNOC_CE_APB_CLK 8 +#define NSS_CC_NSSNOC_CE_AXI_CLK 9 +#define NSS_CC_NSSNOC_EIP_CLK 10 +#define NSS_CC_NSSNOC_NSS_CSR_CLK 11 +#define NSS_CC_NSSNOC_PPE_CFG_CLK 12 +#define NSS_CC_NSSNOC_PPE_CLK 13 +#define NSS_CC_PORT1_MAC_CLK 14 +#define NSS_CC_PORT1_RX_CLK 15 +#define NSS_CC_PORT1_RX_CLK_SRC 16 +#define NSS_CC_PORT1_RX_DIV_CLK_SRC 17 +#define NSS_CC_PORT1_TX_CLK 18 +#define NSS_CC_PORT1_TX_CLK_SRC 19 +#define NSS_CC_PORT1_TX_DIV_CLK_SRC 20 +#define NSS_CC_PORT2_MAC_CLK 21 +#define NSS_CC_PORT2_RX_CLK 22 +#define NSS_CC_PORT2_RX_CLK_SRC 23 +#define NSS_CC_PORT2_RX_DIV_CLK_SRC 24 +#define NSS_CC_PORT2_TX_CLK 25 +#define NSS_CC_PORT2_TX_CLK_SRC 26 +#define NSS_CC_PORT2_TX_DIV_CLK_SRC 27 +#define NSS_CC_PORT3_MAC_CLK 28 +#define NSS_CC_PORT3_RX_CLK 29 +#define NSS_CC_PORT3_RX_CLK_SRC 30 +#define NSS_CC_PORT3_RX_DIV_CLK_SRC 31 +#define NSS_CC_PORT3_TX_CLK 32 +#define NSS_CC_PORT3_TX_CLK_SRC 33 +#define NSS_CC_PORT3_TX_DIV_CLK_SRC 34 +#define NSS_CC_PPE_CLK_SRC 35 +#define NSS_CC_PPE_EDMA_CFG_CLK 36 +#define NSS_CC_PPE_EDMA_CLK 37 +#define NSS_CC_PPE_SWITCH_BTQ_CLK 38 +#define NSS_CC_PPE_SWITCH_CFG_CLK 39 +#define NSS_CC_PPE_SWITCH_CLK 40 +#define NSS_CC_PPE_SWITCH_IPE_CLK 41 +#define NSS_CC_UNIPHY_PORT1_RX_CLK 42 +#define NSS_CC_UNIPHY_PORT1_TX_CLK 43 +#define NSS_CC_UNIPHY_PORT2_RX_CLK 44 +#define NSS_CC_UNIPHY_PORT2_TX_CLK 45 +#define NSS_CC_UNIPHY_PORT3_RX_CLK 46 +#define NSS_CC_UNIPHY_PORT3_TX_CLK 47 +#define NSS_CC_XGMAC0_PTP_REF_CLK 48 +#define NSS_CC_XGMAC0_PTP_REF_DIV_CLK_SRC 49 +#define NSS_CC_XGMAC1_PTP_REF_CLK 50 +#define NSS_CC_XGMAC1_PTP_REF_DIV_CLK_SRC 51 +#define NSS_CC_XGMAC2_PTP_REF_CLK 52 +#define NSS_CC_XGMAC2_PTP_REF_DIV_CLK_SRC 53 + +#endif diff --git a/include/dt-bindings/interconnect/qcom,ipq5424.h b/include/dt-b= indings/interconnect/qcom,ipq5424.h index 66cd9a9ece03..a78604beff99 100644 --- a/include/dt-bindings/interconnect/qcom,ipq5424.h +++ b/include/dt-bindings/interconnect/qcom,ipq5424.h @@ -27,4 +27,17 @@ #define MASTER_NSSNOC_SNOC_1 22 #define SLAVE_NSSNOC_SNOC_1 23 =20 +#define MASTER_NSSNOC_PPE 0 +#define SLAVE_NSSNOC_PPE 1 +#define MASTER_NSSNOC_PPE_CFG 2 +#define SLAVE_NSSNOC_PPE_CFG 3 +#define MASTER_NSSNOC_NSS_CSR 4 +#define SLAVE_NSSNOC_NSS_CSR 5 +#define MASTER_NSSNOC_CE_AXI 6 +#define SLAVE_NSSNOC_CE_AXI 7 +#define MASTER_NSSNOC_CE_APB 8 +#define SLAVE_NSSNOC_CE_APB 9 +#define MASTER_NSSNOC_EIP 10 +#define SLAVE_NSSNOC_EIP 11 + #endif /* INTERCONNECT_QCOM_IPQ5424_H */ diff --git a/include/dt-bindings/reset/qcom,ipq5424-nsscc.h b/include/dt-bi= ndings/reset/qcom,ipq5424-nsscc.h new file mode 100644 index 000000000000..f2f7eaa28b21 --- /dev/null +++ b/include/dt-bindings/reset/qcom,ipq5424-nsscc.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserve= d. + */ + +#ifndef _DT_BINDINGS_RESET_QCOM_IPQ5424_NSSCC_H +#define _DT_BINDINGS_RESET_QCOM_IPQ5424_NSSCC_H + +#define NSS_CC_CE_APB_CLK_ARES 0 +#define NSS_CC_CE_AXI_CLK_ARES 1 +#define NSS_CC_DEBUG_CLK_ARES 2 +#define NSS_CC_EIP_CLK_ARES 3 +#define NSS_CC_NSS_CSR_CLK_ARES 4 +#define NSS_CC_NSSNOC_CE_APB_CLK_ARES 5 +#define NSS_CC_NSSNOC_CE_AXI_CLK_ARES 6 +#define NSS_CC_NSSNOC_EIP_CLK_ARES 7 +#define NSS_CC_NSSNOC_NSS_CSR_CLK_ARES 8 +#define NSS_CC_NSSNOC_PPE_CLK_ARES 9 +#define NSS_CC_NSSNOC_PPE_CFG_CLK_ARES 10 +#define NSS_CC_PORT1_MAC_CLK_ARES 11 +#define NSS_CC_PORT1_RX_CLK_ARES 12 +#define NSS_CC_PORT1_TX_CLK_ARES 13 +#define NSS_CC_PORT2_MAC_CLK_ARES 14 +#define NSS_CC_PORT2_RX_CLK_ARES 15 +#define NSS_CC_PORT2_TX_CLK_ARES 16 +#define NSS_CC_PORT3_MAC_CLK_ARES 17 +#define NSS_CC_PORT3_RX_CLK_ARES 18 +#define NSS_CC_PORT3_TX_CLK_ARES 19 +#define NSS_CC_PPE_BCR 20 +#define NSS_CC_PPE_EDMA_CLK_ARES 21 +#define NSS_CC_PPE_EDMA_CFG_CLK_ARES 22 +#define NSS_CC_PPE_SWITCH_BTQ_CLK_ARES 23 +#define NSS_CC_PPE_SWITCH_CLK_ARES 24 +#define NSS_CC_PPE_SWITCH_CFG_CLK_ARES 25 +#define NSS_CC_PPE_SWITCH_IPE_CLK_ARES 26 +#define NSS_CC_UNIPHY_PORT1_RX_CLK_ARES 27 +#define NSS_CC_UNIPHY_PORT1_TX_CLK_ARES 28 +#define NSS_CC_UNIPHY_PORT2_RX_CLK_ARES 29 +#define NSS_CC_UNIPHY_PORT2_TX_CLK_ARES 30 +#define NSS_CC_UNIPHY_PORT3_RX_CLK_ARES 31 +#define NSS_CC_UNIPHY_PORT3_TX_CLK_ARES 32 +#define NSS_CC_XGMAC0_PTP_REF_CLK_ARES 33 +#define NSS_CC_XGMAC1_PTP_REF_CLK_ARES 34 +#define NSS_CC_XGMAC2_PTP_REF_CLK_ARES 35 + +#endif --=20 2.34.1 From nobody Fri Oct 10 09:53:02 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B0E5C2E0B63; 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The icc-clk framework is used to enable NoC related clocks to create paths so that the networking blocks can connect to these NoCs. Signed-off-by: Luo Jie --- drivers/clk/qcom/Kconfig | 11 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/nsscc-ipq5424.c | 1340 ++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 1352 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 7d5dac26b244..fc4755f18b84 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -281,6 +281,17 @@ config IPQ_GCC_9574 i2c, USB, SD/eMMC, etc. Select this for the root clock of ipq9574. =20 +config IPQ_NSSCC_5424 + tristate "IPQ5424 NSS Clock Controller" + depends on ARM64 || COMPILE_TEST + depends on IPQ_GCC_5424 + help + Support for NSS clock controller on ipq5424 devices. + NSSCC receives the clock sources from GCC, CMN PLL and UNIPHY (PCS). + It in turn supplies the clocks and resets to the networking hardware. + Say Y or M if you want to enable networking function on the + IPQ5424 devices. + config IPQ_NSSCC_9574 tristate "IPQ9574 NSS Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 96862e99e5d4..1c3c35176d13 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -39,6 +39,7 @@ obj-$(CONFIG_IPQ_GCC_6018) +=3D gcc-ipq6018.o obj-$(CONFIG_IPQ_GCC_806X) +=3D gcc-ipq806x.o obj-$(CONFIG_IPQ_GCC_8074) +=3D gcc-ipq8074.o obj-$(CONFIG_IPQ_GCC_9574) +=3D gcc-ipq9574.o +obj-$(CONFIG_IPQ_NSSCC_5424) +=3D nsscc-ipq5424.o obj-$(CONFIG_IPQ_NSSCC_9574) +=3D nsscc-ipq9574.o obj-$(CONFIG_IPQ_LCC_806X) +=3D lcc-ipq806x.o obj-$(CONFIG_IPQ_NSSCC_QCA8K) +=3D nsscc-qca8k.o diff --git a/drivers/clk/qcom/nsscc-ipq5424.c b/drivers/clk/qcom/nsscc-ipq5= 424.c new file mode 100644 index 000000000000..d9de56621702 --- /dev/null +++ b/drivers/clk/qcom/nsscc-ipq5424.c @@ -0,0 +1,1340 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserve= d. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "common.h" +#include "reset.h" + +/* Need to match the order of clocks in DT binding */ +enum { + DT_CMN_PLL_XO_CLK, + DT_CMN_PLL_NSS_300M_CLK, + DT_CMN_PLL_NSS_375M_CLK, + DT_GCC_GPLL0_OUT_AUX, + DT_UNIPHY0_NSS_RX_CLK, + DT_UNIPHY0_NSS_TX_CLK, + DT_UNIPHY1_NSS_RX_CLK, + DT_UNIPHY1_NSS_TX_CLK, + DT_UNIPHY2_NSS_RX_CLK, + DT_UNIPHY2_NSS_TX_CLK, +}; + +enum { + P_CMN_PLL_XO_CLK, + P_CMN_PLL_NSS_300M_CLK, + P_CMN_PLL_NSS_375M_CLK, + P_GCC_GPLL0_OUT_AUX, + P_UNIPHY0_NSS_RX_CLK, + P_UNIPHY0_NSS_TX_CLK, + P_UNIPHY1_NSS_RX_CLK, + P_UNIPHY1_NSS_TX_CLK, + P_UNIPHY2_NSS_RX_CLK, + P_UNIPHY2_NSS_TX_CLK, +}; + +static const struct parent_map nss_cc_parent_map_0[] =3D { + { P_CMN_PLL_XO_CLK, 0 }, + { P_GCC_GPLL0_OUT_AUX, 2 }, + { P_CMN_PLL_NSS_300M_CLK, 5 }, + { P_CMN_PLL_NSS_375M_CLK, 6 }, +}; + +static const struct clk_parent_data nss_cc_parent_data_0[] =3D { + { .index =3D DT_CMN_PLL_XO_CLK }, + { .index =3D DT_GCC_GPLL0_OUT_AUX }, + { .index =3D DT_CMN_PLL_NSS_300M_CLK }, + { .index =3D DT_CMN_PLL_NSS_375M_CLK }, +}; + +static const struct parent_map nss_cc_parent_map_1[] =3D { + { P_CMN_PLL_XO_CLK, 0 }, + { P_GCC_GPLL0_OUT_AUX, 2 }, + { P_UNIPHY0_NSS_RX_CLK, 3 }, + { P_UNIPHY0_NSS_TX_CLK, 4 }, + { P_CMN_PLL_NSS_300M_CLK, 5 }, + { P_CMN_PLL_NSS_375M_CLK, 6 }, +}; + +static const struct clk_parent_data nss_cc_parent_data_1[] =3D { + { .index =3D DT_CMN_PLL_XO_CLK }, + { .index =3D DT_GCC_GPLL0_OUT_AUX }, + { .index =3D DT_UNIPHY0_NSS_RX_CLK }, + { .index =3D DT_UNIPHY0_NSS_TX_CLK }, + { .index =3D DT_CMN_PLL_NSS_300M_CLK }, + { .index =3D DT_CMN_PLL_NSS_375M_CLK }, +}; + +static const struct parent_map nss_cc_parent_map_2[] =3D { + { P_CMN_PLL_XO_CLK, 0 }, + { P_GCC_GPLL0_OUT_AUX, 2 }, + { P_UNIPHY1_NSS_RX_CLK, 3 }, + { P_UNIPHY1_NSS_TX_CLK, 4 }, + { P_CMN_PLL_NSS_300M_CLK, 5 }, + { P_CMN_PLL_NSS_375M_CLK, 6 }, +}; + +static const struct clk_parent_data nss_cc_parent_data_2[] =3D { + { .index =3D DT_CMN_PLL_XO_CLK }, + { .index =3D DT_GCC_GPLL0_OUT_AUX }, + { .index =3D DT_UNIPHY1_NSS_RX_CLK }, + { .index =3D DT_UNIPHY1_NSS_TX_CLK }, + { .index =3D DT_CMN_PLL_NSS_300M_CLK }, + { .index =3D DT_CMN_PLL_NSS_375M_CLK }, +}; + +static const struct parent_map nss_cc_parent_map_3[] =3D { + { P_CMN_PLL_XO_CLK, 0 }, + { P_GCC_GPLL0_OUT_AUX, 2 }, + { P_UNIPHY2_NSS_RX_CLK, 3 }, + { P_UNIPHY2_NSS_TX_CLK, 4 }, + { P_CMN_PLL_NSS_300M_CLK, 5 }, + { P_CMN_PLL_NSS_375M_CLK, 6 }, +}; + +static const struct clk_parent_data nss_cc_parent_data_3[] =3D { + { .index =3D DT_CMN_PLL_XO_CLK }, + { .index =3D DT_GCC_GPLL0_OUT_AUX }, + { .index =3D DT_UNIPHY2_NSS_RX_CLK }, + { .index =3D DT_UNIPHY2_NSS_TX_CLK }, + { .index =3D DT_CMN_PLL_NSS_300M_CLK }, + { .index =3D DT_CMN_PLL_NSS_375M_CLK }, +}; + +static const struct freq_tbl ftbl_nss_cc_ce_clk_src[] =3D { + F(24000000, P_CMN_PLL_XO_CLK, 1, 0, 0), + F(375000000, P_CMN_PLL_NSS_375M_CLK, 1, 0, 0), + { } +}; + +static struct clk_rcg2 nss_cc_ce_clk_src =3D { + .cmd_rcgr =3D 0x5e0, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D nss_cc_parent_map_0, + .freq_tbl =3D ftbl_nss_cc_ce_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data){ + .name =3D "nss_cc_ce_clk_src", + .parent_data =3D nss_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(nss_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_nss_cc_cfg_clk_src[] =3D { + F(100000000, P_GCC_GPLL0_OUT_AUX, 8, 0, 0), + { } +}; + +static struct clk_rcg2 nss_cc_cfg_clk_src =3D { + .cmd_rcgr =3D 0x6a8, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D nss_cc_parent_map_0, + .freq_tbl =3D ftbl_nss_cc_cfg_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data){ + .name =3D "nss_cc_cfg_clk_src", + .parent_data =3D nss_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(nss_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_nss_cc_eip_bfdcd_clk_src[] =3D { + F(300000000, P_CMN_PLL_NSS_300M_CLK, 1, 0, 0), + F(375000000, P_CMN_PLL_NSS_375M_CLK, 1, 0, 0), + { } +}; + +static struct clk_rcg2 nss_cc_eip_bfdcd_clk_src =3D { + .cmd_rcgr =3D 0x644, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D nss_cc_parent_map_0, + .freq_tbl =3D ftbl_nss_cc_eip_bfdcd_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data){ + .name =3D "nss_cc_eip_bfdcd_clk_src", + .parent_data =3D nss_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(nss_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_conf ftbl_nss_cc_port1_rx_clk_src_25[] =3D { + C(P_UNIPHY0_NSS_RX_CLK, 12.5, 0, 0), + C(P_UNIPHY0_NSS_RX_CLK, 5, 0, 0), +}; + +static const struct freq_conf ftbl_nss_cc_port1_rx_clk_src_125[] =3D { + C(P_UNIPHY0_NSS_RX_CLK, 2.5, 0, 0), + C(P_UNIPHY0_NSS_RX_CLK, 1, 0, 0), +}; + +static const struct freq_multi_tbl ftbl_nss_cc_port1_rx_clk_src[] =3D { + FMS(24000000, P_CMN_PLL_XO_CLK, 1, 0, 0), + FM(25000000, ftbl_nss_cc_port1_rx_clk_src_25), + FMS(78125000, P_UNIPHY0_NSS_RX_CLK, 4, 0, 0), + FM(125000000, ftbl_nss_cc_port1_rx_clk_src_125), + FMS(156250000, P_UNIPHY0_NSS_RX_CLK, 2, 0, 0), + FMS(312500000, P_UNIPHY0_NSS_RX_CLK, 1, 0, 0), + { } +}; + +static struct clk_rcg2 nss_cc_port1_rx_clk_src =3D { + .cmd_rcgr =3D 0x4b4, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D nss_cc_parent_map_1, + .freq_multi_tbl =3D ftbl_nss_cc_port1_rx_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data){ + .name =3D "nss_cc_port1_rx_clk_src", + .parent_data =3D nss_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(nss_cc_parent_data_1), + .ops =3D &clk_rcg2_fm_ops, + }, +}; + +static const struct freq_conf ftbl_nss_cc_port1_tx_clk_src_25[] =3D { + C(P_UNIPHY0_NSS_TX_CLK, 12.5, 0, 0), + C(P_UNIPHY0_NSS_TX_CLK, 5, 0, 0), +}; + +static const struct freq_conf ftbl_nss_cc_port1_tx_clk_src_125[] =3D { + C(P_UNIPHY0_NSS_TX_CLK, 2.5, 0, 0), + C(P_UNIPHY0_NSS_TX_CLK, 1, 0, 0), +}; + +static const struct freq_multi_tbl ftbl_nss_cc_port1_tx_clk_src[] =3D { + FMS(24000000, P_CMN_PLL_XO_CLK, 1, 0, 0), + FM(25000000, ftbl_nss_cc_port1_tx_clk_src_25), + FMS(78125000, P_UNIPHY0_NSS_TX_CLK, 4, 0, 0), + FM(125000000, ftbl_nss_cc_port1_tx_clk_src_125), + FMS(156250000, P_UNIPHY0_NSS_TX_CLK, 2, 0, 0), + FMS(312500000, P_UNIPHY0_NSS_TX_CLK, 1, 0, 0), + { } +}; + +static struct clk_rcg2 nss_cc_port1_tx_clk_src =3D { + .cmd_rcgr =3D 0x4c0, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D nss_cc_parent_map_1, + .freq_multi_tbl =3D ftbl_nss_cc_port1_tx_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data){ + .name =3D "nss_cc_port1_tx_clk_src", + .parent_data =3D nss_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(nss_cc_parent_data_1), + .ops =3D &clk_rcg2_fm_ops, + }, +}; + +static const struct freq_conf ftbl_nss_cc_port2_rx_clk_src_25[] =3D { + C(P_UNIPHY1_NSS_RX_CLK, 12.5, 0, 0), + C(P_UNIPHY1_NSS_RX_CLK, 5, 0, 0), +}; + +static const struct freq_conf ftbl_nss_cc_port2_rx_clk_src_125[] =3D { + C(P_UNIPHY1_NSS_RX_CLK, 2.5, 0, 0), + C(P_UNIPHY1_NSS_RX_CLK, 1, 0, 0), +}; + +static const struct freq_multi_tbl ftbl_nss_cc_port2_rx_clk_src[] =3D { + FMS(24000000, P_CMN_PLL_XO_CLK, 1, 0, 0), + FM(25000000, ftbl_nss_cc_port2_rx_clk_src_25), + FMS(78125000, P_UNIPHY1_NSS_RX_CLK, 4, 0, 0), + FM(125000000, ftbl_nss_cc_port2_rx_clk_src_125), + FMS(156250000, P_UNIPHY1_NSS_RX_CLK, 2, 0, 0), + FMS(312500000, P_UNIPHY1_NSS_RX_CLK, 1, 0, 0), + { } +}; + +static struct clk_rcg2 nss_cc_port2_rx_clk_src =3D { + .cmd_rcgr =3D 0x4cc, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D nss_cc_parent_map_2, + .freq_multi_tbl =3D ftbl_nss_cc_port2_rx_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data){ + .name =3D "nss_cc_port2_rx_clk_src", + .parent_data =3D nss_cc_parent_data_2, + .num_parents =3D ARRAY_SIZE(nss_cc_parent_data_2), + .ops =3D &clk_rcg2_fm_ops, + }, +}; + +static const struct freq_conf ftbl_nss_cc_port2_tx_clk_src_25[] =3D { + C(P_UNIPHY1_NSS_TX_CLK, 12.5, 0, 0), + C(P_UNIPHY1_NSS_TX_CLK, 5, 0, 0), +}; + +static const struct freq_conf ftbl_nss_cc_port2_tx_clk_src_125[] =3D { + C(P_UNIPHY1_NSS_TX_CLK, 2.5, 0, 0), + C(P_UNIPHY1_NSS_TX_CLK, 1, 0, 0), +}; + +static const struct freq_multi_tbl ftbl_nss_cc_port2_tx_clk_src[] =3D { + FMS(24000000, P_CMN_PLL_XO_CLK, 1, 0, 0), + FM(25000000, ftbl_nss_cc_port2_tx_clk_src_25), + FMS(78125000, P_UNIPHY1_NSS_TX_CLK, 4, 0, 0), + FM(125000000, ftbl_nss_cc_port2_tx_clk_src_125), + FMS(156250000, P_UNIPHY1_NSS_TX_CLK, 2, 0, 0), + FMS(312500000, P_UNIPHY1_NSS_TX_CLK, 1, 0, 0), + { } +}; + +static struct clk_rcg2 nss_cc_port2_tx_clk_src =3D { + .cmd_rcgr =3D 0x4d8, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D nss_cc_parent_map_2, + .freq_multi_tbl =3D ftbl_nss_cc_port2_tx_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data){ + .name =3D "nss_cc_port2_tx_clk_src", + .parent_data =3D nss_cc_parent_data_2, + .num_parents =3D ARRAY_SIZE(nss_cc_parent_data_2), + .ops =3D &clk_rcg2_fm_ops, + }, +}; + +static const struct freq_conf ftbl_nss_cc_port3_rx_clk_src_25[] =3D { + C(P_UNIPHY2_NSS_RX_CLK, 12.5, 0, 0), + C(P_UNIPHY2_NSS_RX_CLK, 5, 0, 0), +}; + +static const struct freq_conf ftbl_nss_cc_port3_rx_clk_src_125[] =3D { + C(P_UNIPHY2_NSS_RX_CLK, 2.5, 0, 0), + C(P_UNIPHY2_NSS_RX_CLK, 1, 0, 0), +}; + +static const struct freq_multi_tbl ftbl_nss_cc_port3_rx_clk_src[] =3D { + FMS(24000000, P_CMN_PLL_XO_CLK, 1, 0, 0), + FM(25000000, ftbl_nss_cc_port3_rx_clk_src_25), + FMS(78125000, P_UNIPHY2_NSS_RX_CLK, 4, 0, 0), + FM(125000000, ftbl_nss_cc_port3_rx_clk_src_125), + FMS(156250000, P_UNIPHY2_NSS_RX_CLK, 2, 0, 0), + FMS(312500000, P_UNIPHY2_NSS_RX_CLK, 1, 0, 0), + { } +}; + +static struct clk_rcg2 nss_cc_port3_rx_clk_src =3D { + .cmd_rcgr =3D 0x4e4, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D nss_cc_parent_map_3, + .freq_multi_tbl =3D ftbl_nss_cc_port3_rx_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data){ + .name =3D "nss_cc_port3_rx_clk_src", + .parent_data =3D nss_cc_parent_data_3, + .num_parents =3D ARRAY_SIZE(nss_cc_parent_data_3), + .ops =3D &clk_rcg2_fm_ops, + }, +}; + +static const struct freq_conf ftbl_nss_cc_port3_tx_clk_src_25[] =3D { + C(P_UNIPHY2_NSS_TX_CLK, 12.5, 0, 0), + C(P_UNIPHY2_NSS_TX_CLK, 5, 0, 0), +}; + +static const struct freq_conf ftbl_nss_cc_port3_tx_clk_src_125[] =3D { + C(P_UNIPHY2_NSS_TX_CLK, 2.5, 0, 0), + C(P_UNIPHY2_NSS_TX_CLK, 1, 0, 0), +}; + +static const struct freq_multi_tbl ftbl_nss_cc_port3_tx_clk_src[] =3D { + FMS(24000000, P_CMN_PLL_XO_CLK, 1, 0, 0), + FM(25000000, ftbl_nss_cc_port3_tx_clk_src_25), + FMS(78125000, P_UNIPHY2_NSS_TX_CLK, 4, 0, 0), + FM(125000000, ftbl_nss_cc_port3_tx_clk_src_125), + FMS(156250000, P_UNIPHY2_NSS_TX_CLK, 2, 0, 0), + FMS(312500000, P_UNIPHY2_NSS_TX_CLK, 1, 0, 0), + { } +}; + +static struct clk_rcg2 nss_cc_port3_tx_clk_src =3D { + .cmd_rcgr =3D 0x4f0, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D nss_cc_parent_map_3, + .freq_multi_tbl =3D ftbl_nss_cc_port3_tx_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data){ + .name =3D "nss_cc_port3_tx_clk_src", + .parent_data =3D nss_cc_parent_data_3, + .num_parents =3D ARRAY_SIZE(nss_cc_parent_data_3), + .ops =3D &clk_rcg2_fm_ops, + }, +}; + +static struct clk_rcg2 nss_cc_ppe_clk_src =3D { + .cmd_rcgr =3D 0x3ec, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D nss_cc_parent_map_0, + .freq_tbl =3D ftbl_nss_cc_ce_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data){ + .name =3D "nss_cc_ppe_clk_src", + .parent_data =3D nss_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(nss_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_regmap_div nss_cc_port1_rx_div_clk_src =3D { + .reg =3D 0x4bc, + .shift =3D 0, + .width =3D 9, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_port1_rx_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]){ + &nss_cc_port1_rx_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ops, + }, +}; + +static struct clk_regmap_div nss_cc_port1_tx_div_clk_src =3D { + .reg =3D 0x4c8, + .shift =3D 0, + .width =3D 9, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_port1_tx_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]){ + &nss_cc_port1_tx_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ops, + }, +}; + +static struct clk_regmap_div nss_cc_port2_rx_div_clk_src =3D { + .reg =3D 0x4d4, + .shift =3D 0, + .width =3D 9, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_port2_rx_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]){ + &nss_cc_port2_rx_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ops, + }, +}; + +static struct clk_regmap_div nss_cc_port2_tx_div_clk_src =3D { + .reg =3D 0x4e0, + .shift =3D 0, + .width =3D 9, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_port2_tx_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]){ + &nss_cc_port2_tx_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ops, + }, +}; + +static struct clk_regmap_div nss_cc_port3_rx_div_clk_src =3D { + .reg =3D 0x4ec, + .shift =3D 0, + .width =3D 9, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_port3_rx_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]){ + &nss_cc_port3_rx_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ops, + }, +}; + +static struct clk_regmap_div nss_cc_port3_tx_div_clk_src =3D { + .reg =3D 0x4f8, + .shift =3D 0, + .width =3D 9, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_port3_tx_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]){ + &nss_cc_port3_tx_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ops, + }, +}; + +static struct clk_regmap_div nss_cc_xgmac0_ptp_ref_div_clk_src =3D { + .reg =3D 0x3f4, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_xgmac0_ptp_ref_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]){ + &nss_cc_ppe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div nss_cc_xgmac1_ptp_ref_div_clk_src =3D { + .reg =3D 0x3f8, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_xgmac1_ptp_ref_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]){ + &nss_cc_ppe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div nss_cc_xgmac2_ptp_ref_div_clk_src =3D { + .reg =3D 0x3fc, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "nss_cc_xgmac2_ptp_ref_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]){ + &nss_cc_ppe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch nss_cc_ce_apb_clk =3D { + .halt_reg =3D 0x5e8, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x5e8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "nss_cc_ce_apb_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &nss_cc_ce_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_ce_axi_clk =3D { + .halt_reg =3D 0x5ec, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x5ec, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "nss_cc_ce_axi_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &nss_cc_ce_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_debug_clk =3D { + .halt_reg =3D 0x70c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x70c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "nss_cc_debug_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_eip_clk =3D { + .halt_reg =3D 0x658, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x658, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "nss_cc_eip_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &nss_cc_eip_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_nss_csr_clk =3D { + .halt_reg =3D 0x6b0, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x6b0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "nss_cc_nss_csr_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &nss_cc_cfg_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_nssnoc_ce_apb_clk =3D { + .halt_reg =3D 0x5f4, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x5f4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "nss_cc_nssnoc_ce_apb_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &nss_cc_ce_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_nssnoc_ce_axi_clk =3D { + .halt_reg =3D 0x5f8, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x5f8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "nss_cc_nssnoc_ce_axi_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &nss_cc_ce_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_nssnoc_eip_clk =3D { + .halt_reg =3D 0x660, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x660, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "nss_cc_nssnoc_eip_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &nss_cc_eip_bfdcd_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_nssnoc_nss_csr_clk =3D { + .halt_reg =3D 0x6b4, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x6b4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "nss_cc_nssnoc_nss_csr_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &nss_cc_cfg_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_nssnoc_ppe_cfg_clk =3D { + .halt_reg =3D 0x444, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x444, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "nss_cc_nssnoc_ppe_cfg_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &nss_cc_ppe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_nssnoc_ppe_clk =3D { + .halt_reg =3D 0x440, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x440, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "nss_cc_nssnoc_ppe_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &nss_cc_ppe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_port1_mac_clk =3D { + .halt_reg =3D 0x428, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x428, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "nss_cc_port1_mac_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &nss_cc_ppe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_port1_rx_clk =3D { + .halt_reg =3D 0x4fc, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x4fc, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "nss_cc_port1_rx_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &nss_cc_port1_rx_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_port1_tx_clk =3D { + .halt_reg =3D 0x504, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x504, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "nss_cc_port1_tx_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &nss_cc_port1_tx_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_port2_mac_clk =3D { + .halt_reg =3D 0x430, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x430, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "nss_cc_port2_mac_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &nss_cc_ppe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_port2_rx_clk =3D { + .halt_reg =3D 0x50c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x50c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "nss_cc_port2_rx_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &nss_cc_port2_rx_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_port2_tx_clk =3D { + .halt_reg =3D 0x514, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x514, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "nss_cc_port2_tx_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &nss_cc_port2_tx_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_port3_mac_clk =3D { + .halt_reg =3D 0x438, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x438, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "nss_cc_port3_mac_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &nss_cc_ppe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_port3_rx_clk =3D { + .halt_reg =3D 0x51c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x51c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "nss_cc_port3_rx_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &nss_cc_port3_rx_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_port3_tx_clk =3D { + .halt_reg =3D 0x524, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x524, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "nss_cc_port3_tx_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &nss_cc_port3_tx_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_ppe_edma_cfg_clk =3D { + .halt_reg =3D 0x424, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x424, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "nss_cc_ppe_edma_cfg_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &nss_cc_ppe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_ppe_edma_clk =3D { + .halt_reg =3D 0x41c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x41c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "nss_cc_ppe_edma_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &nss_cc_ppe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_ppe_switch_btq_clk =3D { + .halt_reg =3D 0x408, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x408, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "nss_cc_ppe_switch_btq_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &nss_cc_ppe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_ppe_switch_cfg_clk =3D { + .halt_reg =3D 0x418, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x418, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "nss_cc_ppe_switch_cfg_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &nss_cc_ppe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_ppe_switch_clk =3D { + .halt_reg =3D 0x410, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x410, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "nss_cc_ppe_switch_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &nss_cc_ppe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_ppe_switch_ipe_clk =3D { + .halt_reg =3D 0x400, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x400, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "nss_cc_ppe_switch_ipe_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &nss_cc_ppe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_uniphy_port1_rx_clk =3D { + .halt_reg =3D 0x57c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x57c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "nss_cc_uniphy_port1_rx_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &nss_cc_port1_rx_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_uniphy_port1_tx_clk =3D { + .halt_reg =3D 0x580, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x580, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "nss_cc_uniphy_port1_tx_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &nss_cc_port1_tx_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_uniphy_port2_rx_clk =3D { + .halt_reg =3D 0x584, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x584, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "nss_cc_uniphy_port2_rx_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &nss_cc_port2_rx_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_uniphy_port2_tx_clk =3D { + .halt_reg =3D 0x588, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x588, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "nss_cc_uniphy_port2_tx_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &nss_cc_port2_tx_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_uniphy_port3_rx_clk =3D { + .halt_reg =3D 0x58c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x58c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "nss_cc_uniphy_port3_rx_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &nss_cc_port3_rx_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_uniphy_port3_tx_clk =3D { + .halt_reg =3D 0x590, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x590, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "nss_cc_uniphy_port3_tx_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &nss_cc_port3_tx_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_xgmac0_ptp_ref_clk =3D { + .halt_reg =3D 0x448, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x448, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "nss_cc_xgmac0_ptp_ref_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &nss_cc_xgmac0_ptp_ref_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_xgmac1_ptp_ref_clk =3D { + .halt_reg =3D 0x44c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x44c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "nss_cc_xgmac1_ptp_ref_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &nss_cc_xgmac1_ptp_ref_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_xgmac2_ptp_ref_clk =3D { + .halt_reg =3D 0x450, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x450, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "nss_cc_xgmac2_ptp_ref_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &nss_cc_xgmac2_ptp_ref_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_regmap *nss_cc_ipq5424_clocks[] =3D { + [NSS_CC_CE_APB_CLK] =3D &nss_cc_ce_apb_clk.clkr, + [NSS_CC_CE_AXI_CLK] =3D &nss_cc_ce_axi_clk.clkr, + [NSS_CC_CE_CLK_SRC] =3D &nss_cc_ce_clk_src.clkr, + [NSS_CC_CFG_CLK_SRC] =3D &nss_cc_cfg_clk_src.clkr, + [NSS_CC_DEBUG_CLK] =3D &nss_cc_debug_clk.clkr, + [NSS_CC_EIP_BFDCD_CLK_SRC] =3D &nss_cc_eip_bfdcd_clk_src.clkr, + [NSS_CC_EIP_CLK] =3D &nss_cc_eip_clk.clkr, + [NSS_CC_NSS_CSR_CLK] =3D &nss_cc_nss_csr_clk.clkr, + [NSS_CC_NSSNOC_CE_APB_CLK] =3D &nss_cc_nssnoc_ce_apb_clk.clkr, + [NSS_CC_NSSNOC_CE_AXI_CLK] =3D &nss_cc_nssnoc_ce_axi_clk.clkr, + [NSS_CC_NSSNOC_EIP_CLK] =3D &nss_cc_nssnoc_eip_clk.clkr, + [NSS_CC_NSSNOC_NSS_CSR_CLK] =3D &nss_cc_nssnoc_nss_csr_clk.clkr, + [NSS_CC_NSSNOC_PPE_CFG_CLK] =3D &nss_cc_nssnoc_ppe_cfg_clk.clkr, + [NSS_CC_NSSNOC_PPE_CLK] =3D &nss_cc_nssnoc_ppe_clk.clkr, + [NSS_CC_PORT1_MAC_CLK] =3D &nss_cc_port1_mac_clk.clkr, + [NSS_CC_PORT1_RX_CLK] =3D &nss_cc_port1_rx_clk.clkr, + [NSS_CC_PORT1_RX_CLK_SRC] =3D &nss_cc_port1_rx_clk_src.clkr, + [NSS_CC_PORT1_RX_DIV_CLK_SRC] =3D &nss_cc_port1_rx_div_clk_src.clkr, + [NSS_CC_PORT1_TX_CLK] =3D &nss_cc_port1_tx_clk.clkr, + [NSS_CC_PORT1_TX_CLK_SRC] =3D &nss_cc_port1_tx_clk_src.clkr, + [NSS_CC_PORT1_TX_DIV_CLK_SRC] =3D &nss_cc_port1_tx_div_clk_src.clkr, + [NSS_CC_PORT2_MAC_CLK] =3D &nss_cc_port2_mac_clk.clkr, + [NSS_CC_PORT2_RX_CLK] =3D &nss_cc_port2_rx_clk.clkr, + [NSS_CC_PORT2_RX_CLK_SRC] =3D &nss_cc_port2_rx_clk_src.clkr, + [NSS_CC_PORT2_RX_DIV_CLK_SRC] =3D &nss_cc_port2_rx_div_clk_src.clkr, + [NSS_CC_PORT2_TX_CLK] =3D &nss_cc_port2_tx_clk.clkr, + [NSS_CC_PORT2_TX_CLK_SRC] =3D &nss_cc_port2_tx_clk_src.clkr, + [NSS_CC_PORT2_TX_DIV_CLK_SRC] =3D &nss_cc_port2_tx_div_clk_src.clkr, + [NSS_CC_PORT3_MAC_CLK] =3D &nss_cc_port3_mac_clk.clkr, + [NSS_CC_PORT3_RX_CLK] =3D &nss_cc_port3_rx_clk.clkr, + [NSS_CC_PORT3_RX_CLK_SRC] =3D &nss_cc_port3_rx_clk_src.clkr, + [NSS_CC_PORT3_RX_DIV_CLK_SRC] =3D &nss_cc_port3_rx_div_clk_src.clkr, + [NSS_CC_PORT3_TX_CLK] =3D &nss_cc_port3_tx_clk.clkr, + [NSS_CC_PORT3_TX_CLK_SRC] =3D &nss_cc_port3_tx_clk_src.clkr, + [NSS_CC_PORT3_TX_DIV_CLK_SRC] =3D &nss_cc_port3_tx_div_clk_src.clkr, + [NSS_CC_PPE_CLK_SRC] =3D &nss_cc_ppe_clk_src.clkr, + [NSS_CC_PPE_EDMA_CFG_CLK] =3D &nss_cc_ppe_edma_cfg_clk.clkr, + [NSS_CC_PPE_EDMA_CLK] =3D &nss_cc_ppe_edma_clk.clkr, + [NSS_CC_PPE_SWITCH_BTQ_CLK] =3D &nss_cc_ppe_switch_btq_clk.clkr, + [NSS_CC_PPE_SWITCH_CFG_CLK] =3D &nss_cc_ppe_switch_cfg_clk.clkr, + [NSS_CC_PPE_SWITCH_CLK] =3D &nss_cc_ppe_switch_clk.clkr, + [NSS_CC_PPE_SWITCH_IPE_CLK] =3D &nss_cc_ppe_switch_ipe_clk.clkr, + [NSS_CC_UNIPHY_PORT1_RX_CLK] =3D &nss_cc_uniphy_port1_rx_clk.clkr, + [NSS_CC_UNIPHY_PORT1_TX_CLK] =3D &nss_cc_uniphy_port1_tx_clk.clkr, + [NSS_CC_UNIPHY_PORT2_RX_CLK] =3D &nss_cc_uniphy_port2_rx_clk.clkr, + [NSS_CC_UNIPHY_PORT2_TX_CLK] =3D &nss_cc_uniphy_port2_tx_clk.clkr, + [NSS_CC_UNIPHY_PORT3_RX_CLK] =3D &nss_cc_uniphy_port3_rx_clk.clkr, + [NSS_CC_UNIPHY_PORT3_TX_CLK] =3D &nss_cc_uniphy_port3_tx_clk.clkr, + [NSS_CC_XGMAC0_PTP_REF_CLK] =3D &nss_cc_xgmac0_ptp_ref_clk.clkr, + [NSS_CC_XGMAC0_PTP_REF_DIV_CLK_SRC] =3D &nss_cc_xgmac0_ptp_ref_div_clk_sr= c.clkr, + [NSS_CC_XGMAC1_PTP_REF_CLK] =3D &nss_cc_xgmac1_ptp_ref_clk.clkr, + [NSS_CC_XGMAC1_PTP_REF_DIV_CLK_SRC] =3D &nss_cc_xgmac1_ptp_ref_div_clk_sr= c.clkr, + [NSS_CC_XGMAC2_PTP_REF_CLK] =3D &nss_cc_xgmac2_ptp_ref_clk.clkr, + [NSS_CC_XGMAC2_PTP_REF_DIV_CLK_SRC] =3D &nss_cc_xgmac2_ptp_ref_div_clk_sr= c.clkr, +}; + +static const struct qcom_reset_map nss_cc_ipq5424_resets[] =3D { + [NSS_CC_CE_APB_CLK_ARES] =3D { 0x5e8, 2 }, + [NSS_CC_CE_AXI_CLK_ARES] =3D { 0x5ec, 2 }, + [NSS_CC_DEBUG_CLK_ARES] =3D { 0x70c, 2 }, + [NSS_CC_EIP_CLK_ARES] =3D { 0x658, 2 }, + [NSS_CC_NSS_CSR_CLK_ARES] =3D { 0x6b0, 2 }, + [NSS_CC_NSSNOC_CE_APB_CLK_ARES] =3D { 0x5f4, 2 }, + [NSS_CC_NSSNOC_CE_AXI_CLK_ARES] =3D { 0x5f8, 2 }, + [NSS_CC_NSSNOC_EIP_CLK_ARES] =3D { 0x660, 2 }, + [NSS_CC_NSSNOC_NSS_CSR_CLK_ARES] =3D { 0x6b4, 2 }, + [NSS_CC_NSSNOC_PPE_CLK_ARES] =3D { 0x440, 2 }, + [NSS_CC_NSSNOC_PPE_CFG_CLK_ARES] =3D { 0x444, 2 }, + [NSS_CC_PORT1_MAC_CLK_ARES] =3D { 0x428, 2 }, + [NSS_CC_PORT1_RX_CLK_ARES] =3D { 0x4fc, 2 }, + [NSS_CC_PORT1_TX_CLK_ARES] =3D { 0x504, 2 }, + [NSS_CC_PORT2_MAC_CLK_ARES] =3D { 0x430, 2 }, + [NSS_CC_PORT2_RX_CLK_ARES] =3D { 0x50c, 2 }, + [NSS_CC_PORT2_TX_CLK_ARES] =3D { 0x514, 2 }, + [NSS_CC_PORT3_MAC_CLK_ARES] =3D { 0x438, 2 }, + [NSS_CC_PORT3_RX_CLK_ARES] =3D { 0x51c, 2 }, + [NSS_CC_PORT3_TX_CLK_ARES] =3D { 0x524, 2 }, + [NSS_CC_PPE_BCR] =3D { 0x3e8 }, + [NSS_CC_PPE_EDMA_CLK_ARES] =3D { 0x41c, 2 }, + [NSS_CC_PPE_EDMA_CFG_CLK_ARES] =3D { 0x424, 2 }, + [NSS_CC_PPE_SWITCH_BTQ_CLK_ARES] =3D { 0x408, 2 }, + [NSS_CC_PPE_SWITCH_CLK_ARES] =3D { 0x410, 2 }, + [NSS_CC_PPE_SWITCH_CFG_CLK_ARES] =3D { 0x418, 2 }, + [NSS_CC_PPE_SWITCH_IPE_CLK_ARES] =3D { 0x400, 2 }, + [NSS_CC_UNIPHY_PORT1_RX_CLK_ARES] =3D { 0x57c, 2 }, + [NSS_CC_UNIPHY_PORT1_TX_CLK_ARES] =3D { 0x580, 2 }, + [NSS_CC_UNIPHY_PORT2_RX_CLK_ARES] =3D { 0x584, 2 }, + [NSS_CC_UNIPHY_PORT2_TX_CLK_ARES] =3D { 0x588, 2 }, + [NSS_CC_UNIPHY_PORT3_RX_CLK_ARES] =3D { 0x58c, 2 }, + [NSS_CC_UNIPHY_PORT3_TX_CLK_ARES] =3D { 0x590, 2 }, + [NSS_CC_XGMAC0_PTP_REF_CLK_ARES] =3D { 0x448, 2 }, + [NSS_CC_XGMAC1_PTP_REF_CLK_ARES] =3D { 0x44c, 2 }, + [NSS_CC_XGMAC2_PTP_REF_CLK_ARES] =3D { 0x450, 2 }, +}; + +static const struct regmap_config nss_cc_ipq5424_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x800, + .fast_io =3D true, +}; + +static const struct qcom_icc_hws_data icc_ipq5424_nss_hws[] =3D { + { MASTER_NSSNOC_PPE, SLAVE_NSSNOC_PPE, NSS_CC_NSSNOC_PPE_CLK }, + { MASTER_NSSNOC_PPE_CFG, SLAVE_NSSNOC_PPE_CFG, NSS_CC_NSSNOC_PPE_CFG_CLK = }, + { MASTER_NSSNOC_NSS_CSR, SLAVE_NSSNOC_NSS_CSR, NSS_CC_NSSNOC_NSS_CSR_CLK = }, + { MASTER_NSSNOC_CE_AXI, SLAVE_NSSNOC_CE_AXI, NSS_CC_NSSNOC_CE_AXI_CLK}, + { MASTER_NSSNOC_CE_APB, SLAVE_NSSNOC_CE_APB, NSS_CC_NSSNOC_CE_APB_CLK}, + { MASTER_NSSNOC_EIP, SLAVE_NSSNOC_EIP, NSS_CC_NSSNOC_EIP_CLK}, +}; + +#define IPQ_NSSCC_ID (5424 * 2) /* some unique value */ + +static const struct qcom_cc_desc nss_cc_ipq5424_desc =3D { + .config =3D &nss_cc_ipq5424_regmap_config, + .clks =3D nss_cc_ipq5424_clocks, + .num_clks =3D ARRAY_SIZE(nss_cc_ipq5424_clocks), + .resets =3D nss_cc_ipq5424_resets, + .num_resets =3D ARRAY_SIZE(nss_cc_ipq5424_resets), + .icc_hws =3D icc_ipq5424_nss_hws, + .num_icc_hws =3D ARRAY_SIZE(icc_ipq5424_nss_hws), + .icc_first_node_id =3D IPQ_NSSCC_ID, +}; + +static const struct dev_pm_ops nss_cc_ipq5424_pm_ops =3D { + SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + +static const struct of_device_id nss_cc_ipq5424_match_table[] =3D { + { .compatible =3D "qcom,ipq5424-nsscc" }, + { } +}; +MODULE_DEVICE_TABLE(of, nss_cc_ipq5424_match_table); + +static int nss_cc_ipq5424_probe(struct platform_device *pdev) +{ + int ret; + + ret =3D devm_pm_runtime_enable(&pdev->dev); + if (ret) + return dev_err_probe(&pdev->dev, ret, "Fail to enable runtime PM\n"); + + ret =3D devm_pm_clk_create(&pdev->dev); + if (ret) + return dev_err_probe(&pdev->dev, ret, "Fail to create PM clock\n"); + + ret =3D pm_clk_add(&pdev->dev, "bus"); + if (ret) + return dev_err_probe(&pdev->dev, ret, "Fail to add bus clock\n"); + + ret =3D pm_runtime_resume_and_get(&pdev->dev); + if (ret) + return dev_err_probe(&pdev->dev, ret, "Fail to resume\n"); + + ret =3D qcom_cc_probe(pdev, &nss_cc_ipq5424_desc); + pm_runtime_put(&pdev->dev); + + return ret; +} + +static struct platform_driver nss_cc_ipq5424_driver =3D { + .probe =3D nss_cc_ipq5424_probe, + .driver =3D { + .name =3D "qcom,ipq5424-nsscc", + .of_match_table =3D nss_cc_ipq5424_match_table, + .pm =3D &nss_cc_ipq5424_pm_ops, + .sync_state =3D icc_sync_state, + }, +}; +module_platform_driver(nss_cc_ipq5424_driver); + +MODULE_DESCRIPTION("Qualcomm Technologies, Inc. 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Signed-off-by: Luo Jie --- arch/arm64/boot/dts/qcom/ipq5424.dtsi | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qc= om/ipq5424.dtsi index 2eea8a078595..7248f6f07705 100644 --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi @@ -730,6 +730,36 @@ frame@f42d000 { }; }; =20 + clock-controller@39b00000 { + compatible =3D "qcom,ipq5424-nsscc"; + reg =3D <0 0x39b00000 0 0x800>; + clocks =3D <&cmn_pll IPQ5424_XO_24MHZ_CLK>, + <&cmn_pll IPQ5424_NSS_300MHZ_CLK>, + <&cmn_pll IPQ5424_PPE_375MHZ_CLK>, + <&gcc GPLL0_OUT_AUX>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <&gcc GCC_NSSCC_CLK>; + clock-names =3D "xo", + "nss_300", + "ppe_375", + "gpll0_out", + "uniphy0_rx", + "uniphy0_tx", + "uniphy1_rx", + "uniphy1_tx", + "uniphy2_rx", + "uniphy2_tx", + "bus"; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #interconnect-cells =3D <1>; + }; + pcie3: pcie@40000000 { compatible =3D "qcom,pcie-ipq5424", "qcom,pcie-ipq9574"; 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Signed-off-by: Luo Jie --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 897fc686e6a9..f4e4a6d95de4 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1363,6 +1363,7 @@ CONFIG_IPQ_GCC_5424=3Dy CONFIG_IPQ_GCC_6018=3Dy CONFIG_IPQ_GCC_8074=3Dy CONFIG_IPQ_GCC_9574=3Dy +CONFIG_IPQ_NSSCC_5424=3Dm CONFIG_IPQ_NSSCC_9574=3Dm CONFIG_MSM_GCC_8916=3Dy CONFIG_MSM_MMCC_8994=3Dm --=20 2.34.1