From nobody Thu Oct 2 21:05:26 2025 Received: from relay5-d.mail.gandi.net (relay5-d.mail.gandi.net [217.70.183.197]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 491D72E4243; Tue, 17 Jun 2025 12:12:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.197 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750162348; cv=none; b=BjvZ7fx0v1a2qu16QNWBFpoVK6e0xtu9iV0RAQY2wzzJ2c3EZ8yHhPQPM22Uf3ppPCST0kjpsXnRF68b+YILgF4JGQUprgsRiTuqsiXP3V8yPYHKbLnh71dOUUWCGDpN0yF2D/7/6rmHyTFunXcgxz2v0ZM/p5p9N71ItLAmGa0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750162348; c=relaxed/simple; bh=Ktc3xxYXhnRG0Rnso71RGDXd3fiZ42jyI/Gy94OBfRE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=GMUpQ4pQekfrkCTDO2Zyodn9RBbRnQTjVyKL7D63ync0Blgl4s4dbbIYwym5d5e65ii20n8e2CMYUg0zUg2qh0d/2upmiqIT7YqWdsxmglUE6wm7a6YwVJipzq0++ZKUvlPcn2FNEQA/MxkEE4RLVwbmpVw8Le1ijAIWyCPHm9M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=V197FZFy; arc=none smtp.client-ip=217.70.183.197 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="V197FZFy" Received: by mail.gandi.net (Postfix) with ESMTPSA id 941F84330E; Tue, 17 Jun 2025 12:12:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1750162337; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=gKchl/gqrxYqm9EjAM8es6ran3MYFcPpOU3PjiegdmY=; b=V197FZFy3iIABlRa+SP8g4qOE68/WcZFBJFYvANXHgdwUj97pprskxJr2vJSQNc5HFRYPe LegCw14rU312nz41o/OwvjbS6UkxWvKzPbsuVG/gCAHk9sgZG2ajll4tXvCllgIcogII33 JSUTcdThMioyEzgGzlnLTIv0sYoKmdKubP62RZ7GRuSZVJm8OYKRayQvah+c/Zg8LbLPG4 Iy9SLwjy8+YfCDwEmDuf0V+My/m563SX4nNF3tvcQTAr/jhGkMI0xDSYbbhx8IcgavXECT +CZDvojE9ITLAat4LPRroexT7xcGH8qzx8qHikn8mrgolh6r2Jz4Ezwp446z8w== From: Kory Maincent Date: Tue, 17 Jun 2025 14:12:02 +0200 Subject: [PATCH net-next v14 03/13] net: pse-pd: tps23881: Add support for PSE events and interrupts Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250617-feature_poe_port_prio-v14-3-78a1a645e2ee@bootlin.com> References: <20250617-feature_poe_port_prio-v14-0-78a1a645e2ee@bootlin.com> In-Reply-To: <20250617-feature_poe_port_prio-v14-0-78a1a645e2ee@bootlin.com> To: Andrew Lunn , Oleksij Rempel , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Jonathan Corbet , Donald Hunter , Rob Herring , Andrew Lunn , Simon Horman , Heiner Kallweit , Russell King , Krzysztof Kozlowski , Conor Dooley Cc: Liam Girdwood , Mark Brown , Thomas Petazzoni , netdev@vger.kernel.org, linux-doc@vger.kernel.org, Kyle Swenson , Dent Project , kernel@pengutronix.de, Maxime Chevallier , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, "Kory Maincent (Dent Project)" X-Mailer: b4 0.15-dev-8cb71 X-GND-State: clean X-GND-Score: -100 X-GND-Cause: gggruggvucftvghtrhhoucdtuddrgeeffedrtddvgddugecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfitefpfffkpdcuggftfghnshhusghstghrihgsvgenuceurghilhhouhhtmecufedtudenucesvcftvggtihhpihgvnhhtshculddquddttddmnecujfgurhephfffufggtgfgkfhfjgfvvefosehtjeertdertdejnecuhfhrohhmpefmohhrhicuofgrihhntggvnhhtuceokhhorhihrdhmrghinhgtvghnthessghoohhtlhhinhdrtghomheqnecuggftrfgrthhtvghrnhepvefgvdfgkeetgfefgfegkedugffghfdtffeftdeuteehjedtvdelvddvleehtdevnecukfhppeeltddrkeelrdduieefrdduvdejnecuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehinhgvthepledtrdekledrudeifedruddvjedphhgvlhhopegluddvjedrtddruddrudgnpdhmrghilhhfrhhomhepkhhorhihrdhmrghinhgtvghnthessghoohhtlhhinhdrtghomhdpnhgspghrtghpthhtohepvdejpdhrtghpthhtohepuggrvhgvmhesuggrvhgvmhhlohhfthdrnhgvthdprhgtphhtthhopehkohhrhidrmhgrihhntggvnhhtsegsohhothhlihhnrdgtohhmpdhrtghpthhtohepmhgrgihimhgvrdgthhgvvhgrlhhlihgvrhessghoohhtlhhinhdrtghomhdprhgtphhtthhopehprggsvghnihesrhgvughhrghtrdgtohhmpdhrtghpthhtoheptghonhhorhdoughtsehkvghrnhgvlhdrohhrghdpr hgtphhtthhopehkuhgsrgeskhgvrhhnvghlrdhorhhgpdhrtghpthhtoheplhhinhhugidqughotgesvhhgvghrrdhkvghrnhgvlhdrohhrghdprhgtphhtthhopehkhihlvgdrshifvghnshhonhesvghsthdrthgvtghh X-GND-Sasl: kory.maincent@bootlin.com From: Kory Maincent (Dent Project) Add support for PSE event reporting through interrupts. Set up the newly introduced devm_pse_irq_helper helper to register the interrupt. Events are reported for over-current and over-temperature conditions. Signed-off-by: Kory Maincent (Dent Project) Reviewed-by: Oleksij Rempel --- Change in v11: - Remove a potential infinite loop spotted by llm in tps23881_irq_handler. Change in v7: - Add a max irq retry limit to avoid infinite loop in the interrupt handler. Change in v4: - Small rename of a function. Change in v3: - Loop over interruption register to be sure the interruption pin is freed before exiting the interrupt handler function. - Add exist variable to not report event for undescribed PIs. - Used helpers to convert the chan number to the PI port number. Change in v2: - Remove support for OSS pin and TPC23881 specific port priority management --- drivers/net/pse-pd/tps23881.c | 189 ++++++++++++++++++++++++++++++++++++++= +++- 1 file changed, 187 insertions(+), 2 deletions(-) diff --git a/drivers/net/pse-pd/tps23881.c b/drivers/net/pse-pd/tps23881.c index 5e9dda2c0eac..7a9a5dbe0cb1 100644 --- a/drivers/net/pse-pd/tps23881.c +++ b/drivers/net/pse-pd/tps23881.c @@ -16,7 +16,15 @@ #include =20 #define TPS23881_MAX_CHANS 8 - +#define TPS23881_MAX_IRQ_RETRIES 10 + +#define TPS23881_REG_IT 0x0 +#define TPS23881_REG_IT_MASK 0x1 +#define TPS23881_REG_IT_IFAULT BIT(5) +#define TPS23881_REG_IT_SUPF BIT(7) +#define TPS23881_REG_FAULT 0x7 +#define TPS23881_REG_SUPF_EVENT 0xb +#define TPS23881_REG_TSD BIT(7) #define TPS23881_REG_PW_STATUS 0x10 #define TPS23881_REG_OP_MODE 0x12 #define TPS23881_OP_MODE_SEMIAUTO 0xaaaa @@ -24,6 +32,7 @@ #define TPS23881_REG_DET_CLA_EN 0x14 #define TPS23881_REG_GEN_MASK 0x17 #define TPS23881_REG_NBITACC BIT(5) +#define TPS23881_REG_INTEN BIT(7) #define TPS23881_REG_PW_EN 0x19 #define TPS23881_REG_2PAIR_POL1 0x1e #define TPS23881_REG_PORT_MAP 0x26 @@ -51,6 +60,7 @@ struct tps23881_port_desc { u8 chan[2]; bool is_4p; int pw_pol; + bool exist; }; =20 struct tps23881_priv { @@ -782,8 +792,10 @@ tps23881_write_port_matrix(struct tps23881_priv *priv, hw_chan =3D port_matrix[i].hw_chan[0] % 4; =20 /* Set software port matrix for existing ports */ - if (port_matrix[i].exist) + if (port_matrix[i].exist) { priv->port[pi_id].chan[0] =3D lgcl_chan; + priv->port[pi_id].exist =3D true; + } =20 /* Initialize power policy internal value */ priv->port[pi_id].pw_pol =3D -1; @@ -1017,6 +1029,173 @@ static int tps23881_flash_sram_fw(struct i2c_client= *client) return 0; } =20 +/* Convert interrupt events to 0xff to be aligned with the chan + * number. + */ +static u8 tps23881_irq_export_chans_helper(u16 reg_val, u8 field_offset) +{ + u8 val; + + val =3D (reg_val >> (4 + field_offset) & 0xf0) | + (reg_val >> field_offset & 0x0f); + + return val; +} + +/* Convert chan number to port number */ +static void tps23881_set_notifs_helper(struct tps23881_priv *priv, + u8 chans, + unsigned long *notifs, + unsigned long *notifs_mask, + enum ethtool_pse_event event) +{ + u8 chan; + int i; + + if (!chans) + return; + + for (i =3D 0; i < TPS23881_MAX_CHANS; i++) { + if (!priv->port[i].exist) + continue; + /* No need to look at the 2nd channel in case of PoE4 as + * both registers are set. + */ + chan =3D priv->port[i].chan[0]; + + if (BIT(chan) & chans) { + *notifs_mask |=3D BIT(i); + notifs[i] |=3D event; + } + } +} + +static void tps23881_irq_event_over_temp(struct tps23881_priv *priv, + u16 reg_val, + unsigned long *notifs, + unsigned long *notifs_mask) +{ + int i; + + if (reg_val & TPS23881_REG_TSD) { + for (i =3D 0; i < TPS23881_MAX_CHANS; i++) { + if (!priv->port[i].exist) + continue; + + *notifs_mask |=3D BIT(i); + notifs[i] |=3D ETHTOOL_PSE_EVENT_OVER_TEMP; + } + } +} + +static void tps23881_irq_event_over_current(struct tps23881_priv *priv, + u16 reg_val, + unsigned long *notifs, + unsigned long *notifs_mask) +{ + u8 chans; + + chans =3D tps23881_irq_export_chans_helper(reg_val, 0); + if (chans) + tps23881_set_notifs_helper(priv, chans, notifs, notifs_mask, + ETHTOOL_PSE_EVENT_OVER_CURRENT); +} + +static int tps23881_irq_event_handler(struct tps23881_priv *priv, u16 reg, + unsigned long *notifs, + unsigned long *notifs_mask) +{ + struct i2c_client *client =3D priv->client; + int ret; + + /* The Supply event bit is repeated twice so we only need to read + * the one from the first byte. + */ + if (reg & TPS23881_REG_IT_SUPF) { + ret =3D i2c_smbus_read_word_data(client, TPS23881_REG_SUPF_EVENT); + if (ret < 0) + return ret; + tps23881_irq_event_over_temp(priv, ret, notifs, notifs_mask); + } + + if (reg & (TPS23881_REG_IT_IFAULT | TPS23881_REG_IT_IFAULT << 8)) { + ret =3D i2c_smbus_read_word_data(client, TPS23881_REG_FAULT); + if (ret < 0) + return ret; + tps23881_irq_event_over_current(priv, ret, notifs, notifs_mask); + } + + return 0; +} + +static int tps23881_irq_handler(int irq, struct pse_controller_dev *pcdev, + unsigned long *notifs, + unsigned long *notifs_mask) +{ + struct tps23881_priv *priv =3D to_tps23881_priv(pcdev); + struct i2c_client *client =3D priv->client; + int ret, it_mask, retry; + + /* Get interruption mask */ + ret =3D i2c_smbus_read_word_data(client, TPS23881_REG_IT_MASK); + if (ret < 0) + return ret; + it_mask =3D ret; + + /* Read interrupt register until it frees the interruption pin. */ + retry =3D 0; + while (true) { + if (retry > TPS23881_MAX_IRQ_RETRIES) { + dev_err(&client->dev, "interrupt never freed"); + return -ETIMEDOUT; + } + + ret =3D i2c_smbus_read_word_data(client, TPS23881_REG_IT); + if (ret < 0) + return ret; + + /* No more relevant interruption */ + if (!(ret & it_mask)) + return 0; + + ret =3D tps23881_irq_event_handler(priv, (u16)ret, notifs, + notifs_mask); + if (ret) + return ret; + + retry++; + } + return 0; +} + +static int tps23881_setup_irq(struct tps23881_priv *priv, int irq) +{ + struct i2c_client *client =3D priv->client; + struct pse_irq_desc irq_desc =3D { + .name =3D "tps23881-irq", + .map_event =3D tps23881_irq_handler, + }; + int ret; + u16 val; + + val =3D TPS23881_REG_IT_IFAULT | TPS23881_REG_IT_SUPF; + val |=3D val << 8; + ret =3D i2c_smbus_write_word_data(client, TPS23881_REG_IT_MASK, val); + if (ret) + return ret; + + ret =3D i2c_smbus_read_word_data(client, TPS23881_REG_GEN_MASK); + if (ret < 0) + return ret; + + val =3D (u16)(ret | TPS23881_REG_INTEN | TPS23881_REG_INTEN << 8); + ret =3D i2c_smbus_write_word_data(client, TPS23881_REG_GEN_MASK, val); + if (ret < 0) + return ret; + + return devm_pse_irq_helper(&priv->pcdev, irq, 0, &irq_desc); +} + static int tps23881_i2c_probe(struct i2c_client *client) { struct device *dev =3D &client->dev; @@ -1097,6 +1276,12 @@ static int tps23881_i2c_probe(struct i2c_client *cli= ent) "failed to register PSE controller\n"); } =20 + if (client->irq) { + ret =3D tps23881_setup_irq(priv, client->irq); + if (ret) + return ret; + } + return ret; } =20 --=20 2.43.0