From nobody Thu Oct 9 20:22:54 2025 Received: from out-180.mta1.migadu.com (out-180.mta1.migadu.com [95.215.58.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7BC9F223DD5 for ; Mon, 16 Jun 2025 22:01:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.180 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750111288; cv=none; b=m5S1oeiGJp2aqQgO6UoLKWeEJJkwRiWiuZwdHAY5r7YG+ct4hEHGNLBMnEleUbFK0NbxMn1w/UxifjxDe3NRY1fbAOuWownAUdpfJJ/4hPT+p2qOIaSiCNVFQktg2Uo63Wlui6LNTQabOI8QfQQH/HG+EGwSJ6qJjztSs2RXa7Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750111288; c=relaxed/simple; bh=GDARaksPLKEKseFYGSFlXG8ZZvfvQwPmIQyC3rwaexU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=eJW+0AET//8whJl49vy3eebz5sWFfK3PZCWNlsn3rjMy6tQ55PZh5XoIgXzN90aa3X/N9sEOi3NELY1movMh9v5ip0c8dnouo0x+JPvqJkpNMYbRqBw02j+vzLsoxqeoHSSOvHcGyrwBWnwpkW+15np3WmgmhdJ/RvQ8Fs2BSy4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=fRpI7zM8; arc=none smtp.client-ip=95.215.58.180 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="fRpI7zM8" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1750111284; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=U8s2DHgn3w9rCn5wed99fTlnLPjizNqzhROnC2hjDTA=; b=fRpI7zM8EJ3lvBmGn2ZK6cQPnRoS5fEUqpX4uEe/Q79CiQkoJ8ri/t072mO5lxXCYc/qbc 3KTVhRUQHgYXwCYzio47tXfi1X9NhHR5sreoEhqfjwuviauAq0QTq/k8y7nquFpMCUJpxW RNJwGK6tuqfrBzMKUy133m4n6EGrudc= From: Sean Anderson To: Mark Brown , Michal Simek , linux-spi@vger.kernel.org Cc: Jinjie Ruan , Miquel Raynal , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, David Lechner , Amit Kumar Mahapatra , Sean Anderson Subject: [PATCH v2 8/9] spi: zynqmp-gqspi: Support GPIO chip selects Date: Mon, 16 Jun 2025 18:00:53 -0400 Message-Id: <20250616220054.3968946-9-sean.anderson@linux.dev> In-Reply-To: <20250616220054.3968946-1-sean.anderson@linux.dev> References: <20250616220054.3968946-1-sean.anderson@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" GPIO chipselects use the traditional SPI API instead of the SPIMEM API. Implement it with transfer_one and set_cs (for non-GPIO chipselects). At the moment we only support half-duplex transfers, which is good enough to access SPI flashes. Signed-off-by: Sean Anderson --- Changes in v2: - Use ->buses instead of an upper/lower split drivers/spi/spi-zynqmp-gqspi.c | 93 ++++++++++++++++++++++++++++++---- 1 file changed, 84 insertions(+), 9 deletions(-) diff --git a/drivers/spi/spi-zynqmp-gqspi.c b/drivers/spi/spi-zynqmp-gqspi.c index b36159dbaff0..87d375fae653 100644 --- a/drivers/spi/spi-zynqmp-gqspi.c +++ b/drivers/spi/spi-zynqmp-gqspi.c @@ -499,6 +499,15 @@ static void zynqmp_qspi_chipselect(struct spi_device *= qspi, bool is_high) dev_err(xqspi->dev, "Chip select timed out\n"); } =20 +static void zynqmp_qspi_set_cs(struct spi_device *qspi, bool is_high) +{ + struct zynqmp_qspi *xqspi =3D spi_controller_get_devdata(qspi->controller= ); + + mutex_lock(&xqspi->op_lock); + zynqmp_qspi_chipselect(qspi, is_high); + mutex_unlock(&xqspi->op_lock); +} + /** * zynqmp_qspi_selectspimode - Selects SPI mode - x1 or x2 or x4. * @xqspi: xqspi is a pointer to the GQSPI instance @@ -1197,6 +1206,73 @@ static int zynqmp_qspi_exec_op(struct spi_mem *mem, return err; } =20 +static int zynqmp_qspi_transfer_one(struct spi_controller *ctlr, + struct spi_device *spi, + struct spi_transfer *transfer) +{ + struct zynqmp_qspi *xqspi =3D spi_controller_get_devdata(ctlr); + unsigned long timeout; + u32 genfifoentry; + u32 mask =3D 0; + int ret; + + dev_dbg(xqspi->dev, "xfer %u/%u %u\n", transfer->tx_nbits, + transfer->rx_nbits, transfer->len); + + if (transfer->tx_nbits && transfer->rx_nbits) + return -EOPNOTSUPP; + + guard(mutex)(&xqspi->op_lock); + zynqmp_qspi_config_op(xqspi, transfer->speed_hz, spi->mode); + if (spi_get_csgpiod(spi, 0)) { + xqspi->genfifobus =3D + FIELD_PREP(GQSPI_GENFIFO_BUS_MASK, spi->buses); + xqspi->genfifocs =3D 0; + } + genfifoentry =3D xqspi->genfifocs | xqspi->genfifobus; + + reinit_completion(&xqspi->data_completion); + if (transfer->tx_nbits) { + xqspi->txbuf =3D transfer->tx_buf; + xqspi->rxbuf =3D NULL; + xqspi->bytes_to_transfer =3D transfer->len; + xqspi->bytes_to_receive =3D 0; + zynqmp_qspi_write_op(xqspi, transfer->tx_nbits, genfifoentry); + mask =3D GQSPI_IER_TXEMPTY_MASK | GQSPI_IER_GENFIFOEMPTY_MASK | + GQSPI_IER_TXNOT_FULL_MASK; + timeout =3D zynqmp_qspi_timeout(xqspi, transfer->tx_nbits, + transfer->len); + } else { + xqspi->txbuf =3D NULL; + xqspi->rxbuf =3D transfer->rx_buf; + xqspi->bytes_to_transfer =3D 0; + xqspi->bytes_to_receive =3D transfer->len; + ret =3D zynqmp_qspi_read_op(xqspi, transfer->rx_nbits, + genfifoentry); + if (ret) + return ret; + + if (xqspi->mode !=3D GQSPI_MODE_DMA) + mask =3D GQSPI_IER_GENFIFOEMPTY_MASK | + GQSPI_IER_RXNEMPTY_MASK | GQSPI_IER_RXEMPTY_MASK; + timeout =3D zynqmp_qspi_timeout(xqspi, transfer->rx_nbits, + transfer->len); + } + + zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, + zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) | + GQSPI_CFG_START_GEN_FIFO_MASK); + if (mask) + zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST, mask); + else + zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_EN_OFST, + GQSPI_QSPIDMA_DST_I_EN_DONE_MASK); + + if (!wait_for_completion_timeout(&xqspi->data_completion, timeout)) + return -ETIMEDOUT; + return 0; +} + static const struct dev_pm_ops zynqmp_qspi_dev_pm_ops =3D { SET_RUNTIME_PM_OPS(zynqmp_runtime_suspend, zynqmp_runtime_resume, NULL) @@ -1316,27 +1392,26 @@ static int zynqmp_qspi_probe(struct platform_device= *pdev) if (ret) goto clk_dis_all; =20 + ctlr->max_native_cs =3D 2; ret =3D of_property_read_u32(np, "num-cs", &num_cs); - if (ret < 0) { + if (ret < 0) ctlr->num_chipselect =3D GQSPI_DEFAULT_NUM_CS; - } else if (num_cs > GQSPI_MAX_NUM_CS) { - ret =3D -EINVAL; - dev_err(&pdev->dev, "only %d chip selects are available\n", - GQSPI_MAX_NUM_CS); - goto clk_dis_all; - } else { + else ctlr->num_chipselect =3D num_cs; - } =20 ctlr->num_buses =3D 2; - ctlr->flags =3D SPI_CONTROLLER_DEFAULT_BUS_IS_CS; + ctlr->flags =3D SPI_CONTROLLER_DEFAULT_BUS_IS_CS | + SPI_CONTROLLER_HALF_DUPLEX; ctlr->bits_per_word_mask =3D SPI_BPW_MASK(8); ctlr->mem_ops =3D &zynqmp_qspi_mem_ops; ctlr->mem_caps =3D &zynqmp_qspi_mem_caps; ctlr->setup =3D zynqmp_qspi_setup_op; + ctlr->set_cs =3D zynqmp_qspi_set_cs; + ctlr->transfer_one =3D zynqmp_qspi_transfer_one; ctlr->bits_per_word_mask =3D SPI_BPW_MASK(8); ctlr->dev.of_node =3D np; ctlr->auto_runtime_pm =3D true; + ctlr->use_gpio_descriptors =3D true; =20 ret =3D devm_spi_register_controller(&pdev->dev, ctlr); if (ret) { --=20 2.35.1.1320.gc452695387.dirty