From nobody Thu Oct 9 20:22:54 2025 Received: from out-188.mta1.migadu.com (out-188.mta1.migadu.com [95.215.58.188]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E9DBB238152 for ; Mon, 16 Jun 2025 22:01:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.188 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750111287; cv=none; b=MoxyTaElIYOb35+KY/DFEmppCDV2xFHJdWREG16NNDvm/6hmehSdUI26jb2rN4gUPIa1jn98HTKHsA8OSHtxmkYQwhU2Gxrz5Dvdgd/rqeDpdhwX7teg1i1qMtDmNKf8VEdQZyaRToNf+D1OipbKuY8mm37LCuge9CU1usF0V5E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750111287; c=relaxed/simple; bh=Wraj1hZ3EBxKe2cyb3q1iqv3qisL2xc0bmwF6cli6Hk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=OdsyzUz4FoovDetyoiogaGNOchw9/KwNMi8E8ioLwRLNVcAomzMLrJQhPv6IjUakBjuiWyLMxrfqJ3gUlB2QSOjfseFLqQLe6kmzVnzEfRbD2RXJ5HhtfMm2lrpPcq5ybHJXRMfdBBO08xijS5MoqrVY95xRZ1Lc89MRqZvudSI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=vpEA3/2l; arc=none smtp.client-ip=95.215.58.188 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="vpEA3/2l" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1750111283; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=NGOH8Yvcz0WgyTH+Nb2rF8MG3xwZ18CiFbl2INC4Pwc=; b=vpEA3/2lKQLW1KlQy0fAkRGHmm41rLVtpUYTk/FtQEClVaZDGiw59+7LhF+lpXDM4UzepZ fb4cLEp2SSBV37UlS50QI9aUP5JoKCOYg8XHGzaXk3p8SXV1m7VcZ9qcay0zX7+/bT9NfA vwKxcXFL30SFCIuAsagUKLA+gFHt3mw= From: Sean Anderson To: Mark Brown , Michal Simek , linux-spi@vger.kernel.org Cc: Jinjie Ruan , Miquel Raynal , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, David Lechner , Amit Kumar Mahapatra , Sean Anderson Subject: [PATCH v2 7/9] spi: zynqmp-gqspi: Configure SPI mode dynamically Date: Mon, 16 Jun 2025 18:00:52 -0400 Message-Id: <20250616220054.3968946-8-sean.anderson@linux.dev> In-Reply-To: <20250616220054.3968946-1-sean.anderson@linux.dev> References: <20250616220054.3968946-1-sean.anderson@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" The SPI mode (phase/polarity) can change between spi_transfers. In preparation for transfer_one support, program the SPI mode on every operation instead of once during init. Signed-off-by: Sean Anderson --- (no changes since v1) drivers/spi/spi-zynqmp-gqspi.c | 43 +++++++++++++++++++++++----------- 1 file changed, 29 insertions(+), 14 deletions(-) diff --git a/drivers/spi/spi-zynqmp-gqspi.c b/drivers/spi/spi-zynqmp-gqspi.c index a17e77dc4e27..b36159dbaff0 100644 --- a/drivers/spi/spi-zynqmp-gqspi.c +++ b/drivers/spi/spi-zynqmp-gqspi.c @@ -184,7 +184,8 @@ struct qspi_platform_data { * @mode: Defines the mode in which QSPI is operating * @data_completion: completion structure * @op_lock: Operational lock - * @speed_hz: Current SPI bus clock speed in hz + * @speed_hz: Current SPI bus clock speed in hz + * @spi_mode: Current SPI bus mode * @has_tapdelay: Used for tapdelay register available in qspi */ struct zynqmp_qspi { @@ -207,6 +208,7 @@ struct zynqmp_qspi { struct completion data_completion; struct mutex op_lock; u32 speed_hz; + u32 spi_mode; bool has_tapdelay; }; =20 @@ -387,16 +389,11 @@ static void zynqmp_qspi_init_hw(struct zynqmp_qspi *x= qspi) config_reg |=3D GQSPI_CFG_WP_HOLD_MASK; /* Clear pre-scalar by default */ config_reg &=3D ~GQSPI_CFG_BAUD_RATE_DIV_MASK; - /* Set CPHA */ - if (xqspi->ctlr->mode_bits & SPI_CPHA) - config_reg |=3D GQSPI_CFG_CLK_PHA_MASK; - else - config_reg &=3D ~GQSPI_CFG_CLK_PHA_MASK; - /* Set CPOL */ - if (xqspi->ctlr->mode_bits & SPI_CPOL) - config_reg |=3D GQSPI_CFG_CLK_POL_MASK; - else - config_reg &=3D ~GQSPI_CFG_CLK_POL_MASK; + + /* Set default mode */ + xqspi->spi_mode =3D SPI_MODE_3; + config_reg |=3D GQSPI_CFG_CLK_PHA_MASK; + config_reg |=3D GQSPI_CFG_CLK_POL_MASK; =20 /* Set the clock frequency */ clk_rate =3D clk_get_rate(xqspi->refclk); @@ -535,6 +532,7 @@ static inline u32 zynqmp_qspi_selectspimode(struct zynq= mp_qspi *xqspi, * transfer * @xqspi: Pointer to the zynqmp_qspi structure * @req_speed_hz: Requested frequency + * @mode: Requested SPI mode * * Sets the operational mode of QSPI controller for the next QSPI transfer= and * sets the requested clock frequency. @@ -551,7 +549,8 @@ static inline u32 zynqmp_qspi_selectspimode(struct zynq= mp_qspi *xqspi, * by the QSPI controller the driver will set the highest or lowest * frequency supported by controller. */ -static int zynqmp_qspi_config_op(struct zynqmp_qspi *xqspi, u32 req_speed_= hz) +static int zynqmp_qspi_config_op(struct zynqmp_qspi *xqspi, u32 req_speed_= hz, + u32 mode) { ulong clk_rate; u32 config_reg, baud_rate_val =3D 0; @@ -577,7 +576,23 @@ static int zynqmp_qspi_config_op(struct zynqmp_qspi *x= qspi, u32 req_speed_hz) zynqmp_qspi_set_tapdelay(xqspi, baud_rate_val); } =20 - dev_dbg(xqspi->dev, "config speed %u\n", req_speed_hz); + mode &=3D SPI_MODE_X_MASK; + if (xqspi->spi_mode !=3D mode) { + xqspi->spi_mode =3D mode; + + config_reg =3D zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST); + if (mode & SPI_CPHA) + config_reg |=3D GQSPI_CFG_CLK_PHA_MASK; + else + config_reg &=3D ~GQSPI_CFG_CLK_PHA_MASK; + if (mode & SPI_CPOL) + config_reg |=3D GQSPI_CFG_CLK_POL_MASK; + else + config_reg &=3D ~GQSPI_CFG_CLK_POL_MASK; + zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg); + } + + dev_dbg(xqspi->dev, "config speed %u mode %x\n", req_speed_hz, mode); return 0; } =20 @@ -1050,7 +1065,7 @@ static int zynqmp_qspi_exec_op(struct spi_mem *mem, u64 opaddr; =20 mutex_lock(&xqspi->op_lock); - zynqmp_qspi_config_op(xqspi, op->max_freq); + zynqmp_qspi_config_op(xqspi, op->max_freq, mem->spi->mode); zynqmp_qspi_chipselect(mem->spi, false); genfifoentry |=3D xqspi->genfifocs; genfifoentry |=3D xqspi->genfifobus; --=20 2.35.1.1320.gc452695387.dirty