From nobody Thu Oct 9 20:22:55 2025 Received: from out-182.mta1.migadu.com (out-182.mta1.migadu.com [95.215.58.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6DBFB221F11 for ; Mon, 16 Jun 2025 22:01:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.182 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750111285; cv=none; b=gCJodsAEqEMU8MGy9FiCwdejetBm/yMuDNxFUzHHexIpad5V2h/ac8AuulHXaGqmW0kka7DUxJsbeJmExFoBX1Q/cLnj7/P6ehg5+tFOcYy5Bwj/x//dmooU+HYt29a+ScFQhEOaIeklMbGdBdiaAoCN421gkpWfG1Aecj9t2cI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750111285; c=relaxed/simple; bh=NcmTj5O4UnDJpKrXg8mlqcQXqW5kLOfOgZhvciV6zUo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=uhdAWSMSH0S3nn6QqYAHMRYdQ5hcntzTKnNTAFibScl6oc4veHg0xVs6L53LlvoEKjB5u+Z32mmuGTp45XegH6PpLRDT2vmg5XsmI+7vg80uj4bJlBNFWkXrLzjupydK1v400G9nHwbAJSm6Q5LZ82dSfLfEYrQW0wIVypL2Zvs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=udplqrxW; arc=none smtp.client-ip=95.215.58.182 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="udplqrxW" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1750111281; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=UpXv1zP1pu51TTfErAKypkJY3vjgrcKFdh3KjXTzhFA=; b=udplqrxWmGeRFbpu6YjHOGUPktFGJtRBM5UfUSsLYVTGVZ2Yt7dK+XIYp7GzFbUKRk447d nJ8irijhPldc1awyPuB+LHl3oEr9g9aOSJn+LM0DavL274LLBCCTUpZfacG1+O0+A3TrFl NjLIvzJbMesvV/uqBA2M7Ka98jjmCHQ= From: Sean Anderson To: Mark Brown , Michal Simek , linux-spi@vger.kernel.org Cc: Jinjie Ruan , Miquel Raynal , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, David Lechner , Amit Kumar Mahapatra , Sean Anderson Subject: [PATCH v2 6/9] spi: zynqmp-gqspi: Pass speed directly to config_op Date: Mon, 16 Jun 2025 18:00:51 -0400 Message-Id: <20250616220054.3968946-7-sean.anderson@linux.dev> In-Reply-To: <20250616220054.3968946-1-sean.anderson@linux.dev> References: <20250616220054.3968946-1-sean.anderson@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" In preparation for supporting transfer_one, which supplies the speed from the spi_transfer instead of the spi_device, convert config_op to take the speed directly. Signed-off-by: Sean Anderson --- (no changes since v1) drivers/spi/spi-zynqmp-gqspi.c | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/drivers/spi/spi-zynqmp-gqspi.c b/drivers/spi/spi-zynqmp-gqspi.c index add5eea12153..a17e77dc4e27 100644 --- a/drivers/spi/spi-zynqmp-gqspi.c +++ b/drivers/spi/spi-zynqmp-gqspi.c @@ -533,8 +533,8 @@ static inline u32 zynqmp_qspi_selectspimode(struct zynq= mp_qspi *xqspi, /** * zynqmp_qspi_config_op - Configure QSPI controller for specified * transfer - * @xqspi: Pointer to the zynqmp_qspi structure - * @op: The memory operation to execute + * @xqspi: Pointer to the zynqmp_qspi structure + * @req_speed_hz: Requested frequency * * Sets the operational mode of QSPI controller for the next QSPI transfer= and * sets the requested clock frequency. @@ -551,13 +551,10 @@ static inline u32 zynqmp_qspi_selectspimode(struct zy= nqmp_qspi *xqspi, * by the QSPI controller the driver will set the highest or lowest * frequency supported by controller. */ -static int zynqmp_qspi_config_op(struct zynqmp_qspi *xqspi, - const struct spi_mem_op *op) +static int zynqmp_qspi_config_op(struct zynqmp_qspi *xqspi, u32 req_speed_= hz) { ulong clk_rate; - u32 config_reg, req_speed_hz, baud_rate_val =3D 0; - - req_speed_hz =3D op->max_freq; + u32 config_reg, baud_rate_val =3D 0; =20 if (xqspi->speed_hz !=3D req_speed_hz) { xqspi->speed_hz =3D req_speed_hz; @@ -1053,7 +1050,7 @@ static int zynqmp_qspi_exec_op(struct spi_mem *mem, u64 opaddr; =20 mutex_lock(&xqspi->op_lock); - zynqmp_qspi_config_op(xqspi, op); + zynqmp_qspi_config_op(xqspi, op->max_freq); zynqmp_qspi_chipselect(mem->spi, false); genfifoentry |=3D xqspi->genfifocs; genfifoentry |=3D xqspi->genfifobus; --=20 2.35.1.1320.gc452695387.dirty