From nobody Thu Oct 9 16:37:47 2025 Received: from out-171.mta1.migadu.com (out-171.mta1.migadu.com [95.215.58.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E26DC19F42D for ; Mon, 16 Jun 2025 22:01:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750111275; cv=none; b=pz3hNtUglPT8+ogbtefa80nTAmVt0RS6z+XrB0ti2H3AA4ja4VItZr5x3F2VP64M4Mcc/MoW/HrZghB3jUtl0XQAJw52AZ42LggopSb3JWYGlFW10p9xR0/2KEWQt5JYAWeJgfapdj0cdZ1KbcGoYx1FcLQt63b05DyYLcaz80k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750111275; c=relaxed/simple; bh=SFLO0xOMn8PJY80uuJvTi/bHhgq8BmwsE8+5yzDsMRE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=nQPqeU3vF5ZvoAeX8/4UK8m7lKXRW9XJquMmmQl8WqnRjjhg+DFP65BW3JdijkMSGUP7f62NY/TlNnO2jl7PGAkwTRy/U3xkt2iuFPxUTMvwI1TnPFq2EWjx9e3S9Acd6AD7hscaOFBd8Dazg0AeEktiNUd0/Jm8zcfG1P59hSE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=UadQiczH; arc=none smtp.client-ip=95.215.58.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="UadQiczH" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1750111272; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=k02eg2nEnGNOVqzzGntSYPh+yjp3owIb+q67azvL4JA=; b=UadQiczHIeD6B2nrEfEl0KTczlznS2BpAm4IByPdlh/tvG58UEa+mIg6NA1S7Lc701VBxv 9aJRLszvcLyWiPz79MIql9Ggn/GzVrMhLou+zA/KGa5dIWESVTQRgAf7/1nO73SGVYPyHv AnUXRehC7n8USBTzD/K95i0cHdiLV48= From: Sean Anderson To: Mark Brown , Michal Simek , linux-spi@vger.kernel.org Cc: Jinjie Ruan , Miquel Raynal , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, David Lechner , Amit Kumar Mahapatra , Sean Anderson Subject: [PATCH v2 1/9] dt-bindings: spi: Add spi-buses property Date: Mon, 16 Jun 2025 18:00:46 -0400 Message-Id: <20250616220054.3968946-2-sean.anderson@linux.dev> In-Reply-To: <20250616220054.3968946-1-sean.anderson@linux.dev> References: <20250616220054.3968946-1-sean.anderson@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" From: David Lechner Add a spi-buses property to the spi-peripheral-props binding to allow specifying the SPI bus or buses that a peripheral is connected to in cases where the SPI controller has more than one physical SPI bus. Signed-off-by: David Lechner Signed-off-by: Sean Anderson --- Changes in v2: - New .../devicetree/bindings/spi/spi-peripheral-props.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yam= l b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml index 8fc17e16efb2..cfdb55071a08 100644 --- a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml +++ b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml @@ -89,6 +89,16 @@ properties: description: Delay, in microseconds, after a write transfer. =20 + spi-buses: + description: + Array of bus numbers that describes which SPI buses of the controlle= r are + connected to the peripheral. This only applies to peripherals connec= ted + to specialized SPI controllers that have multiple SPI buses on a sin= gle + controller. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + default: [0] + stacked-memories: description: Several SPI memories can be wired in stacked mode. This basically means that either a device features several chip --=20 2.35.1.1320.gc452695387.dirty From nobody Thu Oct 9 16:37:47 2025 Received: from out-179.mta1.migadu.com (out-179.mta1.migadu.com [95.215.58.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A63C420E01F; Mon, 16 Jun 2025 22:01:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.179 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750111278; cv=none; b=FUc+e2Af9DyW7dta2ukupmefEsLHHh+WQCWEFSofvKUUf/dYR+O5i+b6ozliQsPv6MaKkS+tFIRqR+s9258GE8TVvIWvkbxJVNAucPa0moQzE9ImlEoqlKMlIwKILPdgSpHWFpi60Wa6R1HvTJGlV6f+ppQVW+WmI1YsB4Y76Uo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750111278; c=relaxed/simple; bh=Vhfy//Tt2j7qdqBp2swhp7LRoCz7fTH1cTzQHky6pzE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=CsmkiUiIav5+91Iho7eH+Om1gqPO042+Ls5acO+jShZmJnEGbucW8t86WRI6TRaqrp19CDsIkB/poH+yT+ivLQ8AzRpHnGvuAz/AG+c2LSjxSCBHpqtLOydIQGse86xpY+GBmFAXtC/cOp5Q+P1mwFu+agelEUoEjU3uHyq++xI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=F91ClS5f; arc=none smtp.client-ip=95.215.58.179 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="F91ClS5f" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1750111273; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=DYNxKYy9tzRuJkdjCisZbvAuwLPriCoPPBBF8f3Xfak=; b=F91ClS5fDbY1agTH3+ZLkRlkBQZ4vz/bewBbT8pDW2tFKLX+Y9kaJNWbl5+/LuIdyC1lUV lIk4woGYrtDdmMW0/XhZ4A4XlBJ+fXUd/N2Gw7nB+NjzKOqa2n4U36ldOOO1ZA3587NDOl lk32sZWaPPtxaE824aC68ydUaZkfA9M= From: Sean Anderson To: Mark Brown , Michal Simek , linux-spi@vger.kernel.org Cc: Jinjie Ruan , Miquel Raynal , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, David Lechner , Amit Kumar Mahapatra , Sean Anderson , Conor Dooley , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH v2 2/9] dt-bindings: spi: zynqmp-qspi: Add example dual upper/lower bus Date: Mon, 16 Jun 2025 18:00:47 -0400 Message-Id: <20250616220054.3968946-3-sean.anderson@linux.dev> In-Reply-To: <20250616220054.3968946-1-sean.anderson@linux.dev> References: <20250616220054.3968946-1-sean.anderson@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" Add an example of the spi-buses property showcasing how to have devices on both the upper and lower buses. Signed-off-by: Sean Anderson --- Changes in v2: - New .../bindings/spi/spi-zynqmp-qspi.yaml | 22 ++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml b/D= ocumentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml index 02cf1314367b..c6a57fbb9dcf 100644 --- a/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml +++ b/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml @@ -69,7 +69,7 @@ examples: #address-cells =3D <2>; #size-cells =3D <2>; =20 - qspi: spi@ff0f0000 { + qspi: spi-controller@ff0f0000 { compatible =3D "xlnx,zynqmp-qspi-1.0"; clocks =3D <&zynqmp_clk 53>, <&zynqmp_clk 82>; clock-names =3D "ref_clk", "pclk"; @@ -77,5 +77,25 @@ examples: interrupt-parent =3D <&gic>; reg =3D <0x0 0xff0f0000 0x0 0x1000>, <0x0 0xc0000000 0x0 0x8000000>; + num-cs =3D <3>; + cs-gpios =3D <0>, <0>, <&gpio 5>; + + flash@0 { + reg =3D <0>; + spi-buses =3D <0>; + compatible =3D "jedec,spi-nor"; + }; + + flash@1 { + reg =3D <1>; + spi-buses =3D <1>; + compatible =3D "jedec,spi-nor"; + }; + + flash@2 { + reg =3D <2>; + spi-buses =3D <0>; + compatible =3D "jedec,spi-nor"; + }; }; }; --=20 2.35.1.1320.gc452695387.dirty From nobody Thu Oct 9 16:37:47 2025 Received: from out-183.mta1.migadu.com (out-183.mta1.migadu.com [95.215.58.183]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 14207225405 for ; Mon, 16 Jun 2025 22:01:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.183 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750111278; cv=none; b=cApLs42tZLH0q2cZQbOZ0JZE44RdjpjMVu0cMTuGWEYNsIX9JC4dLuHtRJZdElXUesvCCPt/EiPdJbSvTTpsGWOXZC4ayJjE2VVom2aButwpjTGTvqIXqH5skNnL972YL/JPXcCvuK3LCobt31buN8AuXiwy9aom+4VDCfLgH7w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750111278; c=relaxed/simple; bh=AcUKZuHRVnI+4gxBISBOYegc/FcNVd9I4VO+rzYErV8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=UGG4HoEnSI3jhQ0y4loHPWwHixyB1pT8bBG3nVwON0tq5+fZEag6BvGQpVrHtIMH1ke5KPF63MDNIMWdeCHkOlrxgFf3KKx7+pRPJpI8Mdl8YYlWl8Ev2ZEpo5WC9diicdNkc7xWnnHw3Ak4VIA55waf9RRvUVuefiWIxWH7sSw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=Mn/zUG2Q; arc=none smtp.client-ip=95.215.58.183 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="Mn/zUG2Q" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1750111275; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=HXSa9B9J2FkeGT4PKUZGBGTcf10cHbFGccTdZDDZdaA=; b=Mn/zUG2QLLNhYeX2c9acd3FovpjK/9Kkpa3OQ1zhNTVCTlKrWbvOT6I9mZsLdHbw1hgEN+ 4mIeXOWd3L9iz6v9oOsMWIEtmrUhBRP2rrv0g3zAkSsvUefXApCC82XXx9JKbRzOriLwoZ o8lBHp3GA6DY5eRIaDsh+nci5t86Bf0= From: Sean Anderson To: Mark Brown , Michal Simek , linux-spi@vger.kernel.org Cc: Jinjie Ruan , Miquel Raynal , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, David Lechner , Amit Kumar Mahapatra , Sean Anderson Subject: [PATCH v2 3/9] spi: Support multi-bus controllers Date: Mon, 16 Jun 2025 18:00:48 -0400 Message-Id: <20250616220054.3968946-4-sean.anderson@linux.dev> In-Reply-To: <20250616220054.3968946-1-sean.anderson@linux.dev> References: <20250616220054.3968946-1-sean.anderson@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" From: David Lechner Add support for SPI controllers with multiple physical SPI buses. This is common in the type of controller that can be used with parallel flash memories, but can be used for general purpose SPI as well. To indicate support, a controller just needs to set ctlr->num_buses to something greater than 1. Peripherals indicate which bus they are connected to via device tree (ACPI support can be added if needed). In the future, this can be extended to support peripherals that also have multiple SPI buses to use those buses at the same time by adding a similar bus flags field to struct spi_transfer. Signed-off-by: David Lechner Signed-off-by: Sean Anderson --- Changes in v2: - New drivers/spi/spi.c | 26 +++++++++++++++++++++++++- include/linux/spi/spi.h | 13 +++++++++++++ 2 files changed, 38 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index 1bc0fdbb1bd7..9fbf069623a8 100644 --- a/drivers/spi/spi.c +++ b/drivers/spi/spi.c @@ -2359,7 +2359,7 @@ static void of_spi_parse_dt_cs_delay(struct device_no= de *nc, static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device = *spi, struct device_node *nc) { - u32 value, cs[SPI_CS_CNT_MAX]; + u32 value, buses[8], cs[SPI_CS_CNT_MAX]; int rc, idx; =20 /* Mode (clock phase/polarity/etc.) */ @@ -2460,6 +2460,29 @@ static int of_spi_parse_dt(struct spi_controller *ct= lr, struct spi_device *spi, for (idx =3D 0; idx < rc; idx++) spi_set_chipselect(spi, idx, cs[idx]); =20 + rc =3D of_property_read_variable_u32_array(nc, "spi-buses", buses, 1, + ARRAY_SIZE(buses)); + if (rc < 0 && rc !=3D -EINVAL) { + dev_err(&ctlr->dev, "%pOF has invalid 'spi-buses' property (%d)\n", + nc, rc); + return rc; + } + + if (rc =3D=3D -EINVAL) { + /* Default when property is omitted. */ + spi->buses =3D BIT(0); + } else { + for (idx =3D 0; idx < rc; idx++) { + if (buses[idx] >=3D ctlr->num_buses) { + dev_err(&ctlr->dev, + "%pOF has out of range 'spi-buses' property (%d)\n", + nc, buses[idx]); + return -EINVAL; + } + spi->buses |=3D BIT(buses[idx]); + } + } + /* * By default spi->chip_select[0] will hold the physical CS number, * so set bit 0 in spi->cs_index_mask. @@ -3070,6 +3093,7 @@ struct spi_controller *__spi_alloc_controller(struct = device *dev, mutex_init(&ctlr->add_lock); ctlr->bus_num =3D -1; ctlr->num_chipselect =3D 1; + ctlr->num_buses =3D 1; ctlr->target =3D target; if (IS_ENABLED(CONFIG_SPI_SLAVE) && target) ctlr->dev.class =3D &spi_target_class; diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h index 4789f91dae94..70e8e6555a33 100644 --- a/include/linux/spi/spi.h +++ b/include/linux/spi/spi.h @@ -228,6 +228,11 @@ struct spi_device { struct spi_delay cs_hold; struct spi_delay cs_inactive; =20 + /* + * Bit flags indicating which buses this device is connected to. Only + * applicable to multi-bus controllers. + */ + u8 buses; u8 chip_select[SPI_CS_CNT_MAX]; =20 /* @@ -574,6 +579,14 @@ struct spi_controller { */ u16 num_chipselect; =20 + /* + * Some specialized SPI controllers can have more than one physical + * bus interface per controller. This specifies the number of buses + * in that case. Other controllers do not need to set this (defaults + * to 1). + */ + u16 num_buses; + /* Some SPI controllers pose alignment requirements on DMAable * buffers; let protocol drivers know about these requirements. */ --=20 2.35.1.1320.gc452695387.dirty From nobody Thu Oct 9 16:37:47 2025 Received: from out-189.mta1.migadu.com (out-189.mta1.migadu.com [95.215.58.189]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 15A6022D9F7 for ; Mon, 16 Jun 2025 22:01:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.189 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750111281; cv=none; b=NxmoLI46VZkiE8BXgUzwD4DgqGcwBIwPnjCgG5xkNe+r6DIA7DGeqtobF0SBbxekyl8XQes2+8fxs76rmyRSyHZG5/EcClTNA+9vC79nvvV4F8byeDJRYCrTl/OqgZH3oIqzF5cQc3lIR8w27ToKnjFRIFJjR0vlh52TuXlgbjc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750111281; c=relaxed/simple; bh=vCP/PaR6IG5saR7yXq+ikd9n8NjFbEdzOfmfr1VN9Sw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=HrT1JILLvX9OTi90xLyhZw44ro1PhpUCVcIXK0GAnc87xxzrIJ/H74sV/Mjxa14JHEvbae3PuTeK/1V3AxNyEWLlbtku2dajislQMi4JDb42xJQk1XkeYGERTCxEhNDDE05yY/CEusIrq/yzePHnSUV7OxL/U8WiHaLftZP5TmM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=iVSfe482; arc=none smtp.client-ip=95.215.58.189 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="iVSfe482" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1750111278; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=TYfaovqReb0YC/IVKoaet5lnN16Aykfnj2HI88YzzQU=; b=iVSfe4829NP8fycZu8j2fpXmtjF/KVdc9OyiEFUGfAAeDc97G2/yleYdCKG++p79wq3CqZ vvZQ01SnJykyrg3vFPJBHUT96AnYHB+6PgkH7ajQbyXXB8oCwB5tZIdeGn11n9EoVNwvWH h4LI5mWdcBlHSrBUwsJ0FCgIEEgvuPo= From: Sean Anderson To: Mark Brown , Michal Simek , linux-spi@vger.kernel.org Cc: Jinjie Ruan , Miquel Raynal , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, David Lechner , Amit Kumar Mahapatra , Sean Anderson Subject: [PATCH v2 4/9] spi: Add flag to determine default bus Date: Mon, 16 Jun 2025 18:00:49 -0400 Message-Id: <20250616220054.3968946-5-sean.anderson@linux.dev> In-Reply-To: <20250616220054.3968946-1-sean.anderson@linux.dev> References: <20250616220054.3968946-1-sean.anderson@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" The ZynqMP GQSPI driver determines the default SPI bus based on the chip select. For compatibility, introduce a flag to determine the buses from the chipselect when the spi-buses property is absent. Signed-off-by: Sean Anderson --- Changes in v2: - New drivers/spi/spi.c | 7 ++++++- include/linux/spi/spi.h | 2 ++ 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index 9fbf069623a8..d9d0c24cee0b 100644 --- a/drivers/spi/spi.c +++ b/drivers/spi/spi.c @@ -2470,7 +2470,12 @@ static int of_spi_parse_dt(struct spi_controller *ct= lr, struct spi_device *spi, =20 if (rc =3D=3D -EINVAL) { /* Default when property is omitted. */ - spi->buses =3D BIT(0); + if ((ctlr->flags & SPI_CONTROLLER_DEFAULT_BUS_IS_CS) && + cs[0] !=3D SPI_INVALID_CS && cs[0] < ctlr->num_buses) { + spi->buses =3D BIT(cs[0]); + } else { + spi->buses =3D BIT(0); + } } else { for (idx =3D 0; idx < rc; idx++) { if (buses[idx] >=3D ctlr->num_buses) { diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h index 70e8e6555a33..cea93b0895b9 100644 --- a/include/linux/spi/spi.h +++ b/include/linux/spi/spi.h @@ -621,6 +621,8 @@ struct spi_controller { * assert/de-assert more than one chip select at once. */ #define SPI_CONTROLLER_MULTI_CS BIT(7) + /* spi_device->buses defaults to spi_device->cs[0] */ +#define SPI_CONTROLLER_DEFAULT_BUS_IS_CS BIT(8) =20 /* Flag indicating if the allocation of this struct is devres-managed */ bool devm_allocated; --=20 2.35.1.1320.gc452695387.dirty From nobody Thu Oct 9 16:37:47 2025 Received: from out-188.mta1.migadu.com (out-188.mta1.migadu.com [95.215.58.188]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 88A1C23313E for ; Mon, 16 Jun 2025 22:01:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.188 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750111283; cv=none; b=s5mHSBxhQJtABTlmV61hNvaieXK785t6Lw/gY9fzLLFX4IEhVYUdglfK4nM3P0YP94azjentbC/qAtzyrMS3PgbAgpPnGquK5DOUGgQN9IAcOiqiyLho7OCe0AOQTAv8ll2bAcU7LNpNW69/aSHF7lARKRGXqJwtw2j4C3XaAew= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750111283; c=relaxed/simple; bh=J3HRmysUvAMuPBZHaaEJ3p7CVlln3bfpkvyA/v/2xVE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=SFuKlG1DngloKConFWFpJtfWhvBxz2AtaX7IKAJr06gvy8i1QBOdMaLCIMtNxKySQkwKVXjnpgYFj6nu8ntzmz2QtfweFgedKicw1VC0RtIIcrGg7ODLZRLbsAHErQUKE6rJVJioAq+LpU9aHTWJM4RgCOO8FAKQJi9g4ctpzvQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=jrwOh4Kh; arc=none smtp.client-ip=95.215.58.188 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="jrwOh4Kh" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1750111279; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=lKeCmjqMfNPPRNpjK82ZCg/Ku8sd60DeUcDOkrmPcJw=; b=jrwOh4KhAkiVpQJgns719VppdBhUkBodMTpMmBIxn1pEQ5ZOseJMmS01AU9i3k9usbeX2m AIQPuPtqEC1V3cZQr7KCdMicMohKEb8K9jjExEpMsKQxQe4Qtrmpv9A3CJW4ifwu0iDv3H RX4HjQtW2x1O3p8JTtFDKs/Ju8Y8O2A= From: Sean Anderson To: Mark Brown , Michal Simek , linux-spi@vger.kernel.org Cc: Jinjie Ruan , Miquel Raynal , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, David Lechner , Amit Kumar Mahapatra , Sean Anderson Subject: [PATCH v2 5/9] spi: zynqmp-gqspi: Support multiple buses Date: Mon, 16 Jun 2025 18:00:50 -0400 Message-Id: <20250616220054.3968946-6-sean.anderson@linux.dev> In-Reply-To: <20250616220054.3968946-1-sean.anderson@linux.dev> References: <20250616220054.3968946-1-sean.anderson@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" Currently, selection of the upper/lower buses is determined by the chipselect. Decouple this by allowing explicit bus selection through the spi-buses property. Signed-off-by: Sean Anderson --- Changes in v2: - New drivers/spi/spi-zynqmp-gqspi.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/spi/spi-zynqmp-gqspi.c b/drivers/spi/spi-zynqmp-gqspi.c index 595b6dc10845..add5eea12153 100644 --- a/drivers/spi/spi-zynqmp-gqspi.c +++ b/drivers/spi/spi-zynqmp-gqspi.c @@ -465,13 +465,13 @@ static void zynqmp_qspi_chipselect(struct spi_device = *qspi, bool is_high) genfifoentry |=3D GQSPI_GENFIFO_MODE_SPI; =20 if (!is_high) { - if (!spi_get_chipselect(qspi, 0)) { - xqspi->genfifobus =3D GQSPI_GENFIFO_BUS_LOWER; + xqspi->genfifobus =3D + FIELD_PREP(GQSPI_GENFIFO_BUS_MASK, qspi->buses); + if (!spi_get_chipselect(qspi, 0)) xqspi->genfifocs =3D GQSPI_GENFIFO_CS_LOWER; - } else { - xqspi->genfifobus =3D GQSPI_GENFIFO_BUS_UPPER; + else xqspi->genfifocs =3D GQSPI_GENFIFO_CS_UPPER; - } + genfifoentry |=3D xqspi->genfifobus; genfifoentry |=3D xqspi->genfifocs; genfifoentry |=3D GQSPI_GENFIFO_CS_SETUP; @@ -1316,6 +1316,8 @@ static int zynqmp_qspi_probe(struct platform_device *= pdev) ctlr->num_chipselect =3D num_cs; } =20 + ctlr->num_buses =3D 2; + ctlr->flags =3D SPI_CONTROLLER_DEFAULT_BUS_IS_CS; ctlr->bits_per_word_mask =3D SPI_BPW_MASK(8); ctlr->mem_ops =3D &zynqmp_qspi_mem_ops; ctlr->mem_caps =3D &zynqmp_qspi_mem_caps; --=20 2.35.1.1320.gc452695387.dirty From nobody Thu Oct 9 16:37:47 2025 Received: from out-182.mta1.migadu.com (out-182.mta1.migadu.com [95.215.58.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6DBFB221F11 for ; Mon, 16 Jun 2025 22:01:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.182 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750111285; cv=none; b=gCJodsAEqEMU8MGy9FiCwdejetBm/yMuDNxFUzHHexIpad5V2h/ac8AuulHXaGqmW0kka7DUxJsbeJmExFoBX1Q/cLnj7/P6ehg5+tFOcYy5Bwj/x//dmooU+HYt29a+ScFQhEOaIeklMbGdBdiaAoCN421gkpWfG1Aecj9t2cI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750111285; c=relaxed/simple; bh=NcmTj5O4UnDJpKrXg8mlqcQXqW5kLOfOgZhvciV6zUo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=uhdAWSMSH0S3nn6QqYAHMRYdQ5hcntzTKnNTAFibScl6oc4veHg0xVs6L53LlvoEKjB5u+Z32mmuGTp45XegH6PpLRDT2vmg5XsmI+7vg80uj4bJlBNFWkXrLzjupydK1v400G9nHwbAJSm6Q5LZ82dSfLfEYrQW0wIVypL2Zvs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=udplqrxW; arc=none smtp.client-ip=95.215.58.182 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="udplqrxW" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1750111281; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=UpXv1zP1pu51TTfErAKypkJY3vjgrcKFdh3KjXTzhFA=; b=udplqrxWmGeRFbpu6YjHOGUPktFGJtRBM5UfUSsLYVTGVZ2Yt7dK+XIYp7GzFbUKRk447d nJ8irijhPldc1awyPuB+LHl3oEr9g9aOSJn+LM0DavL274LLBCCTUpZfacG1+O0+A3TrFl NjLIvzJbMesvV/uqBA2M7Ka98jjmCHQ= From: Sean Anderson To: Mark Brown , Michal Simek , linux-spi@vger.kernel.org Cc: Jinjie Ruan , Miquel Raynal , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, David Lechner , Amit Kumar Mahapatra , Sean Anderson Subject: [PATCH v2 6/9] spi: zynqmp-gqspi: Pass speed directly to config_op Date: Mon, 16 Jun 2025 18:00:51 -0400 Message-Id: <20250616220054.3968946-7-sean.anderson@linux.dev> In-Reply-To: <20250616220054.3968946-1-sean.anderson@linux.dev> References: <20250616220054.3968946-1-sean.anderson@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" In preparation for supporting transfer_one, which supplies the speed from the spi_transfer instead of the spi_device, convert config_op to take the speed directly. Signed-off-by: Sean Anderson --- (no changes since v1) drivers/spi/spi-zynqmp-gqspi.c | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/drivers/spi/spi-zynqmp-gqspi.c b/drivers/spi/spi-zynqmp-gqspi.c index add5eea12153..a17e77dc4e27 100644 --- a/drivers/spi/spi-zynqmp-gqspi.c +++ b/drivers/spi/spi-zynqmp-gqspi.c @@ -533,8 +533,8 @@ static inline u32 zynqmp_qspi_selectspimode(struct zynq= mp_qspi *xqspi, /** * zynqmp_qspi_config_op - Configure QSPI controller for specified * transfer - * @xqspi: Pointer to the zynqmp_qspi structure - * @op: The memory operation to execute + * @xqspi: Pointer to the zynqmp_qspi structure + * @req_speed_hz: Requested frequency * * Sets the operational mode of QSPI controller for the next QSPI transfer= and * sets the requested clock frequency. @@ -551,13 +551,10 @@ static inline u32 zynqmp_qspi_selectspimode(struct zy= nqmp_qspi *xqspi, * by the QSPI controller the driver will set the highest or lowest * frequency supported by controller. */ -static int zynqmp_qspi_config_op(struct zynqmp_qspi *xqspi, - const struct spi_mem_op *op) +static int zynqmp_qspi_config_op(struct zynqmp_qspi *xqspi, u32 req_speed_= hz) { ulong clk_rate; - u32 config_reg, req_speed_hz, baud_rate_val =3D 0; - - req_speed_hz =3D op->max_freq; + u32 config_reg, baud_rate_val =3D 0; =20 if (xqspi->speed_hz !=3D req_speed_hz) { xqspi->speed_hz =3D req_speed_hz; @@ -1053,7 +1050,7 @@ static int zynqmp_qspi_exec_op(struct spi_mem *mem, u64 opaddr; =20 mutex_lock(&xqspi->op_lock); - zynqmp_qspi_config_op(xqspi, op); + zynqmp_qspi_config_op(xqspi, op->max_freq); zynqmp_qspi_chipselect(mem->spi, false); genfifoentry |=3D xqspi->genfifocs; genfifoentry |=3D xqspi->genfifobus; --=20 2.35.1.1320.gc452695387.dirty From nobody Thu Oct 9 16:37:47 2025 Received: from out-188.mta1.migadu.com (out-188.mta1.migadu.com [95.215.58.188]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E9DBB238152 for ; Mon, 16 Jun 2025 22:01:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.188 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750111287; cv=none; b=MoxyTaElIYOb35+KY/DFEmppCDV2xFHJdWREG16NNDvm/6hmehSdUI26jb2rN4gUPIa1jn98HTKHsA8OSHtxmkYQwhU2Gxrz5Dvdgd/rqeDpdhwX7teg1i1qMtDmNKf8VEdQZyaRToNf+D1OipbKuY8mm37LCuge9CU1usF0V5E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750111287; c=relaxed/simple; bh=Wraj1hZ3EBxKe2cyb3q1iqv3qisL2xc0bmwF6cli6Hk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=OdsyzUz4FoovDetyoiogaGNOchw9/KwNMi8E8ioLwRLNVcAomzMLrJQhPv6IjUakBjuiWyLMxrfqJ3gUlB2QSOjfseFLqQLe6kmzVnzEfRbD2RXJ5HhtfMm2lrpPcq5ybHJXRMfdBBO08xijS5MoqrVY95xRZ1Lc89MRqZvudSI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=vpEA3/2l; arc=none smtp.client-ip=95.215.58.188 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="vpEA3/2l" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1750111283; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=NGOH8Yvcz0WgyTH+Nb2rF8MG3xwZ18CiFbl2INC4Pwc=; b=vpEA3/2lKQLW1KlQy0fAkRGHmm41rLVtpUYTk/FtQEClVaZDGiw59+7LhF+lpXDM4UzepZ fb4cLEp2SSBV37UlS50QI9aUP5JoKCOYg8XHGzaXk3p8SXV1m7VcZ9qcay0zX7+/bT9NfA vwKxcXFL30SFCIuAsagUKLA+gFHt3mw= From: Sean Anderson To: Mark Brown , Michal Simek , linux-spi@vger.kernel.org Cc: Jinjie Ruan , Miquel Raynal , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, David Lechner , Amit Kumar Mahapatra , Sean Anderson Subject: [PATCH v2 7/9] spi: zynqmp-gqspi: Configure SPI mode dynamically Date: Mon, 16 Jun 2025 18:00:52 -0400 Message-Id: <20250616220054.3968946-8-sean.anderson@linux.dev> In-Reply-To: <20250616220054.3968946-1-sean.anderson@linux.dev> References: <20250616220054.3968946-1-sean.anderson@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" The SPI mode (phase/polarity) can change between spi_transfers. In preparation for transfer_one support, program the SPI mode on every operation instead of once during init. Signed-off-by: Sean Anderson --- (no changes since v1) drivers/spi/spi-zynqmp-gqspi.c | 43 +++++++++++++++++++++++----------- 1 file changed, 29 insertions(+), 14 deletions(-) diff --git a/drivers/spi/spi-zynqmp-gqspi.c b/drivers/spi/spi-zynqmp-gqspi.c index a17e77dc4e27..b36159dbaff0 100644 --- a/drivers/spi/spi-zynqmp-gqspi.c +++ b/drivers/spi/spi-zynqmp-gqspi.c @@ -184,7 +184,8 @@ struct qspi_platform_data { * @mode: Defines the mode in which QSPI is operating * @data_completion: completion structure * @op_lock: Operational lock - * @speed_hz: Current SPI bus clock speed in hz + * @speed_hz: Current SPI bus clock speed in hz + * @spi_mode: Current SPI bus mode * @has_tapdelay: Used for tapdelay register available in qspi */ struct zynqmp_qspi { @@ -207,6 +208,7 @@ struct zynqmp_qspi { struct completion data_completion; struct mutex op_lock; u32 speed_hz; + u32 spi_mode; bool has_tapdelay; }; =20 @@ -387,16 +389,11 @@ static void zynqmp_qspi_init_hw(struct zynqmp_qspi *x= qspi) config_reg |=3D GQSPI_CFG_WP_HOLD_MASK; /* Clear pre-scalar by default */ config_reg &=3D ~GQSPI_CFG_BAUD_RATE_DIV_MASK; - /* Set CPHA */ - if (xqspi->ctlr->mode_bits & SPI_CPHA) - config_reg |=3D GQSPI_CFG_CLK_PHA_MASK; - else - config_reg &=3D ~GQSPI_CFG_CLK_PHA_MASK; - /* Set CPOL */ - if (xqspi->ctlr->mode_bits & SPI_CPOL) - config_reg |=3D GQSPI_CFG_CLK_POL_MASK; - else - config_reg &=3D ~GQSPI_CFG_CLK_POL_MASK; + + /* Set default mode */ + xqspi->spi_mode =3D SPI_MODE_3; + config_reg |=3D GQSPI_CFG_CLK_PHA_MASK; + config_reg |=3D GQSPI_CFG_CLK_POL_MASK; =20 /* Set the clock frequency */ clk_rate =3D clk_get_rate(xqspi->refclk); @@ -535,6 +532,7 @@ static inline u32 zynqmp_qspi_selectspimode(struct zynq= mp_qspi *xqspi, * transfer * @xqspi: Pointer to the zynqmp_qspi structure * @req_speed_hz: Requested frequency + * @mode: Requested SPI mode * * Sets the operational mode of QSPI controller for the next QSPI transfer= and * sets the requested clock frequency. @@ -551,7 +549,8 @@ static inline u32 zynqmp_qspi_selectspimode(struct zynq= mp_qspi *xqspi, * by the QSPI controller the driver will set the highest or lowest * frequency supported by controller. */ -static int zynqmp_qspi_config_op(struct zynqmp_qspi *xqspi, u32 req_speed_= hz) +static int zynqmp_qspi_config_op(struct zynqmp_qspi *xqspi, u32 req_speed_= hz, + u32 mode) { ulong clk_rate; u32 config_reg, baud_rate_val =3D 0; @@ -577,7 +576,23 @@ static int zynqmp_qspi_config_op(struct zynqmp_qspi *x= qspi, u32 req_speed_hz) zynqmp_qspi_set_tapdelay(xqspi, baud_rate_val); } =20 - dev_dbg(xqspi->dev, "config speed %u\n", req_speed_hz); + mode &=3D SPI_MODE_X_MASK; + if (xqspi->spi_mode !=3D mode) { + xqspi->spi_mode =3D mode; + + config_reg =3D zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST); + if (mode & SPI_CPHA) + config_reg |=3D GQSPI_CFG_CLK_PHA_MASK; + else + config_reg &=3D ~GQSPI_CFG_CLK_PHA_MASK; + if (mode & SPI_CPOL) + config_reg |=3D GQSPI_CFG_CLK_POL_MASK; + else + config_reg &=3D ~GQSPI_CFG_CLK_POL_MASK; + zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg); + } + + dev_dbg(xqspi->dev, "config speed %u mode %x\n", req_speed_hz, mode); return 0; } =20 @@ -1050,7 +1065,7 @@ static int zynqmp_qspi_exec_op(struct spi_mem *mem, u64 opaddr; =20 mutex_lock(&xqspi->op_lock); - zynqmp_qspi_config_op(xqspi, op->max_freq); + zynqmp_qspi_config_op(xqspi, op->max_freq, mem->spi->mode); zynqmp_qspi_chipselect(mem->spi, false); genfifoentry |=3D xqspi->genfifocs; genfifoentry |=3D xqspi->genfifobus; --=20 2.35.1.1320.gc452695387.dirty From nobody Thu Oct 9 16:37:47 2025 Received: from out-180.mta1.migadu.com (out-180.mta1.migadu.com [95.215.58.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7BC9F223DD5 for ; Mon, 16 Jun 2025 22:01:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.180 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750111288; cv=none; b=m5S1oeiGJp2aqQgO6UoLKWeEJJkwRiWiuZwdHAY5r7YG+ct4hEHGNLBMnEleUbFK0NbxMn1w/UxifjxDe3NRY1fbAOuWownAUdpfJJ/4hPT+p2qOIaSiCNVFQktg2Uo63Wlui6LNTQabOI8QfQQH/HG+EGwSJ6qJjztSs2RXa7Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750111288; c=relaxed/simple; bh=GDARaksPLKEKseFYGSFlXG8ZZvfvQwPmIQyC3rwaexU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; 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DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1750111284; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=U8s2DHgn3w9rCn5wed99fTlnLPjizNqzhROnC2hjDTA=; b=fRpI7zM8EJ3lvBmGn2ZK6cQPnRoS5fEUqpX4uEe/Q79CiQkoJ8ri/t072mO5lxXCYc/qbc 3KTVhRUQHgYXwCYzio47tXfi1X9NhHR5sreoEhqfjwuviauAq0QTq/k8y7nquFpMCUJpxW RNJwGK6tuqfrBzMKUy133m4n6EGrudc= From: Sean Anderson To: Mark Brown , Michal Simek , linux-spi@vger.kernel.org Cc: Jinjie Ruan , Miquel Raynal , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, David Lechner , Amit Kumar Mahapatra , Sean Anderson Subject: [PATCH v2 8/9] spi: zynqmp-gqspi: Support GPIO chip selects Date: Mon, 16 Jun 2025 18:00:53 -0400 Message-Id: <20250616220054.3968946-9-sean.anderson@linux.dev> In-Reply-To: <20250616220054.3968946-1-sean.anderson@linux.dev> References: <20250616220054.3968946-1-sean.anderson@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" GPIO chipselects use the traditional SPI API instead of the SPIMEM API. Implement it with transfer_one and set_cs (for non-GPIO chipselects). At the moment we only support half-duplex transfers, which is good enough to access SPI flashes. Signed-off-by: Sean Anderson --- Changes in v2: - Use ->buses instead of an upper/lower split drivers/spi/spi-zynqmp-gqspi.c | 93 ++++++++++++++++++++++++++++++---- 1 file changed, 84 insertions(+), 9 deletions(-) diff --git a/drivers/spi/spi-zynqmp-gqspi.c b/drivers/spi/spi-zynqmp-gqspi.c index b36159dbaff0..87d375fae653 100644 --- a/drivers/spi/spi-zynqmp-gqspi.c +++ b/drivers/spi/spi-zynqmp-gqspi.c @@ -499,6 +499,15 @@ static void zynqmp_qspi_chipselect(struct spi_device *= qspi, bool is_high) dev_err(xqspi->dev, "Chip select timed out\n"); } =20 +static void zynqmp_qspi_set_cs(struct spi_device *qspi, bool is_high) +{ + struct zynqmp_qspi *xqspi =3D spi_controller_get_devdata(qspi->controller= ); + + mutex_lock(&xqspi->op_lock); + zynqmp_qspi_chipselect(qspi, is_high); + mutex_unlock(&xqspi->op_lock); +} + /** * zynqmp_qspi_selectspimode - Selects SPI mode - x1 or x2 or x4. * @xqspi: xqspi is a pointer to the GQSPI instance @@ -1197,6 +1206,73 @@ static int zynqmp_qspi_exec_op(struct spi_mem *mem, return err; } =20 +static int zynqmp_qspi_transfer_one(struct spi_controller *ctlr, + struct spi_device *spi, + struct spi_transfer *transfer) +{ + struct zynqmp_qspi *xqspi =3D spi_controller_get_devdata(ctlr); + unsigned long timeout; + u32 genfifoentry; + u32 mask =3D 0; + int ret; + + dev_dbg(xqspi->dev, "xfer %u/%u %u\n", transfer->tx_nbits, + transfer->rx_nbits, transfer->len); + + if (transfer->tx_nbits && transfer->rx_nbits) + return -EOPNOTSUPP; + + guard(mutex)(&xqspi->op_lock); + zynqmp_qspi_config_op(xqspi, transfer->speed_hz, spi->mode); + if (spi_get_csgpiod(spi, 0)) { + xqspi->genfifobus =3D + FIELD_PREP(GQSPI_GENFIFO_BUS_MASK, spi->buses); + xqspi->genfifocs =3D 0; + } + genfifoentry =3D xqspi->genfifocs | xqspi->genfifobus; + + reinit_completion(&xqspi->data_completion); + if (transfer->tx_nbits) { + xqspi->txbuf =3D transfer->tx_buf; + xqspi->rxbuf =3D NULL; + xqspi->bytes_to_transfer =3D transfer->len; + xqspi->bytes_to_receive =3D 0; + zynqmp_qspi_write_op(xqspi, transfer->tx_nbits, genfifoentry); + mask =3D GQSPI_IER_TXEMPTY_MASK | GQSPI_IER_GENFIFOEMPTY_MASK | + GQSPI_IER_TXNOT_FULL_MASK; + timeout =3D zynqmp_qspi_timeout(xqspi, transfer->tx_nbits, + transfer->len); + } else { + xqspi->txbuf =3D NULL; + xqspi->rxbuf =3D transfer->rx_buf; + xqspi->bytes_to_transfer =3D 0; + xqspi->bytes_to_receive =3D transfer->len; + ret =3D zynqmp_qspi_read_op(xqspi, transfer->rx_nbits, + genfifoentry); + if (ret) + return ret; + + if (xqspi->mode !=3D GQSPI_MODE_DMA) + mask =3D GQSPI_IER_GENFIFOEMPTY_MASK | + GQSPI_IER_RXNEMPTY_MASK | GQSPI_IER_RXEMPTY_MASK; + timeout =3D zynqmp_qspi_timeout(xqspi, transfer->rx_nbits, + transfer->len); + } + + zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, + zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) | + GQSPI_CFG_START_GEN_FIFO_MASK); + if (mask) + zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST, mask); + else + zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_EN_OFST, + GQSPI_QSPIDMA_DST_I_EN_DONE_MASK); + + if (!wait_for_completion_timeout(&xqspi->data_completion, timeout)) + return -ETIMEDOUT; + return 0; +} + static const struct dev_pm_ops zynqmp_qspi_dev_pm_ops =3D { SET_RUNTIME_PM_OPS(zynqmp_runtime_suspend, zynqmp_runtime_resume, NULL) @@ -1316,27 +1392,26 @@ static int zynqmp_qspi_probe(struct platform_device= *pdev) if (ret) goto clk_dis_all; =20 + ctlr->max_native_cs =3D 2; ret =3D of_property_read_u32(np, "num-cs", &num_cs); - if (ret < 0) { + if (ret < 0) ctlr->num_chipselect =3D GQSPI_DEFAULT_NUM_CS; - } else if (num_cs > GQSPI_MAX_NUM_CS) { - ret =3D -EINVAL; - dev_err(&pdev->dev, "only %d chip selects are available\n", - GQSPI_MAX_NUM_CS); - goto clk_dis_all; - } else { + else ctlr->num_chipselect =3D num_cs; - } =20 ctlr->num_buses =3D 2; - ctlr->flags =3D SPI_CONTROLLER_DEFAULT_BUS_IS_CS; + ctlr->flags =3D SPI_CONTROLLER_DEFAULT_BUS_IS_CS | + SPI_CONTROLLER_HALF_DUPLEX; ctlr->bits_per_word_mask =3D SPI_BPW_MASK(8); ctlr->mem_ops =3D &zynqmp_qspi_mem_ops; ctlr->mem_caps =3D &zynqmp_qspi_mem_caps; ctlr->setup =3D zynqmp_qspi_setup_op; + ctlr->set_cs =3D zynqmp_qspi_set_cs; + ctlr->transfer_one =3D zynqmp_qspi_transfer_one; ctlr->bits_per_word_mask =3D SPI_BPW_MASK(8); ctlr->dev.of_node =3D np; ctlr->auto_runtime_pm =3D true; + ctlr->use_gpio_descriptors =3D true; =20 ret =3D devm_spi_register_controller(&pdev->dev, ctlr); if (ret) { --=20 2.35.1.1320.gc452695387.dirty From nobody Thu Oct 9 16:37:47 2025 Received: from out-172.mta1.migadu.com (out-172.mta1.migadu.com [95.215.58.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4A22C23B60C for ; Mon, 16 Jun 2025 22:01:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750111290; cv=none; b=CkGrpfqR6QvES5R4xJi39nwdU+DtVJdX339dZKOpndTFXB8dYqH0Jc+vl0XIzaR+Ljuh2teufG3wKpzsUPewWQkRYLBFBCieOGdZVAoLkY54IcRGjUbocI4f2it3lZyY906MDPNGacej8dQQEEqgGy4iOnoQovt5r/hQ5wIc6ZE= ARC-Message-Signature: i=1; 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DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1750111286; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=baIhgE/N38Lr9mmVCwKX0SXbBt/r7eLwevkwAfS0a18=; b=EqtSoBDAhVsc11UmSbE01aj/EmNvOXXZu5gS7VXEGDDNz4D+TobMSEaQ6RA10sZeDGgKYZ MHjLl4dQaiKRo6DjwxEIUpfEIuoZp5+PIkToBDNsZM+GrF/q8HmAhmBiU6LPOiZnjggmKc ycVP8hhm8oqBGMXYMLJzYeYOInrwe+4= From: Sean Anderson To: Mark Brown , Michal Simek , linux-spi@vger.kernel.org Cc: Jinjie Ruan , Miquel Raynal , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, David Lechner , Amit Kumar Mahapatra , Sean Anderson , Conor Dooley , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH v2 9/9] ARM64: xilinx: zynqmp: Add spi-buses property Date: Mon, 16 Jun 2025 18:00:54 -0400 Message-Id: <20250616220054.3968946-10-sean.anderson@linux.dev> In-Reply-To: <20250616220054.3968946-1-sean.anderson@linux.dev> References: <20250616220054.3968946-1-sean.anderson@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" Add the spi-buses property to the ZynqMP devicetrees. This is pretty simple, since all boards use the lower bus. Signed-off-by: Sean Anderson --- (no changes since v1) arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts | 1 + arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts | 1 + arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts | 1 + arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts | 1 + arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 1 + arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts | 1 + arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts | 1 + arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts | 1 + arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts | 1 + arch/arm64/boot/dts/xilinx/zynqmp-zcu1275-revA.dts | 1 + 10 files changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts b/arch/arm64= /boot/dts/xilinx/zynqmp-sm-k26-revA.dts index bfa7ea6b9224..3d3cb656f38c 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts @@ -132,6 +132,7 @@ &qspi { /* MIO 0-5 - U143 */ spi_flash: flash@0 { /* MT25QU512A */ compatible =3D "jedec,spi-nor"; /* 64MB */ reg =3D <0>; + spi-buses =3D <0>; spi-tx-bus-width =3D <4>; spi-rx-bus-width =3D <4>; spi-max-frequency =3D <40000000>; /* 40MHz */ diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts b/arch/arm64= /boot/dts/xilinx/zynqmp-zc1254-revA.dts index 3dec57cf18be..f550ccea58cd 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts @@ -45,6 +45,7 @@ flash@0 { #address-cells =3D <1>; #size-cells =3D <1>; reg =3D <0x0>; + spi-buses =3D <0>; spi-tx-bus-width =3D <4>; spi-rx-bus-width =3D <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency =3D <108000000>; /* Based on DC1 spec */ diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts b/arch/= arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts index 6aff22d43361..4ad5efdd40cd 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts @@ -359,6 +359,7 @@ flash@0 { #address-cells =3D <1>; #size-cells =3D <1>; reg =3D <0x0>; + spi-buses =3D <0>; spi-tx-bus-width =3D <4>; spi-rx-bus-width =3D <4>; spi-max-frequency =3D <108000000>; /* Based on DC1 spec */ diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts b/arch/= arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts index 6ec1d9813973..26c33685b320 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts @@ -177,6 +177,7 @@ flash@0 { #address-cells =3D <1>; #size-cells =3D <1>; reg =3D <0x0>; + spi-buses =3D <0>; spi-tx-bus-width =3D <4>; spi-rx-bus-width =3D <4>; /* also DUAL configuration possible */ spi-max-frequency =3D <108000000>; /* Based on DC1 spec */ diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64= /boot/dts/xilinx/zynqmp-zcu102-revA.dts index 7e26489a1539..aa4ed3a082fa 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts @@ -958,6 +958,7 @@ flash@0 { #address-cells =3D <1>; #size-cells =3D <1>; reg =3D <0x0>; + spi-buses =3D <0>; spi-tx-bus-width =3D <4>; spi-rx-bus-width =3D <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency =3D <108000000>; /* Based on DC1 spec */ diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts b/arch/arm64= /boot/dts/xilinx/zynqmp-zcu104-revA.dts index eb2090673ec1..acbe0758a31b 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts @@ -444,6 +444,7 @@ flash@0 { #address-cells =3D <1>; #size-cells =3D <1>; reg =3D <0x0>; + spi-buses =3D <0>; spi-tx-bus-width =3D <4>; spi-rx-bus-width =3D <4>; spi-max-frequency =3D <108000000>; /* Based on DC1 spec */ diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts b/arch/arm64= /boot/dts/xilinx/zynqmp-zcu104-revC.dts index 4694d0a841f1..9b0324acbeec 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts @@ -456,6 +456,7 @@ flash@0 { #address-cells =3D <1>; #size-cells =3D <1>; reg =3D <0x0>; + spi-buses =3D <0>; spi-tx-bus-width =3D <4>; spi-rx-bus-width =3D <4>; spi-max-frequency =3D <108000000>; /* Based on DC1 spec */ diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64= /boot/dts/xilinx/zynqmp-zcu106-revA.dts index 7beedd730f94..fd983f4c416d 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts @@ -964,6 +964,7 @@ flash@0 { #address-cells =3D <1>; #size-cells =3D <1>; reg =3D <0x0>; + spi-buses =3D <0>; spi-tx-bus-width =3D <4>; spi-rx-bus-width =3D <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency =3D <108000000>; /* Based on DC1 spec */ diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts b/arch/arm64= /boot/dts/xilinx/zynqmp-zcu111-revA.dts index b67ff7ecf3c3..af225413a274 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts @@ -794,6 +794,7 @@ flash@0 { #address-cells =3D <1>; #size-cells =3D <1>; reg =3D <0x0>; + spi-buses =3D <0>; spi-tx-bus-width =3D <4>; spi-rx-bus-width =3D <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency =3D <108000000>; /* Based on DC1 spec */ diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu1275-revA.dts b/arch/arm6= 4/boot/dts/xilinx/zynqmp-zcu1275-revA.dts index a38c2baeba6c..65790e341c15 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu1275-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu1275-revA.dts @@ -47,6 +47,7 @@ &qspi { flash@0 { compatible =3D "m25p80", "jedec,spi-nor"; reg =3D <0x0>; + spi-buses =3D <0>; spi-tx-bus-width =3D <4>; spi-rx-bus-width =3D <4>; spi-max-frequency =3D <108000000>; --=20 2.35.1.1320.gc452695387.dirty