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[184.74.55.142]) by smtp.googlemail.com with ESMTPSA id d75a77b69052e-4a72a5298f2sm50952041cf.80.2025.06.16.09.21.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Jun 2025 09:21:54 -0700 (PDT) From: Robert Cross To: netdev@vger.kernel.org Cc: bpf@vger.kernel.org, andrew@lunn.ch, olteanv@gmail.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, linux-kernel@vger.kernel.org, Robert Cross Subject: [PATCH v2] net: dsa: mv88e6xxx: fix external smi for mv88e6176 Date: Mon, 16 Jun 2025 12:20:25 -0400 Message-Id: <20250616162023.2795566-1-quantumcross@gmail.com> X-Mailer: git-send-email 2.39.5 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" (Sorry this is my second attempt, I fixed my email client) I was trying to enable external SMI on a mv88e6176. mv88e6390_g2_scratch_gpio_set_smi() would return -EBUSY when checking the scratch register Config DATA2 p0 mode to ensure that the external smi pins are free, but on my device, bit 4 of p0_mode was always 1, even if the port was completely disabled. Unless someone with the datasheet can prove me wrong, I believe that at least for the 6176, the mode mask here is 3 bits wide, and the fourth bit is irrelevant or reserved. To fix this, I add a field in mv88e6xxx_info to denote a p0_mode_mask_override to use. If this is set to the default value of 0, then the definition of MV88E6352_G2_SCRATCH_CONFIG_DATA2_P0_MODE_MASK will be used as normal. I can confirm that this allows me to use external smi on my mv88e6176! Fixes: 2510babcfaf0 ("net: dsa: mv88e6xxx: scratch registers and external M= DIO pins") Signed-off-by: Robert Cross --- drivers/net/dsa/mv88e6xxx/chip.c | 1 + drivers/net/dsa/mv88e6xxx/chip.h | 7 +++++++ drivers/net/dsa/mv88e6xxx/global2_scratch.c | 7 ++++++- 3 files changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/c= hip.c index 2281d6ab8c9ab..0fe7b6fc7016c 100644 --- a/drivers/net/dsa/mv88e6xxx/chip.c +++ b/drivers/net/dsa/mv88e6xxx/chip.c @@ -6013,6 +6013,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = =3D { .multi_chip =3D true, .edsa_support =3D MV88E6XXX_EDSA_SUPPORTED, .ops =3D &mv88e6176_ops, + .p0_mode_mask_override =3D 0x7, }, =20 [MV88E6185] =3D { diff --git a/drivers/net/dsa/mv88e6xxx/chip.h b/drivers/net/dsa/mv88e6xxx/c= hip.h index 7d00482f53a3b..6307c225ce94c 100644 --- a/drivers/net/dsa/mv88e6xxx/chip.h +++ b/drivers/net/dsa/mv88e6xxx/chip.h @@ -178,6 +178,13 @@ struct mv88e6xxx_info { * port 0, 1 means internal PHYs range starts at port 1, etc */ unsigned int internal_phys_offset; + + /* Some chips use 3 bits for the port mode in scratch + * register CONFIG Data2. + * If this is set to 0x0, it will use the default mask of + * MV88E6352_G2_SCRATCH_CONFIG_DATA2_P0_MODE_MASK + */ + u8 p0_mode_mask_override; }; =20 struct mv88e6xxx_atu_entry { diff --git a/drivers/net/dsa/mv88e6xxx/global2_scratch.c b/drivers/net/dsa/= mv88e6xxx/global2_scratch.c index 53a6d3ed63b32..7f1657eba7a4e 100644 --- a/drivers/net/dsa/mv88e6xxx/global2_scratch.c +++ b/drivers/net/dsa/mv88e6xxx/global2_scratch.c @@ -255,6 +255,7 @@ int mv88e6390_g2_scratch_gpio_set_smi(struct mv88e6xxx_= chip *chip, int config_data1 =3D MV88E6352_G2_SCRATCH_CONFIG_DATA1; int config_data2 =3D MV88E6352_G2_SCRATCH_CONFIG_DATA2; bool no_cpu; + u8 p0_mode_mask; u8 p0_mode; int err; u8 val; @@ -263,7 +264,11 @@ int mv88e6390_g2_scratch_gpio_set_smi(struct mv88e6xxx= _chip *chip, if (err) return err; =20 - p0_mode =3D val & MV88E6352_G2_SCRATCH_CONFIG_DATA2_P0_MODE_MASK; + p0_mode_mask =3D chip->info->p0_mode_mask_override; + if( p0_mode_mask =3D=3D 0x0) { + p0_mode_mask =3D MV88E6352_G2_SCRATCH_CONFIG_DATA2_P0_MODE_MASK; + } + p0_mode =3D val & p0_mode_mask; =20 if (p0_mode =3D=3D 0x01 || p0_mode =3D=3D 0x02) return -EBUSY; --=20 2.39.5