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Mon, 16 Jun 2025 07:14:56 -0700 From: Mark Bloch To: "David S. Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" , Simon Horman CC: , , , , Leon Romanovsky , "Jesper Dangaard Brouer" , Ilias Apalodimas , Richard Cochran , Alexei Starovoitov , Daniel Borkmann , John Fastabend , Stanislav Fomichev , , , , , Dragos Tatulea , Mina Almasry , Cosmin Ratiu , Mark Bloch Subject: [PATCH net-next v6 01/12] net: Allow const args for of page_to_netmem() Date: Mon, 16 Jun 2025 17:14:30 +0300 Message-ID: <20250616141441.1243044-2-mbloch@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250616141441.1243044-1-mbloch@nvidia.com> References: <20250616141441.1243044-1-mbloch@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PEPF0000000F:EE_|IA1PR12MB8288:EE_ X-MS-Office365-Filtering-Correlation-Id: 0cce0bc7-6446-42e8-7a35-08ddace032b3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|376014|7416014|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?VgtfhgE2pg5Rfqmcomn41l653qAXDlytgxjamrqAj1EmNCahAZezQtw678hY?= =?us-ascii?Q?Ux8Ba6R69hVN85D1D+jRDq/obn1SCCNzQbbcMYrrwJGgzWYcYyi008JWLuui?= =?us-ascii?Q?MlAoUYsTRJt5Kes+0eJrXUX0OoJ5ZrCGLtSSm1RJm1z2nxNLVXP+f8W7mURC?= =?us-ascii?Q?SLbaid2Orp0ip8+f5ozU9GXHOUwohYHeRx02qKmkJEIstAe+rUtQzNIxLCUL?= =?us-ascii?Q?mURSf7pCHm4EdUwFeW2mMA9S8g7nGwFXiQRP5C7d6ZBS3JK85vOi2bFx5r4Z?= =?us-ascii?Q?lFR01nIk9MjUvcJaUBE1VF6TbsM7H+7GJ0IZWchu7nB6FMGt0MUO7mQI/IJz?= =?us-ascii?Q?xBIE1zkpIBIz03BzM9ltKkjeLtDKQJct/nwIVjdZbcuSpQK57LDrV55gHpWT?= =?us-ascii?Q?XzL3lEZM3Wogz5lNqsX+QmvHaFGsHrQW95slPNrutVQQbCs+rZarEq11fgAp?= =?us-ascii?Q?WKL8nQENDENcGN30QVxXPk0GkLxtJWNG38lqRk54R8K++vjgeIhvBv5Rg0S4?= =?us-ascii?Q?87KXQwkUmqUoKoF2hPW5und8bsoAgSVvHOnHXstGqRxOQLtuQFot+GYg5ers?= =?us-ascii?Q?ex0m2RAApVjNX7Ox/PkuqBwFR1HNagp79pT+D0jONnvvJwOt+v2O+kbn1Ywg?= =?us-ascii?Q?ud8s8UlSX8hZSD5c8Uja1uEu5sCowD+aAgNB2KXPjFc/Sq2H8iuL29j9m09M?= =?us-ascii?Q?M36WmCQTFKx3lTuuXCZgsA867iDjwrFRLrxq5lmJ3Mt6lE4W1/WnutURGHs7?= =?us-ascii?Q?CIcKfbskVamu6rQgRXrEO7CQrdyLQFjMt10llKcxP+mqtJXGuVhPAQl91vKg?= =?us-ascii?Q?dqYuM2JBnRkw4+0gkxP2MHVHTFmtdWhJbcbyDFBucH4QrYYpBBRloKBmiz8b?= =?us-ascii?Q?QoLNcaMqFV7gMpTm3y1VoFN8l8kxZCVTmd6xhYxNkSOXp8cUbRDQy+WtQ1fd?= =?us-ascii?Q?ca+XxiAWWsJD9/5PzGOLFZsAi2ss0tzjXQ4tRCGiPTvXixP+3ErRrDoXSKU5?= =?us-ascii?Q?Wv54hqT9V+YsVdOHCQ4OxQqLcL8UCtVhkMNmGBx2RbQjsL9WyXgVs4gbl1vB?= =?us-ascii?Q?jXv/QD28oB+ACa+Yrq3bJ/omG94fNfsivNWJujaXu5PTc//mDuv5nUzUAvpR?= =?us-ascii?Q?Fk0uQKledREAFLwViKfL59ECaIDKIwsj5h9LaDo2AGwgY4zl05x9CpUeP3hF?= =?us-ascii?Q?ayLMcOdgaYhrVur4ABaPZSttOJB27OhPSei4QPimZ2vvLrXec66a6OgNu97n?= =?us-ascii?Q?ZXikaTxsuxlIlavxbjTGJH4usr9rqQ60n1okkkMOzxyUeIn6XTyZJH4M6Fx7?= =?us-ascii?Q?5jyYzsLLqhu5CDbxd1k/bJ74lxsLUmJNpg1XK/VJVxfWDdt7ktXL79qvyJs1?= =?us-ascii?Q?mcs0qRg1YqKQ2H8+trYGL9EdT9s/AzGdEWtKPwBbqOmQckzAmQ0T1kzapJaD?= =?us-ascii?Q?Bz0AhegjOQw9IzggRDiQBDqXPvYaxIxbIuabHTDZUDBw0znwHkGwNGfTnb+K?= =?us-ascii?Q?sryapWoH0gyjvWsgyqqrGHZI0ZnqA1TbMuaH?= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(376014)(7416014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Jun 2025 14:15:07.8648 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0cce0bc7-6446-42e8-7a35-08ddace032b3 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF0000000F.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB8288 Content-Type: text/plain; charset="utf-8" From: Dragos Tatulea This allows calling page_to_netmem() with a const page * argument. Signed-off-by: Dragos Tatulea Reviewed-by: Mina Almasry Reviewed-by: Cosmin Ratiu Signed-off-by: Mark Bloch --- include/net/netmem.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/net/netmem.h b/include/net/netmem.h index 386164fb9c18..caf2e773c915 100644 --- a/include/net/netmem.h +++ b/include/net/netmem.h @@ -143,7 +143,7 @@ static inline netmem_ref net_iov_to_netmem(struct net_i= ov *niov) return (__force netmem_ref)((unsigned long)niov | NET_IOV); } =20 -static inline netmem_ref page_to_netmem(struct page *page) +static inline netmem_ref page_to_netmem(const struct page *page) { return (__force netmem_ref)page; } --=20 2.34.1 From nobody Thu Sep 25 21:08:12 2025 Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2040.outbound.protection.outlook.com [40.107.93.40]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9C2421DEFD2; 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" , Simon Horman CC: , , , , Leon Romanovsky , "Jesper Dangaard Brouer" , Ilias Apalodimas , Richard Cochran , Alexei Starovoitov , Daniel Borkmann , John Fastabend , Stanislav Fomichev , , , , , Dragos Tatulea , Cosmin Ratiu , Mina Almasry , Mark Bloch Subject: [PATCH net-next v6 02/12] net: Add skb_can_coalesce for netmem Date: Mon, 16 Jun 2025 17:14:31 +0300 Message-ID: <20250616141441.1243044-3-mbloch@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250616141441.1243044-1-mbloch@nvidia.com> References: <20250616141441.1243044-1-mbloch@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF0000C37E:EE_|PH7PR12MB5999:EE_ X-MS-Office365-Filtering-Correlation-Id: 3e7e70da-5e27-4105-8bb4-08ddace03b12 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|82310400026|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?OEUlX36NNM82/1qP3BKkup/kbUpao9jqEANL4c36XfWyiyP2fcFlTOdXZ2mw?= =?us-ascii?Q?ctiYL1G7EA+VmPXM4S9qMVqZMNGyEfA1a9HF7CFWx34EsmbvuxICN9v2XqRj?= =?us-ascii?Q?XO+glCvSkhaYreLoDhVDGIcz2vqxnmtchJ4DR/IixNY1tT/2RTbP4RfEwLuF?= =?us-ascii?Q?X6WwOUZkLwH7TrELqe0tt2HRJ64dfF8lOCR8Jquz08daxLdcenVniWGF7Qhq?= =?us-ascii?Q?8if8ys8IQuzPGk27ulNwd7Og65bKHfHWT9vo0vVHcMPaMmZxha5HPZC+B0W5?= =?us-ascii?Q?vb6UHws0nnDBfiHI6gAaG56a8p9Rjxk5Wrf4ZRttJNFAGVnQ23+jPd26pdvA?= =?us-ascii?Q?H3EnwAmrpG4dyS2m2fNlRJhlbjUsXJYWe8tCL34VUcyGC+jx+Tbt44VsS62T?= =?us-ascii?Q?yQTIwBUQRp92WcKxyxNZZWVlSb0z1C5zO6QfAfehewPyFHni5khM026Mm/Bz?= =?us-ascii?Q?k0zojUX6sjmjYyXFbBI8ZrEZGXIcbEJ8ua7v9QE2pN7LhHU1G+5W8g5JuRt/?= =?us-ascii?Q?OqxqG3sr7mq1lAQemA50J0upVFWlmA7FsYpVNCmTZikEXwn8hct+1j++h3aQ?= =?us-ascii?Q?EHWdZA0z/uqfn0FcMyBoGKUopOthZC0s+9nM3plCNPIIZbAeyccHWfn6/HCU?= =?us-ascii?Q?y0xzoyEjc/fblXD5a17+TDT5j6CTqBhAqBUIduDFubeJzwi2QPZONVFZ1dk/?= =?us-ascii?Q?W9Kp2djd87FB56VBVU+YXCord9WT0rgje4/mcuHCfR79/Zq8TFsTt3Nj96BO?= =?us-ascii?Q?mVeFtkeSRAl6C72kyefFxoTCKz1RvllDwl1RelBNA6wQwDD/dYjUjgWoYiDn?= =?us-ascii?Q?5i3mfLCUKBHXectdshUU0WLYkL3/1aS2RYF684xKQNcBM/TMGH1PdM1rn/JC?= =?us-ascii?Q?UhwtTi3SXzWLQSlNsxNe+gC/Yie9Y1l2Xz+774XFxPvUq30j8nBakqjw4y1w?= =?us-ascii?Q?+FV15Ji/MqjZq57TDePU4RDLEt925ea8nRdXhDjw2Gtz3t0F8XWiLWec71F2?= =?us-ascii?Q?9E0EjRV4PY0jl7437X8+g8dEMpUYheoocqojiCG3KonA5A8+wRpgf8hksO8J?= =?us-ascii?Q?BlRvmz5HtiWvu/jLSNuzLfvfS/YCmP4qF/8D6HbzRtvjl0AQOF288X471gIi?= =?us-ascii?Q?2ABFTMfySlTosMC5NWrVUqWjaI9Sb5/SObK64POzD+1YLp0mMKUQ0rWjqfeH?= =?us-ascii?Q?iOjLFEcU9h9rAMaAyMuqdNeL4CAZdwNm1sY6cxlDiM4lq8uzdOPyCQktNI/c?= =?us-ascii?Q?Vcja8za8tY3CdcB1kzR8tFT8kyycwZupQmi7ZCGL7erte7w4RBdTN8bBAFGX?= =?us-ascii?Q?3mzOkqxkHtX10TssmZJm4uwwTtAERiFsuIYv9kPcpclT+fONGaSABDlPyPIp?= =?us-ascii?Q?wGIEkxQ1uZe9ckVgRe6VXCdgm/6O7a2l7okdlFtTRfmHyuLi7FJIUOg+gsgE?= =?us-ascii?Q?moHRcRr7uEecRvlYF5ejlDsNbto/SH8u0wIXqLSwNHrpdgiJ1A2V3CoToPA0?= =?us-ascii?Q?feB6sz0ttO97soRBJTyzJqmXPGKlD3IF9etT?= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(376014)(82310400026)(36860700013)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Jun 2025 14:15:21.8896 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3e7e70da-5e27-4105-8bb4-08ddace03b12 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF0000C37E.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB5999 Content-Type: text/plain; charset="utf-8" From: Dragos Tatulea Allow drivers that have moved over to netmem to do fragment coalescing. Signed-off-by: Dragos Tatulea Signed-off-by: Cosmin Ratiu Reviewed-by: Tariq Toukan Reviewed-by: Mina Almasry Signed-off-by: Mark Bloch --- include/linux/skbuff.h | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/include/linux/skbuff.h b/include/linux/skbuff.h index 5520524c93bf..9508968cb300 100644 --- a/include/linux/skbuff.h +++ b/include/linux/skbuff.h @@ -3873,20 +3873,26 @@ static inline int __must_check skb_put_padto(struct= sk_buff *skb, unsigned int l bool csum_and_copy_from_iter_full(void *addr, size_t bytes, __wsum *csum, = struct iov_iter *i) __must_check; =20 -static inline bool skb_can_coalesce(struct sk_buff *skb, int i, - const struct page *page, int off) +static inline bool skb_can_coalesce_netmem(struct sk_buff *skb, int i, + netmem_ref netmem, int off) { if (skb_zcopy(skb)) return false; if (i) { const skb_frag_t *frag =3D &skb_shinfo(skb)->frags[i - 1]; =20 - return page =3D=3D skb_frag_page(frag) && + return netmem =3D=3D skb_frag_netmem(frag) && off =3D=3D skb_frag_off(frag) + skb_frag_size(frag); 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" , Simon Horman CC: , , , , Leon Romanovsky , "Jesper Dangaard Brouer" , Ilias Apalodimas , Richard Cochran , Alexei Starovoitov , Daniel Borkmann , John Fastabend , Stanislav Fomichev , , , , , Dragos Tatulea , Mina Almasry , Mark Bloch Subject: [PATCH net-next v6 03/12] page_pool: Add page_pool_dev_alloc_netmems helper Date: Mon, 16 Jun 2025 17:14:32 +0300 Message-ID: <20250616141441.1243044-4-mbloch@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250616141441.1243044-1-mbloch@nvidia.com> References: <20250616141441.1243044-1-mbloch@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF0000C37B:EE_|BL3PR12MB6428:EE_ X-MS-Office365-Filtering-Correlation-Id: 9533faf8-98bb-421a-2fd5-08ddace03ff3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|82310400026|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?40Hjao8peWqM+YIeJwih9mWN+7kRRMioIZFweqHKKWtnoSihpoIFYPmjAXIk?= =?us-ascii?Q?iVOcfUlNnxTbRRYAYE8xKGjiD2vywmrWX+WejaLPeIRkdrTLPqbS90FyQB36?= =?us-ascii?Q?ey4WEo3BH12Ft6rJo81AKiv3e1X6EdFIy6kV6dAmnM2Lova4czFYPyPqEz+Z?= =?us-ascii?Q?lkl71wI6QgHObz1owFWjy9xsGBLQoXwPWXFj8lej00kVhcdC6/TmIp/9XpbD?= =?us-ascii?Q?Tqsj+BaMoF7rx5PAM4gPAqSLfIf7OaH4BMXK/+gOXfx8V1VTqS0lIc/nnqoq?= =?us-ascii?Q?Rl+7Lerutpcczz+GAp+i9LhjKJqmYn0jo/SIF/MbAEZrG1VyF3nCjcgNdjFH?= =?us-ascii?Q?W0Uz7VcnDMGc/H5bejbWAHp2+mAadEZ88DDdD/xDQMqZg0lX95QZDSmQsbYy?= =?us-ascii?Q?s8gS4KeZZWYY7UH7lCySn4wjvvNsFZoTUR8b/hOyKhakyiryiyYaiAKOfKSD?= =?us-ascii?Q?b6grpyaO41qtbM82WFoWiudCyeWMY83SOTyJG+wo5ugfyEsjqNL8TA8TLL0e?= =?us-ascii?Q?legUyDkuudJYtDLrHwmJBlcAyETAzjxinnf4lRsCew50eWIFvwQW1VHc2u8F?= =?us-ascii?Q?IZfZu+V1ykPMIiPnCYrQv+BAbndUlC9Mz7zfG8nwSiVrI+hQF90bU2cmT3eu?= =?us-ascii?Q?OHt7slVfDIqZ8e06BuIdASHukp3yynZR0MOq6EH9A2MdLqRqvShzcg5MIZpc?= =?us-ascii?Q?UmPe5iY3IbXVSIiAPpl2viFpv8J4XXx+PnoO9F+YEs4YYLm7G98H+SxdbTYl?= =?us-ascii?Q?I4wNTt0rUb+f8rzH154IIl/SdrP3yu18GUDZevbfBosqV2DqemSG0RfM1Rq9?= =?us-ascii?Q?FnDBZevgW9ClnBuDc6sB6NpbFLdsjrEzUWTeTZFYIdappU9ELkhTI3Ub1pJq?= =?us-ascii?Q?bi4qs8RMr/wILp75QPPIJTSXO0OhottLBqKo/JrcmNp+mkcCTtjPCf+IzmmP?= =?us-ascii?Q?oTq7nMAry9ZWV0+ZzyrsYOH1rNFjZBOJrGK85TkpJAxg9PZccPPZ8+XIXIHi?= =?us-ascii?Q?Ki6AM4eiouSsEfPLBdy/DgHTl7THjoAA8xqN4sIUTLSvyN1LfyIDtzcBsuvb?= =?us-ascii?Q?l+H+KUpDhY/lyVffOUGeXFs58OG8p4yEDYNaNJMNLNwvTxzaZ71DhjjDijw6?= =?us-ascii?Q?8Mr1f5qZC4TynvItEihCX467uuO4Fc5uhsefYCedihq5PMae3t9tPI50zICG?= =?us-ascii?Q?z/uvRALNt6QvQvuMFB+NO75CanlgFX5Io4Zdpa3td5/QKe4iiNcAqI8KgKZE?= =?us-ascii?Q?0zBm2ybI5HwFSCApaI5tOCsbOsCZQPesZ6MFKFrzJu0z6e+IONHc80D/s4gr?= =?us-ascii?Q?74pPyEk52OgdLZiDlegoffVNm1er0JQTM7VX9dsGnrvBvSJI5pRvTHR3L7YQ?= =?us-ascii?Q?KqEQg1NkVyLOai1Z8IiO+bqE26jmM8j0DWKIlrgaKHOw/9OORURppdKFT8FL?= =?us-ascii?Q?cZuGLsjs1B/9Gj/HNXHZOcyu5A37d5e5i6meFs9DSA/v2p9ftSCrjWJRz1p6?= =?us-ascii?Q?q59n6smXo9zLrpyNUHmC5MRB7Nlifmj9NgR0?= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(376014)(82310400026)(36860700013)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Jun 2025 14:15:30.0488 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9533faf8-98bb-421a-2fd5-08ddace03ff3 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF0000C37B.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL3PR12MB6428 Content-Type: text/plain; charset="utf-8" From: Dragos Tatulea This is the netmem counterpart of page_pool_dev_alloc_pages() which uses the default GFP flags for RX. Signed-off-by: Dragos Tatulea Reviewed-by: Mina Almasry Signed-off-by: Mark Bloch --- include/net/page_pool/helpers.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/include/net/page_pool/helpers.h b/include/net/page_pool/helper= s.h index 93f2c31baf9b..773fc65780b5 100644 --- a/include/net/page_pool/helpers.h +++ b/include/net/page_pool/helpers.h @@ -153,6 +153,13 @@ static inline netmem_ref page_pool_dev_alloc_netmem(st= ruct page_pool *pool, return page_pool_alloc_netmem(pool, offset, size, gfp); } =20 +static inline netmem_ref page_pool_dev_alloc_netmems(struct page_pool *poo= l) +{ + gfp_t gfp =3D GFP_ATOMIC | __GFP_NOWARN; + + return page_pool_alloc_netmems(pool, gfp); +} + static inline struct page *page_pool_alloc(struct page_pool *pool, unsigned int *offset, unsigned int *size, gfp_t gfp) --=20 2.34.1 From nobody Thu Sep 25 21:08:12 2025 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2070.outbound.protection.outlook.com [40.107.94.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 606F31FBCB2; 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" , Simon Horman CC: , , , , Leon Romanovsky , "Jesper Dangaard Brouer" , Ilias Apalodimas , Richard Cochran , Alexei Starovoitov , Daniel Borkmann , John Fastabend , Stanislav Fomichev , , , , , Dragos Tatulea , Cosmin Ratiu , Mark Bloch Subject: [PATCH net-next v6 04/12] net/mlx5e: SHAMPO: Reorganize mlx5_rq_shampo_alloc Date: Mon, 16 Jun 2025 17:14:33 +0300 Message-ID: <20250616141441.1243044-5-mbloch@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250616141441.1243044-1-mbloch@nvidia.com> References: <20250616141441.1243044-1-mbloch@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PEPF0000000F:EE_|BL3PR12MB6570:EE_ X-MS-Office365-Filtering-Correlation-Id: 726a3fc4-ddb0-43e4-aab6-08ddace04290 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|82310400026|7416014|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?tqYtNpD6IvubCtjVneyoSg8PHBKeBVrih8g5Zmqg52gofrUDW0oyCU7iJV7o?= =?us-ascii?Q?y0bcj8cE9iHfGM2U+u/SwvDTy01OfVP/uLxvidm5RgVgv8yanrsc/bWwoNGG?= =?us-ascii?Q?PcLTmkaXWBHdVDQQGKivsYGzWGUOdgK2h2H3twijIGKKQKscsI/W05cliRRx?= =?us-ascii?Q?Ve+F1sr312/jtMeMkEQoeUu+gwuiFHLD7s+dCyXt9yFoluvwISrU7YbX1gQu?= =?us-ascii?Q?WCY16/zkQFnkgNLNYFiVM9FbVko6tN8O6yuP6jqvxbXjSTzE5/YoVgVpJL37?= =?us-ascii?Q?P8F2DR9/K4JWjYpPchb0YXrS2+qBl6HZVcjVQuchBr5UQl/6cB3aaMjjHqrg?= =?us-ascii?Q?5SsEvbUP4nx/FLNLAW5gpvY0tXtE718TD8Hu2hMS20y/AA5fJesk1cDMs6lE?= =?us-ascii?Q?MHymvnlTLDV7C8kt+O0ynSxLurK7bLCrqVa9PrMlvzjMMnV0f6+pvvhxgOAu?= =?us-ascii?Q?TwBFBj4YqVY6eiNpSrUA3eWRLsi6a+7dCgOVcn1weJN9040rK2xckI6LiTag?= =?us-ascii?Q?nVACkkM413kC7ItEYKvifcTKta5otBz5R8L4qxdt8gxth0W7KGq98pLM6SFT?= =?us-ascii?Q?Q/jh8Q/JQp/DBC4vWda/+cGEeSILD73D03di/gV80/xJYBl+HSPIzINvMtPE?= =?us-ascii?Q?zfXQWqWB6++wjpDwnQxByz4tY+XC1+eEMSQtuhcPx/w6T+qzHOoTR7KJ8Lg1?= =?us-ascii?Q?UD+tKOX6NpEUblvcfcaUnkJZQCjJiH7EzY8pRqIgCVcKss1kpSpCMWaCBnhp?= =?us-ascii?Q?AN8wPxYUqiutHlKaM8MydlggW1oKoQCahWIyLYtiJwWjTairDYZRN5drx5DL?= =?us-ascii?Q?VRDJow2e9kr8LYQpTCqKESSdhDS/QteM8Gq1SF2Fs/RiDST/BfcTPM5iE9Fr?= =?us-ascii?Q?58xk6rhV2fqYQqKCECwhxRQYeXu+UY4zEbe782pu6xYzISZQIH294Xm3tAFZ?= =?us-ascii?Q?hx9zCsUlldSvJvFJ/89GRuHOpJ62TM2GNdYcBoCKmuqyzIchg/Uuz+PZD+Rc?= =?us-ascii?Q?u7tmxr+uEu2zzaPN7FhgEi5T3k/xg54pe4YR+aXmguP2ggVHBEJ7i8PlkaDs?= =?us-ascii?Q?o+ZrtxinOtg3rw857owFRgetnyYe431BdgvS5JabXN8ECUp2HG5KDNxEFzye?= =?us-ascii?Q?+QMVoMeVKHaceswaKselBNrzbEwj403ETMwlkABpHog7H0mv/MDMNihHZnH4?= =?us-ascii?Q?ibDR8kmDxsckl2scyJo4oEsm6UrHNqJ0R/UTmJZzk+awO/TZLTArZxF2PFqY?= =?us-ascii?Q?HE3WYaczKVnrcXhOe2eeruvopsB84oI26q7UfzpUTMYn7htRp7p7R5Z9uOWW?= =?us-ascii?Q?KfJfnT/NSX4OHKU+MpKLwMau9GxKBx5ciLrUVDt03V/4HfNvNkzeg7U5vp0t?= =?us-ascii?Q?ed2lWuZGbvu6Wou70VBpEPV7z+kWTNTbB7dmFlkjSb3D4K9mbY1U8LIm7V8b?= =?us-ascii?Q?lnHGtdPbLqpLoTt+UjFMfjj2LWkU4+v5SXDW4tW4uOu0BsvdZHV4nhFP3Dxe?= =?us-ascii?Q?JKoIEG5k7o0qH1dlLqbxzbasL9dnGj1kfcm3?= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(82310400026)(7416014)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Jun 2025 14:15:34.4120 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 726a3fc4-ddb0-43e4-aab6-08ddace04290 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF0000000F.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL3PR12MB6570 Content-Type: text/plain; charset="utf-8" From: Saeed Mahameed Drop redundant SHAMPO structure alloc/free functions. Gather together function calls pertaining to header split info, pass header per WQE (hd_per_wqe) as parameter to those function to avoid use before initialization future mistakes. Allocate HW GRO related info outside of the header related info scope. Signed-off-by: Saeed Mahameed Reviewed-by: Dragos Tatulea Signed-off-by: Cosmin Ratiu Reviewed-by: Tariq Toukan Signed-off-by: Mark Bloch --- drivers/net/ethernet/mellanox/mlx5/core/en.h | 1 - .../net/ethernet/mellanox/mlx5/core/en_main.c | 135 +++++++++--------- 2 files changed, 66 insertions(+), 70 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en.h b/drivers/net/eth= ernet/mellanox/mlx5/core/en.h index 5b0d03b3efe8..211ea429ea89 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en.h @@ -638,7 +638,6 @@ struct mlx5e_shampo_hd { struct mlx5e_frag_page *pages; u32 hd_per_wq; u16 hd_per_wqe; - u16 pages_per_wq; unsigned long *bitmap; u16 pi; u16 ci; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/en_main.c index ea822c69d137..3d11c9f87171 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -331,47 +331,6 @@ static inline void mlx5e_build_umr_wqe(struct mlx5e_rq= *rq, ucseg->mkey_mask =3D cpu_to_be64(MLX5_MKEY_MASK_FREE); } =20 -static int mlx5e_rq_shampo_hd_alloc(struct mlx5e_rq *rq, int node) -{ - rq->mpwqe.shampo =3D kvzalloc_node(sizeof(*rq->mpwqe.shampo), - GFP_KERNEL, node); - if (!rq->mpwqe.shampo) - return -ENOMEM; - return 0; -} - -static void mlx5e_rq_shampo_hd_free(struct mlx5e_rq *rq) -{ - kvfree(rq->mpwqe.shampo); -} - -static int mlx5e_rq_shampo_hd_info_alloc(struct mlx5e_rq *rq, int node) -{ - struct mlx5e_shampo_hd *shampo =3D rq->mpwqe.shampo; - - shampo->bitmap =3D bitmap_zalloc_node(shampo->hd_per_wq, GFP_KERNEL, - node); - shampo->pages =3D kvzalloc_node(array_size(shampo->hd_per_wq, - sizeof(*shampo->pages)), - GFP_KERNEL, node); - if (!shampo->bitmap || !shampo->pages) - goto err_nomem; - - return 0; - -err_nomem: - bitmap_free(shampo->bitmap); - kvfree(shampo->pages); - - return -ENOMEM; -} - -static void mlx5e_rq_shampo_hd_info_free(struct mlx5e_rq *rq) -{ - bitmap_free(rq->mpwqe.shampo->bitmap); - kvfree(rq->mpwqe.shampo->pages); -} - static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq, int node) { int wq_sz =3D mlx5_wq_ll_get_size(&rq->mpwqe.wq); @@ -584,19 +543,18 @@ static int mlx5e_create_rq_umr_mkey(struct mlx5_core_= dev *mdev, struct mlx5e_rq } =20 static int mlx5e_create_rq_hd_umr_mkey(struct mlx5_core_dev *mdev, - struct mlx5e_rq *rq) + u16 hd_per_wq, u32 *umr_mkey) { u32 max_ksm_size =3D BIT(MLX5_CAP_GEN(mdev, log_max_klm_list_size)); =20 - if (max_ksm_size < rq->mpwqe.shampo->hd_per_wq) { + if (max_ksm_size < hd_per_wq) { mlx5_core_err(mdev, "max ksm list size 0x%x is smaller than shampo heade= r buffer list size 0x%x\n", - max_ksm_size, rq->mpwqe.shampo->hd_per_wq); + max_ksm_size, hd_per_wq); return -EINVAL; } - - return mlx5e_create_umr_ksm_mkey(mdev, rq->mpwqe.shampo->hd_per_wq, + return mlx5e_create_umr_ksm_mkey(mdev, hd_per_wq, MLX5E_SHAMPO_LOG_HEADER_ENTRY_SIZE, - &rq->mpwqe.shampo->mkey); + umr_mkey); } =20 static void mlx5e_init_frags_partition(struct mlx5e_rq *rq) @@ -758,6 +716,35 @@ static int mlx5e_init_rxq_rq(struct mlx5e_channel *c, = struct mlx5e_params *param xdp_frag_size); } =20 +static int mlx5e_rq_shampo_hd_info_alloc(struct mlx5e_rq *rq, u16 hd_per_w= q, + int node) +{ + struct mlx5e_shampo_hd *shampo =3D rq->mpwqe.shampo; + + shampo->hd_per_wq =3D hd_per_wq; + + shampo->bitmap =3D bitmap_zalloc_node(hd_per_wq, GFP_KERNEL, node); + shampo->pages =3D kvzalloc_node(array_size(hd_per_wq, + sizeof(*shampo->pages)), + GFP_KERNEL, node); + if (!shampo->bitmap || !shampo->pages) + goto err_nomem; + + return 0; + +err_nomem: + kvfree(shampo->pages); + bitmap_free(shampo->bitmap); + + return -ENOMEM; +} + +static void mlx5e_rq_shampo_hd_info_free(struct mlx5e_rq *rq) +{ + kvfree(rq->mpwqe.shampo->pages); + bitmap_free(rq->mpwqe.shampo->bitmap); +} + static int mlx5_rq_shampo_alloc(struct mlx5_core_dev *mdev, struct mlx5e_params *params, struct mlx5e_rq_param *rqp, @@ -765,42 +752,52 @@ static int mlx5_rq_shampo_alloc(struct mlx5_core_dev = *mdev, u32 *pool_size, int node) { + void *wqc =3D MLX5_ADDR_OF(rqc, rqp->rqc, wq); + u16 hd_per_wq; + int wq_size; int err; =20 if (!test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state)) return 0; - err =3D mlx5e_rq_shampo_hd_alloc(rq, node); - if (err) - goto out; - rq->mpwqe.shampo->hd_per_wq =3D - mlx5e_shampo_hd_per_wq(mdev, params, rqp); - err =3D mlx5e_create_rq_hd_umr_mkey(mdev, rq); + + rq->mpwqe.shampo =3D kvzalloc_node(sizeof(*rq->mpwqe.shampo), + GFP_KERNEL, node); + if (!rq->mpwqe.shampo) + return -ENOMEM; + + /* split headers data structures */ + hd_per_wq =3D mlx5e_shampo_hd_per_wq(mdev, params, rqp); + err =3D mlx5e_rq_shampo_hd_info_alloc(rq, hd_per_wq, node); if (err) - goto err_shampo_hd; - err =3D mlx5e_rq_shampo_hd_info_alloc(rq, node); + goto err_shampo_hd_info_alloc; + + err =3D mlx5e_create_rq_hd_umr_mkey(mdev, hd_per_wq, + &rq->mpwqe.shampo->mkey); if (err) - goto err_shampo_info; + goto err_umr_mkey; + + rq->mpwqe.shampo->key =3D cpu_to_be32(rq->mpwqe.shampo->mkey); + rq->mpwqe.shampo->hd_per_wqe =3D + mlx5e_shampo_hd_per_wqe(mdev, params, rqp); + wq_size =3D BIT(MLX5_GET(wq, wqc, log_wq_sz)); + *pool_size +=3D (rq->mpwqe.shampo->hd_per_wqe * wq_size) / + MLX5E_SHAMPO_WQ_HEADER_PER_PAGE; + + /* gro only data structures */ rq->hw_gro_data =3D kvzalloc_node(sizeof(*rq->hw_gro_data), GFP_KERNEL, n= ode); if (!rq->hw_gro_data) { err =3D -ENOMEM; goto err_hw_gro_data; } - rq->mpwqe.shampo->key =3D - cpu_to_be32(rq->mpwqe.shampo->mkey); - rq->mpwqe.shampo->hd_per_wqe =3D - mlx5e_shampo_hd_per_wqe(mdev, params, rqp); - rq->mpwqe.shampo->pages_per_wq =3D - rq->mpwqe.shampo->hd_per_wq / MLX5E_SHAMPO_WQ_HEADER_PER_PAGE; - *pool_size +=3D rq->mpwqe.shampo->pages_per_wq; + return 0; =20 err_hw_gro_data: - mlx5e_rq_shampo_hd_info_free(rq); -err_shampo_info: mlx5_core_destroy_mkey(mdev, rq->mpwqe.shampo->mkey); -err_shampo_hd: - mlx5e_rq_shampo_hd_free(rq); -out: +err_umr_mkey: + mlx5e_rq_shampo_hd_info_free(rq); +err_shampo_hd_info_alloc: + kvfree(rq->mpwqe.shampo); return err; } =20 @@ -812,7 +809,7 @@ static void mlx5e_rq_free_shampo(struct mlx5e_rq *rq) kvfree(rq->hw_gro_data); mlx5e_rq_shampo_hd_info_free(rq); mlx5_core_destroy_mkey(rq->mdev, rq->mpwqe.shampo->mkey); - mlx5e_rq_shampo_hd_free(rq); + kvfree(rq->mpwqe.shampo); } =20 static int mlx5e_alloc_rq(struct mlx5e_params *params, --=20 2.34.1 From nobody Thu Sep 25 21:08:12 2025 Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2085.outbound.protection.outlook.com [40.107.243.85]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 036E11FF1AD; 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Signed-off-by: Saeed Mahameed Reviewed-by: Dragos Tatulea Signed-off-by: Cosmin Ratiu Signed-off-by: Tariq Toukan Signed-off-by: Mark Bloch --- drivers/net/ethernet/mellanox/mlx5/core/en.h | 4 --- .../ethernet/mellanox/mlx5/core/en/params.c | 36 ++++++++++--------- .../net/ethernet/mellanox/mlx5/core/en_main.c | 4 --- 3 files changed, 20 insertions(+), 24 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en.h b/drivers/net/eth= ernet/mellanox/mlx5/core/en.h index 211ea429ea89..581eef34f512 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en.h @@ -278,10 +278,6 @@ enum packet_merge { struct mlx5e_packet_merge_param { enum packet_merge type; u32 timeout; - struct { - u8 match_criteria_type; - u8 alignment_granularity; - } shampo; }; =20 struct mlx5e_params { diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/params.c b/drivers/= net/ethernet/mellanox/mlx5/core/en/params.c index 58ec5e44aa7a..fc945bce933a 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/params.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/params.c @@ -901,6 +901,7 @@ int mlx5e_build_rq_param(struct mlx5_core_dev *mdev, { void *rqc =3D param->rqc; void *wq =3D MLX5_ADDR_OF(rqc, rqc, wq); + u32 lro_timeout; int ndsegs =3D 1; int err; =20 @@ -926,22 +927,25 @@ int mlx5e_build_rq_param(struct mlx5_core_dev *mdev, MLX5_SET(wq, wq, log_wqe_stride_size, log_wqe_stride_size - MLX5_MPWQE_LOG_STRIDE_SZ_BASE); MLX5_SET(wq, wq, log_wq_sz, mlx5e_mpwqe_get_log_rq_size(mdev, params, xs= k)); - if (params->packet_merge.type =3D=3D MLX5E_PACKET_MERGE_SHAMPO) { - MLX5_SET(wq, wq, shampo_enable, true); - MLX5_SET(wq, wq, log_reservation_size, - mlx5e_shampo_get_log_rsrv_size(mdev, params)); - MLX5_SET(wq, wq, - log_max_num_of_packets_per_reservation, - mlx5e_shampo_get_log_pkt_per_rsrv(mdev, params)); - MLX5_SET(wq, wq, log_headers_entry_size, - mlx5e_shampo_get_log_hd_entry_size(mdev, params)); - MLX5_SET(rqc, rqc, reservation_timeout, - mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_SHAMPO_TIMEOUT)); - MLX5_SET(rqc, rqc, shampo_match_criteria_type, - params->packet_merge.shampo.match_criteria_type); - MLX5_SET(rqc, rqc, shampo_no_match_alignment_granularity, - params->packet_merge.shampo.alignment_granularity); - } + if (params->packet_merge.type !=3D MLX5E_PACKET_MERGE_SHAMPO) + break; + + MLX5_SET(wq, wq, shampo_enable, true); + MLX5_SET(wq, wq, log_reservation_size, + mlx5e_shampo_get_log_rsrv_size(mdev, params)); + MLX5_SET(wq, wq, + log_max_num_of_packets_per_reservation, + mlx5e_shampo_get_log_pkt_per_rsrv(mdev, params)); + MLX5_SET(wq, wq, log_headers_entry_size, + mlx5e_shampo_get_log_hd_entry_size(mdev, params)); + lro_timeout =3D + mlx5e_choose_lro_timeout(mdev, + MLX5E_DEFAULT_SHAMPO_TIMEOUT); + MLX5_SET(rqc, rqc, reservation_timeout, lro_timeout); + MLX5_SET(rqc, rqc, shampo_match_criteria_type, + MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED); + MLX5_SET(rqc, rqc, shampo_no_match_alignment_granularity, + MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE); break; } default: /* MLX5_WQ_TYPE_CYCLIC */ diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/en_main.c index 3d11c9f87171..e1e44533b744 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -4040,10 +4040,6 @@ static int set_feature_hw_gro(struct net_device *net= dev, bool enable) =20 if (enable) { new_params.packet_merge.type =3D MLX5E_PACKET_MERGE_SHAMPO; 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No functional change here as all by default disabled features are explicitly disabled at the bottom of the function. Signed-off-by: Saeed Mahameed Reviewed-by: Dragos Tatulea Signed-off-by: Cosmin Ratiu Signed-off-by: Tariq Toukan Signed-off-by: Mark Bloch --- drivers/net/ethernet/mellanox/mlx5/core/en_main.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/en_main.c index e1e44533b744..a81d354af7c8 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -78,7 +78,8 @@ =20 static bool mlx5e_hw_gro_supported(struct mlx5_core_dev *mdev) { - if (!MLX5_CAP_GEN(mdev, shampo)) + if (!MLX5_CAP_GEN(mdev, shampo) || + !MLX5_CAP_SHAMPO(mdev, shampo_header_split_data_merge)) return false; =20 /* Our HW-GRO implementation relies on "KSM Mkey" for @@ -5499,17 +5500,17 @@ static void mlx5e_build_nic_netdev(struct net_devic= e *netdev) MLX5E_MPWRQ_UMR_MODE_ALIGNED)) netdev->vlan_features |=3D NETIF_F_LRO; =20 + if (mlx5e_hw_gro_supported(mdev) && + mlx5e_check_fragmented_striding_rq_cap(mdev, PAGE_SHIFT, + MLX5E_MPWRQ_UMR_MODE_ALIGNED)) + netdev->vlan_features |=3D NETIF_F_GRO_HW; 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This will be useful for adding support to zc page pool, which has to be different from the headers page pool. For now, the pools are the same. Signed-off-by: Saeed Mahameed Reviewed-by: Dragos Tatulea Signed-off-by: Cosmin Ratiu Signed-off-by: Tariq Toukan Signed-off-by: Mark Bloch --- drivers/net/ethernet/mellanox/mlx5/core/en.h | 4 ++ .../net/ethernet/mellanox/mlx5/core/en_main.c | 43 ++++++++++++++++++- .../net/ethernet/mellanox/mlx5/core/en_rx.c | 41 ++++++++++-------- 3 files changed, 69 insertions(+), 19 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en.h b/drivers/net/eth= ernet/mellanox/mlx5/core/en.h index 581eef34f512..c329de1d4f0a 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en.h @@ -716,7 +716,11 @@ struct mlx5e_rq { struct bpf_prog __rcu *xdp_prog; struct mlx5e_xdpsq *xdpsq; DECLARE_BITMAP(flags, 8); + + /* page pools */ struct page_pool *page_pool; + struct page_pool *hd_page_pool; + struct mlx5e_xdp_buff mxbuf; =20 /* AF_XDP zero-copy */ diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/en_main.c index a81d354af7c8..5e649705e35f 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -41,6 +41,7 @@ #include #include #include +#include #include #include #include @@ -746,6 +747,11 @@ static void mlx5e_rq_shampo_hd_info_free(struct mlx5e_= rq *rq) bitmap_free(rq->mpwqe.shampo->bitmap); } =20 +static bool mlx5_rq_needs_separate_hd_pool(struct mlx5e_rq *rq) +{ + return false; +} + static int mlx5_rq_shampo_alloc(struct mlx5_core_dev *mdev, struct mlx5e_params *params, struct mlx5e_rq_param *rqp, @@ -754,6 +760,7 @@ static int mlx5_rq_shampo_alloc(struct mlx5_core_dev *m= dev, int node) { void *wqc =3D MLX5_ADDR_OF(rqc, rqp->rqc, wq); + u32 hd_pool_size; u16 hd_per_wq; int wq_size; int err; @@ -781,8 +788,34 @@ static int mlx5_rq_shampo_alloc(struct mlx5_core_dev *= mdev, rq->mpwqe.shampo->hd_per_wqe =3D mlx5e_shampo_hd_per_wqe(mdev, params, rqp); wq_size =3D BIT(MLX5_GET(wq, wqc, log_wq_sz)); - *pool_size +=3D (rq->mpwqe.shampo->hd_per_wqe * wq_size) / - MLX5E_SHAMPO_WQ_HEADER_PER_PAGE; + hd_pool_size =3D (rq->mpwqe.shampo->hd_per_wqe * wq_size) / + MLX5E_SHAMPO_WQ_HEADER_PER_PAGE; + + if (mlx5_rq_needs_separate_hd_pool(rq)) { + /* Separate page pool for shampo headers */ + struct page_pool_params pp_params =3D { }; + + pp_params.order =3D 0; + pp_params.flags =3D PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV; + pp_params.pool_size =3D hd_pool_size; + pp_params.nid =3D node; + pp_params.dev =3D rq->pdev; + pp_params.napi =3D rq->cq.napi; + pp_params.netdev =3D rq->netdev; + pp_params.dma_dir =3D rq->buff.map_dir; + pp_params.max_len =3D PAGE_SIZE; + + rq->hd_page_pool =3D page_pool_create(&pp_params); + if (IS_ERR(rq->hd_page_pool)) { + err =3D PTR_ERR(rq->hd_page_pool); + rq->hd_page_pool =3D NULL; + goto err_hds_page_pool; + } + } else { + /* Common page pool, reserve space for headers. */ + *pool_size +=3D hd_pool_size; + rq->hd_page_pool =3D NULL; + } =20 /* gro only data structures */ rq->hw_gro_data =3D kvzalloc_node(sizeof(*rq->hw_gro_data), GFP_KERNEL, n= ode); @@ -794,6 +827,8 @@ static int mlx5_rq_shampo_alloc(struct mlx5_core_dev *m= dev, return 0; =20 err_hw_gro_data: + page_pool_destroy(rq->hd_page_pool); +err_hds_page_pool: mlx5_core_destroy_mkey(mdev, rq->mpwqe.shampo->mkey); err_umr_mkey: mlx5e_rq_shampo_hd_info_free(rq); @@ -808,6 +843,8 @@ static void mlx5e_rq_free_shampo(struct mlx5e_rq *rq) return; =20 kvfree(rq->hw_gro_data); + if (rq->hd_page_pool !=3D rq->page_pool) + page_pool_destroy(rq->hd_page_pool); mlx5e_rq_shampo_hd_info_free(rq); mlx5_core_destroy_mkey(rq->mdev, rq->mpwqe.shampo->mkey); kvfree(rq->mpwqe.shampo); @@ -939,6 +976,8 @@ static int mlx5e_alloc_rq(struct mlx5e_params *params, rq->page_pool =3D NULL; goto err_free_by_rq_type; } + if (!rq->hd_page_pool) + rq->hd_page_pool =3D rq->page_pool; if (xdp_rxq_info_is_reg(&rq->xdp_rxq)) err =3D xdp_rxq_info_reg_mem_model(&rq->xdp_rxq, MEM_TYPE_PAGE_POOL, rq->page_pool); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c b/drivers/net/= ethernet/mellanox/mlx5/core/en_rx.c index 84b1ab8233b8..e34ef53ebd0e 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c @@ -273,12 +273,12 @@ static inline u32 mlx5e_decompress_cqes_start(struct = mlx5e_rq *rq, =20 #define MLX5E_PAGECNT_BIAS_MAX (PAGE_SIZE / 64) =20 -static int mlx5e_page_alloc_fragmented(struct mlx5e_rq *rq, +static int mlx5e_page_alloc_fragmented(struct page_pool *pool, struct mlx5e_frag_page *frag_page) { struct page *page; =20 - page =3D page_pool_dev_alloc_pages(rq->page_pool); + page =3D page_pool_dev_alloc_pages(pool); if (unlikely(!page)) return -ENOMEM; =20 @@ -292,14 +292,14 @@ static int mlx5e_page_alloc_fragmented(struct mlx5e_r= q *rq, return 0; } =20 -static void mlx5e_page_release_fragmented(struct mlx5e_rq *rq, +static void mlx5e_page_release_fragmented(struct page_pool *pool, struct mlx5e_frag_page *frag_page) { u16 drain_count =3D MLX5E_PAGECNT_BIAS_MAX - frag_page->frags; struct page *page =3D frag_page->page; =20 if (page_pool_unref_page(page, drain_count) =3D=3D 0) - page_pool_put_unrefed_page(rq->page_pool, page, -1, true); + page_pool_put_unrefed_page(pool, page, -1, true); } =20 static inline int mlx5e_get_rx_frag(struct mlx5e_rq *rq, @@ -313,7 +313,8 @@ static inline int mlx5e_get_rx_frag(struct mlx5e_rq *rq, * offset) should just use the new one without replenishing again * by themselves. */ - err =3D mlx5e_page_alloc_fragmented(rq, frag->frag_page); + err =3D mlx5e_page_alloc_fragmented(rq->page_pool, + frag->frag_page); =20 return err; } @@ -332,7 +333,7 @@ static inline void mlx5e_put_rx_frag(struct mlx5e_rq *r= q, struct mlx5e_wqe_frag_info *frag) { if (mlx5e_frag_can_release(frag)) - mlx5e_page_release_fragmented(rq, frag->frag_page); + mlx5e_page_release_fragmented(rq->page_pool, frag->frag_page); } =20 static inline struct mlx5e_wqe_frag_info *get_frag(struct mlx5e_rq *rq, u1= 6 ix) @@ -584,7 +585,8 @@ mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_m= pw_info *wi) struct mlx5e_frag_page *frag_page; =20 frag_page =3D &wi->alloc_units.frag_pages[i]; - mlx5e_page_release_fragmented(rq, frag_page); + mlx5e_page_release_fragmented(rq->page_pool, + frag_page); } } } @@ -679,11 +681,10 @@ static int mlx5e_build_shampo_hd_umr(struct mlx5e_rq = *rq, struct mlx5e_frag_page *frag_page =3D mlx5e_shampo_hd_to_frag_page(rq, i= ndex); u64 addr; =20 - err =3D mlx5e_page_alloc_fragmented(rq, frag_page); + err =3D mlx5e_page_alloc_fragmented(rq->hd_page_pool, frag_page); if (unlikely(err)) goto err_unmap; =20 - addr =3D page_pool_get_dma_addr(frag_page->page); =20 for (int j =3D 0; j < MLX5E_SHAMPO_WQ_HEADER_PER_PAGE; j++) { @@ -715,7 +716,8 @@ static int mlx5e_build_shampo_hd_umr(struct mlx5e_rq *r= q, if (!header_offset) { struct mlx5e_frag_page *frag_page =3D mlx5e_shampo_hd_to_frag_page(rq, = index); =20 - mlx5e_page_release_fragmented(rq, frag_page); + mlx5e_page_release_fragmented(rq->hd_page_pool, + frag_page); } } =20 @@ -791,7 +793,7 @@ static int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, u1= 6 ix) for (i =3D 0; i < rq->mpwqe.pages_per_wqe; i++, frag_page++) { dma_addr_t addr; =20 - err =3D mlx5e_page_alloc_fragmented(rq, frag_page); + err =3D mlx5e_page_alloc_fragmented(rq->page_pool, frag_page); if (unlikely(err)) goto err_unmap; addr =3D page_pool_get_dma_addr(frag_page->page); @@ -836,7 +838,7 @@ static int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, u1= 6 ix) err_unmap: while (--i >=3D 0) { frag_page--; - mlx5e_page_release_fragmented(rq, frag_page); + mlx5e_page_release_fragmented(rq->page_pool, frag_page); } =20 bitmap_fill(wi->skip_release_bitmap, rq->mpwqe.pages_per_wqe); @@ -855,7 +857,7 @@ mlx5e_free_rx_shampo_hd_entry(struct mlx5e_rq *rq, u16 = header_index) if (((header_index + 1) & (MLX5E_SHAMPO_WQ_HEADER_PER_PAGE - 1)) =3D=3D 0= ) { struct mlx5e_frag_page *frag_page =3D mlx5e_shampo_hd_to_frag_page(rq, h= eader_index); =20 - mlx5e_page_release_fragmented(rq, frag_page); + mlx5e_page_release_fragmented(rq->hd_page_pool, frag_page); } clear_bit(header_index, shampo->bitmap); } @@ -1100,6 +1102,8 @@ INDIRECT_CALLABLE_SCOPE bool mlx5e_post_rx_mpwqes(str= uct mlx5e_rq *rq) =20 if (rq->page_pool) page_pool_nid_changed(rq->page_pool, numa_mem_id()); + if (rq->hd_page_pool) + page_pool_nid_changed(rq->hd_page_pool, numa_mem_id()); =20 head =3D rq->mpwqe.actual_wq_head; i =3D missing; @@ -2004,7 +2008,8 @@ mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq *r= q, struct mlx5e_mpw_info *w if (prog) { /* area for bpf_xdp_[store|load]_bytes */ net_prefetchw(page_address(frag_page->page) + frag_offset); - if (unlikely(mlx5e_page_alloc_fragmented(rq, &wi->linear_page))) { + if (unlikely(mlx5e_page_alloc_fragmented(rq->page_pool, + &wi->linear_page))) { rq->stats->buff_alloc_err++; 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SHAMPO can issue packets that are not split into header and data. These packets will be dropped if the data part resides in a net_iov as the driver can't read into this area. No performance degradation observed. Signed-off-by: Saeed Mahameed Signed-off-by: Dragos Tatulea Reviewed-by: Dragos Tatulea Reviewed-by: Tariq Toukan Reviewed-by: Mina Almasry Signed-off-by: Mark Bloch --- drivers/net/ethernet/mellanox/mlx5/core/en.h | 2 +- .../net/ethernet/mellanox/mlx5/core/en_rx.c | 105 +++++++++++------- 2 files changed, 63 insertions(+), 44 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en.h b/drivers/net/eth= ernet/mellanox/mlx5/core/en.h index c329de1d4f0a..65a73913b9a2 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en.h @@ -553,7 +553,7 @@ struct mlx5e_icosq { } ____cacheline_aligned_in_smp; =20 struct mlx5e_frag_page { - struct page *page; + netmem_ref netmem; u16 frags; }; =20 diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c b/drivers/net/= ethernet/mellanox/mlx5/core/en_rx.c index e34ef53ebd0e..2bb32082bfcc 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c @@ -273,33 +273,32 @@ static inline u32 mlx5e_decompress_cqes_start(struct = mlx5e_rq *rq, =20 #define MLX5E_PAGECNT_BIAS_MAX (PAGE_SIZE / 64) =20 -static int mlx5e_page_alloc_fragmented(struct page_pool *pool, +static int mlx5e_page_alloc_fragmented(struct page_pool *pp, struct mlx5e_frag_page *frag_page) { - struct page *page; + netmem_ref netmem =3D page_pool_dev_alloc_netmems(pp); =20 - page =3D page_pool_dev_alloc_pages(pool); - if (unlikely(!page)) + if (unlikely(!netmem)) return -ENOMEM; =20 - page_pool_fragment_page(page, MLX5E_PAGECNT_BIAS_MAX); + page_pool_fragment_netmem(netmem, MLX5E_PAGECNT_BIAS_MAX); =20 *frag_page =3D (struct mlx5e_frag_page) { - .page =3D page, + .netmem =3D netmem, .frags =3D 0, }; =20 return 0; } =20 -static void mlx5e_page_release_fragmented(struct page_pool *pool, +static void mlx5e_page_release_fragmented(struct page_pool *pp, struct mlx5e_frag_page *frag_page) { u16 drain_count =3D MLX5E_PAGECNT_BIAS_MAX - frag_page->frags; - struct page *page =3D frag_page->page; + netmem_ref netmem =3D frag_page->netmem; =20 - if (page_pool_unref_page(page, drain_count) =3D=3D 0) - page_pool_put_unrefed_page(pool, page, -1, true); + if (page_pool_unref_netmem(netmem, drain_count) =3D=3D 0) + page_pool_put_unrefed_netmem(pp, netmem, -1, true); } =20 static inline int mlx5e_get_rx_frag(struct mlx5e_rq *rq, @@ -359,7 +358,7 @@ static int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, stru= ct mlx5e_rx_wqe_cyc *wqe, frag->flags &=3D ~BIT(MLX5E_WQE_FRAG_SKIP_RELEASE); =20 headroom =3D i =3D=3D 0 ? rq->buff.headroom : 0; - addr =3D page_pool_get_dma_addr(frag->frag_page->page); + addr =3D page_pool_get_dma_addr_netmem(frag->frag_page->netmem); wqe->data[i].addr =3D cpu_to_be64(addr + frag->offset + headroom); } =20 @@ -500,9 +499,10 @@ mlx5e_add_skb_shared_info_frag(struct mlx5e_rq *rq, st= ruct skb_shared_info *sinf struct xdp_buff *xdp, struct mlx5e_frag_page *frag_page, u32 frag_offset, u32 len) { + netmem_ref netmem =3D frag_page->netmem; skb_frag_t *frag; =20 - dma_addr_t addr =3D page_pool_get_dma_addr(frag_page->page); + dma_addr_t addr =3D page_pool_get_dma_addr_netmem(netmem); =20 dma_sync_single_for_cpu(rq->pdev, addr + frag_offset, len, rq->buff.map_d= ir); if (!xdp_buff_has_frags(xdp)) { @@ -515,9 +515,9 @@ mlx5e_add_skb_shared_info_frag(struct mlx5e_rq *rq, str= uct skb_shared_info *sinf } =20 frag =3D &sinfo->frags[sinfo->nr_frags++]; - skb_frag_fill_page_desc(frag, frag_page->page, frag_offset, len); + skb_frag_fill_netmem_desc(frag, netmem, frag_offset, len); =20 - if (page_is_pfmemalloc(frag_page->page)) + if (netmem_is_pfmemalloc(netmem)) xdp_buff_set_frag_pfmemalloc(xdp); sinfo->xdp_frags_size +=3D len; } @@ -528,27 +528,29 @@ mlx5e_add_skb_frag(struct mlx5e_rq *rq, struct sk_buf= f *skb, u32 frag_offset, u32 len, unsigned int truesize) { - dma_addr_t addr =3D page_pool_get_dma_addr(frag_page->page); + dma_addr_t addr =3D page_pool_get_dma_addr_netmem(frag_page->netmem); u8 next_frag =3D skb_shinfo(skb)->nr_frags; + netmem_ref netmem =3D frag_page->netmem; =20 dma_sync_single_for_cpu(rq->pdev, addr + frag_offset, len, rq->buff.map_dir); =20 - if (skb_can_coalesce(skb, next_frag, frag_page->page, frag_offset)) { + if (skb_can_coalesce_netmem(skb, next_frag, netmem, frag_offset)) { skb_coalesce_rx_frag(skb, next_frag - 1, len, truesize); - } else { - frag_page->frags++; - skb_add_rx_frag(skb, next_frag, frag_page->page, - frag_offset, len, truesize); + return; } + + frag_page->frags++; + skb_add_rx_frag_netmem(skb, next_frag, netmem, + frag_offset, len, truesize); } =20 static inline void mlx5e_copy_skb_header(struct mlx5e_rq *rq, struct sk_buff *skb, - struct page *page, dma_addr_t addr, + netmem_ref netmem, dma_addr_t addr, int offset_from, int dma_offset, u32 headlen) { - const void *from =3D page_address(page) + offset_from; + const void *from =3D netmem_address(netmem) + offset_from; /* Aligning len to sizeof(long) optimizes memcpy performance */ unsigned int len =3D ALIGN(headlen, sizeof(long)); =20 @@ -685,7 +687,7 @@ static int mlx5e_build_shampo_hd_umr(struct mlx5e_rq *r= q, if (unlikely(err)) goto err_unmap; =20 - addr =3D page_pool_get_dma_addr(frag_page->page); + addr =3D page_pool_get_dma_addr_netmem(frag_page->netmem); =20 for (int j =3D 0; j < MLX5E_SHAMPO_WQ_HEADER_PER_PAGE; j++) { header_offset =3D mlx5e_shampo_hd_offset(index++); @@ -796,7 +798,8 @@ static int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, u1= 6 ix) err =3D mlx5e_page_alloc_fragmented(rq->page_pool, frag_page); if (unlikely(err)) goto err_unmap; - addr =3D page_pool_get_dma_addr(frag_page->page); + + addr =3D page_pool_get_dma_addr_netmem(frag_page->netmem); umr_wqe->inline_mtts[i] =3D (struct mlx5_mtt) { .ptag =3D cpu_to_be64(addr | MLX5_EN_WR), }; @@ -1216,7 +1219,7 @@ static void *mlx5e_shampo_get_packet_hd(struct mlx5e_= rq *rq, u16 header_index) struct mlx5e_frag_page *frag_page =3D mlx5e_shampo_hd_to_frag_page(rq, he= ader_index); u16 head_offset =3D mlx5e_shampo_hd_offset(header_index) + rq->buff.headr= oom; =20 - return page_address(frag_page->page) + head_offset; + return netmem_address(frag_page->netmem) + head_offset; } =20 static void mlx5e_shampo_update_ipv4_udp_hdr(struct mlx5e_rq *rq, struct i= phdr *ipv4) @@ -1677,11 +1680,11 @@ mlx5e_skb_from_cqe_linear(struct mlx5e_rq *rq, stru= ct mlx5e_wqe_frag_info *wi, dma_addr_t addr; u32 frag_size; =20 - va =3D page_address(frag_page->page) + wi->offset; + va =3D netmem_address(frag_page->netmem) + wi->offset; data =3D va + rx_headroom; frag_size =3D MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt); =20 - addr =3D page_pool_get_dma_addr(frag_page->page); + addr =3D page_pool_get_dma_addr_netmem(frag_page->netmem); dma_sync_single_range_for_cpu(rq->pdev, addr, wi->offset, frag_size, rq->buff.map_dir); net_prefetch(data); @@ -1731,10 +1734,10 @@ mlx5e_skb_from_cqe_nonlinear(struct mlx5e_rq *rq, s= truct mlx5e_wqe_frag_info *wi =20 frag_page =3D wi->frag_page; =20 - va =3D page_address(frag_page->page) + wi->offset; + va =3D netmem_address(frag_page->netmem) + wi->offset; frag_consumed_bytes =3D min_t(u32, frag_info->frag_size, cqe_bcnt); =20 - addr =3D page_pool_get_dma_addr(frag_page->page); + addr =3D page_pool_get_dma_addr_netmem(frag_page->netmem); dma_sync_single_range_for_cpu(rq->pdev, addr, wi->offset, rq->buff.frame0_sz, rq->buff.map_dir); net_prefetchw(va); /* xdp_frame data area */ @@ -2007,13 +2010,14 @@ mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq = *rq, struct mlx5e_mpw_info *w =20 if (prog) { /* area for bpf_xdp_[store|load]_bytes */ - net_prefetchw(page_address(frag_page->page) + frag_offset); + net_prefetchw(netmem_address(frag_page->netmem) + frag_offset); if (unlikely(mlx5e_page_alloc_fragmented(rq->page_pool, &wi->linear_page))) { rq->stats->buff_alloc_err++; return NULL; } - va =3D page_address(wi->linear_page.page); + + va =3D netmem_address(wi->linear_page.netmem); net_prefetchw(va); /* xdp_frame data area */ linear_hr =3D XDP_PACKET_HEADROOM; linear_data_len =3D 0; @@ -2124,8 +2128,8 @@ mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq *r= q, struct mlx5e_mpw_info *w while (++pagep < frag_page); } /* copy header */ - addr =3D page_pool_get_dma_addr(head_page->page); - mlx5e_copy_skb_header(rq, skb, head_page->page, addr, + addr =3D page_pool_get_dma_addr_netmem(head_page->netmem); + mlx5e_copy_skb_header(rq, skb, head_page->netmem, addr, head_offset, head_offset, headlen); /* skb linear part was allocated with headlen and aligned to long */ skb->tail +=3D headlen; @@ -2155,11 +2159,11 @@ mlx5e_skb_from_cqe_mpwrq_linear(struct mlx5e_rq *rq= , struct mlx5e_mpw_info *wi, return NULL; } =20 - va =3D page_address(frag_page->page) + head_offset; + va =3D netmem_address(frag_page->netmem) + head_offset; data =3D va + rx_headroom; frag_size =3D MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt); =20 - addr =3D page_pool_get_dma_addr(frag_page->page); + addr =3D page_pool_get_dma_addr_netmem(frag_page->netmem); dma_sync_single_range_for_cpu(rq->pdev, addr, head_offset, frag_size, rq->buff.map_dir); net_prefetch(data); @@ -2198,16 +2202,19 @@ mlx5e_skb_from_cqe_shampo(struct mlx5e_rq *rq, stru= ct mlx5e_mpw_info *wi, struct mlx5_cqe64 *cqe, u16 header_index) { struct mlx5e_frag_page *frag_page =3D mlx5e_shampo_hd_to_frag_page(rq, he= ader_index); - dma_addr_t page_dma_addr =3D page_pool_get_dma_addr(frag_page->page); u16 head_offset =3D mlx5e_shampo_hd_offset(header_index); - dma_addr_t dma_addr =3D page_dma_addr + head_offset; u16 head_size =3D cqe->shampo.header_size; u16 rx_headroom =3D rq->buff.headroom; struct sk_buff *skb =3D NULL; + dma_addr_t page_dma_addr; + dma_addr_t dma_addr; void *hdr, *data; u32 frag_size; =20 - hdr =3D page_address(frag_page->page) + head_offset; + page_dma_addr =3D page_pool_get_dma_addr_netmem(frag_page->netmem); + dma_addr =3D page_dma_addr + head_offset; + + hdr =3D netmem_address(frag_page->netmem) + head_offset; data =3D hdr + rx_headroom; frag_size =3D MLX5_SKB_FRAG_SZ(rx_headroom + head_size); =20 @@ -2232,7 +2239,7 @@ mlx5e_skb_from_cqe_shampo(struct mlx5e_rq *rq, struct= mlx5e_mpw_info *wi, } =20 net_prefetchw(skb->data); - mlx5e_copy_skb_header(rq, skb, frag_page->page, dma_addr, + mlx5e_copy_skb_header(rq, skb, frag_page->netmem, dma_addr, head_offset + rx_headroom, rx_headroom, head_size); /* skb linear part was allocated with headlen and aligned to long */ @@ -2326,11 +2333,23 @@ static void mlx5e_handle_rx_cqe_mpwrq_shampo(struct= mlx5e_rq *rq, struct mlx5_cq } =20 if (!*skb) { - if (likely(head_size)) + if (likely(head_size)) { *skb =3D mlx5e_skb_from_cqe_shampo(rq, wi, cqe, header_index); - else - *skb =3D mlx5e_skb_from_cqe_mpwrq_nonlinear(rq, wi, cqe, cqe_bcnt, - data_offset, page_idx); + } else { + struct mlx5e_frag_page *frag_page; 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" , Simon Horman CC: , , , , Leon Romanovsky , "Jesper Dangaard Brouer" , Ilias Apalodimas , Richard Cochran , Alexei Starovoitov , Daniel Borkmann , John Fastabend , Stanislav Fomichev , , , , , Dragos Tatulea , Mina Almasry , Mark Bloch Subject: [PATCH net-next v6 09/12] net/mlx5e: Add support for UNREADABLE netmem page pools Date: Mon, 16 Jun 2025 17:14:38 +0300 Message-ID: <20250616141441.1243044-10-mbloch@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250616141441.1243044-1-mbloch@nvidia.com> References: <20250616141441.1243044-1-mbloch@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PEPF0000000A:EE_|PH0PR12MB7908:EE_ X-MS-Office365-Filtering-Correlation-Id: 5104a963-4a67-4087-e290-08ddace0596b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700013|376014|7416014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?FXwsBTPiChs5jdAfiVwXLy63qNhK94f2jmsMYg7JNbqwIsGDfY+uABYdHc7K?= =?us-ascii?Q?9XBu6UkSRz9YSYpBTuIezgJ1RZuvK+gPwZKs+muHIe+GYB4SsiWl/7qlJolx?= =?us-ascii?Q?zDZ5xy9T197MJOcjAFEM9pMSkk7iT/SDVd+WkWi4s5dQ3XuRryW8E+yuqDiz?= =?us-ascii?Q?JPQhY9fU85tPnyagLBCqumDTrqaLjZONtjp+7DqqIK0qP4+VUt1XvY5PVR9y?= =?us-ascii?Q?SpxoLiQDb5FFZJ8CMxruXrlBOw9Ij6llbLLWffZ6fzWc9/jxlynbZjWvMB4F?= =?us-ascii?Q?vCHJJI+DGWS+KaMpRqo7uD5iOTE0WmYGlXbpNejSH6p4s4S3bmfjO9a0AxIP?= =?us-ascii?Q?eE6PdZ0bq/LTX5yn3hlOcrqUJYAcFAY1ClFk4bOcuOX+8OIXpVy6h6AWqoL+?= =?us-ascii?Q?o486k64ApM+wEFAzkEHdYrJvY5F8gASQWZQksior4WmQVsQMXxg/xsmLmmkB?= =?us-ascii?Q?GA2gOzlOBowOgJIET1LCeQ8uiwbn+Jk6flaGkDwEFJpaQEvPxkLGCztghXiD?= =?us-ascii?Q?7SDsm2r/tmifK3TsVlUewEjvtqG61lUsUdRlBKMFXtW0Kx3rFksxNDsACx4L?= =?us-ascii?Q?L4OtrM9wNkDg5eQQKzzemIx+FMcfAuM09Kf2kqajAEOmfOqTBRATtdV2f3j9?= =?us-ascii?Q?LcPJwvrlJdXOl/uiR7+abLCh2RCpTaHB55VVbQdYQ8F0oO70k+sESyjaqvjL?= =?us-ascii?Q?gOqiIyYAzvmIKJ6l3dOdNFE6cMRX3wjWAYwbbTolIXRhNTnt/IlblHUKryik?= =?us-ascii?Q?4zUvqOCzAIzs48d62Ch4clew60jjrMm5BXbTmGCk3ZU5PIFsOyyG+cghXoV5?= =?us-ascii?Q?GNxCdns7w3VdUi5bssrHdEFSgcETbr8ukwjZghUZf5YW2SaKZi+44zaw3khh?= =?us-ascii?Q?1e4Rmm6vk8Y1XDcpu/9oXpCtgnS0VKw+VaFeXdCjRUAABglvFlPt16IWGriB?= =?us-ascii?Q?Mch1zYpILv6vaQiKJMskZTJsNCAGcUX0Y+2LSaWcBXAj6D/GOrEAi0zZUpgI?= =?us-ascii?Q?BNses/d4hB94RZXHvGpu3qCJtWYmmg4puoGh2AhFgprTyuyH+S7enOQK2H/W?= =?us-ascii?Q?wfK8BaGi3jpvw8kEQwUkL8QyUiO8YrqMjXocQnDP3vh2JGhwuks6gKHRni5X?= =?us-ascii?Q?9m71wYybM0Hn69sDkpJIRNDO3jKfHrkoCowZTmCTzSHJ/oCdmF9Ug+W4TLdp?= =?us-ascii?Q?PeWYEtWjqIkIcDr2O6jW2rG0aWj/hZEpm7L8oTFlNB8vAOnQ6+Tzt0OR9Fgh?= =?us-ascii?Q?pFq6gAVUlWOtODsydzi+DQeKCAXqtlFe/gzUKjiCOhmcmz56u6OYcr0BXnsR?= =?us-ascii?Q?/gtB008i5ea1lCbSo5JicRj43sAYmOwIggonbZrm89QbPX2Ecq88fIyyZ81o?= =?us-ascii?Q?oN3iAP9Zx0IB+KhjKiwciQoxN2zmZ4vSnzMHR/MWKWbcagkf4g/7Yi7aWqlv?= =?us-ascii?Q?DHCXWaxwDg8IdnjfpFhtVgloD97Hl3invPthZ2q+2rwLBlJQ4KNHEQzrTCR5?= =?us-ascii?Q?WXo/H7gUtsk1h/9iMl53pN0pKK84e7PNNnlQ?= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700013)(376014)(7416014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Jun 2025 14:16:12.7981 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5104a963-4a67-4087-e290-08ddace0596b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF0000000A.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB7908 Content-Type: text/plain; charset="utf-8" From: Saeed Mahameed On netdev_rx_queue_restart, a special type of page pool maybe expected. In this patch declare support for UNREADABLE netmem iov pages in the pool params only when header data split shampo RQ mode is enabled, also set the queue index in the page pool params struct. Shampo mode requirement: Without header split rx needs to peek at the data, we can't do UNREADABLE_NETMEM. The patch also enables the use of a separate page pool for headers when a memory provider is installed for the queue, otherwise the same common page pool continues to be used. Signed-off-by: Saeed Mahameed Reviewed-by: Dragos Tatulea Reviewed-by: Tariq Toukan Reviewed-by: Mina Almasry Signed-off-by: Mark Bloch --- drivers/net/ethernet/mellanox/mlx5/core/en_main.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/en_main.c index 5e649705e35f..a51e204bd364 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -749,7 +749,9 @@ static void mlx5e_rq_shampo_hd_info_free(struct mlx5e_r= q *rq) =20 static bool mlx5_rq_needs_separate_hd_pool(struct mlx5e_rq *rq) { - return false; + struct netdev_rx_queue *rxq =3D __netif_get_rx_queue(rq->netdev, rq->ix); + + return !!rxq->mp_params.mp_ops; } =20 static int mlx5_rq_shampo_alloc(struct mlx5_core_dev *mdev, @@ -964,6 +966,11 @@ static int mlx5e_alloc_rq(struct mlx5e_params *params, pp_params.netdev =3D rq->netdev; pp_params.dma_dir =3D rq->buff.map_dir; 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" , Simon Horman CC: , , , , Leon Romanovsky , "Jesper Dangaard Brouer" , Ilias Apalodimas , Richard Cochran , Alexei Starovoitov , Daniel Borkmann , John Fastabend , Stanislav Fomichev , , , , , Dragos Tatulea , Mark Bloch Subject: [PATCH net-next v6 10/12] net/mlx5e: Implement queue mgmt ops and single channel swap Date: Mon, 16 Jun 2025 17:14:39 +0300 Message-ID: <20250616141441.1243044-11-mbloch@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250616141441.1243044-1-mbloch@nvidia.com> References: <20250616141441.1243044-1-mbloch@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PEPF0000000A:EE_|LV8PR12MB9618:EE_ X-MS-Office365-Filtering-Correlation-Id: 1675f524-4152-4fb1-059e-08ddace05cbd X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|36860700013|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?gWwmwL60h7FJRe1oZVxfNsCwpKzctHK/5fX/is9NfSzilVQM2Oy5qFIZ4Mfa?= =?us-ascii?Q?HsZ7gy+4MOjMs81sKBwajE8cErNLKCRg2nJ+wI+C5JdPaiMCGXVhQ2weKsgV?= =?us-ascii?Q?VjOvMI572UUZhVQWItDcvd3n9y5xmzSlod/IwNUnGms1o4801i9Y62nJ88xQ?= =?us-ascii?Q?0K5IltK7R12kh30STahT8R0UrhPFJRekTPb+9WXtCBdfOUcVWTI/nZZHwYlr?= =?us-ascii?Q?Z7P3JuQXk3UgqrQ0x4wztoZuaQktuxHwKkIIZYe3Ysmdxi6QZROVGESDOaB5?= =?us-ascii?Q?nEHESsG/TyBaV/9Lxqsq2VIvlaX9v+KnIbFTGqagNKluXC1QCq2glDcnVFJW?= =?us-ascii?Q?/UwCKKhzMZVOnwRV1w55qMdGzNdNwiqUGqejuK1kbA4KJkIiLsUxjx5T824V?= =?us-ascii?Q?AirnctAqVcyr7kkhV9AtgpovIooK8GhJU4WymuuQrm6dieCDyP1XoSwPuiS6?= =?us-ascii?Q?IBmLQIWc2ob4PVt0tqNnUsWA39Wh/ZEgVqaxxFxe8WNHNfQNnkeb9wp3neTL?= =?us-ascii?Q?e8NIScwd8YLr8ENPrhR5Gj9NhuqXkvzkKuY7nH/UNZ2kcYT64b+ToSrnkhV/?= =?us-ascii?Q?vIlJNvbvrcIJ5Wyn9DsACpfdF5nUJYWHpsP2FQdZemyqehvNr8bIwnYuaJe4?= =?us-ascii?Q?7xWfeqakPxaqdMPD7dFdmYbmcTbJlqbMIs00T7RhhMeI1WA09xxY/zFmuGDB?= =?us-ascii?Q?ozHYu56DjplxMvKOFajX5ev/zeO0ZxU7zdzzkpt58kLuLLckRkh00jYG68mn?= =?us-ascii?Q?9tBxA7C/c1GAiL90JDh0+GStntpxsDJfBi/RXmClj1HwSV/g2LfcdY+3GY3Q?= =?us-ascii?Q?7FFkE1ZoKoPUePmcTmZsIUgwakS3LQ3me6zvk8pMLWKg6rDP7SjC2cAlVP8Z?= =?us-ascii?Q?R+XlfGtinzjNPbwt2nfmPbqD3f5mp6f4aUgou10f3lfdijRgQna5ajoIMMQb?= =?us-ascii?Q?lPMTyRWlUAHttjXWH3p38G3MxuDH3r2wvOeDfrcL5a6WXy4jpTvIWZO6FDEc?= =?us-ascii?Q?CETk8Om7zL1UqODPzq5zQSzFwsVhdp0XKWeOCwiBBC2fD8xpVc+31rK/SP34?= =?us-ascii?Q?tNYjMQ6YmSN8DnTT1yP4T6GNWObow8s/rRJlzF4Q4x5QEe8jq8o8Uc1dfxeR?= =?us-ascii?Q?gjaSqW2vAcdpQKqIlyGb3+LqWegPHjqpACLrLEAB+R85y9+C2f1Z3bVSVtVB?= =?us-ascii?Q?6EKlUNWFcc4ZB5mCkTzRw7GigFVRrz4kfxUFULA34JwOAlxUQOMPbpExMAnY?= =?us-ascii?Q?Ghe6WMGgPLkz43A7xQxgigyGolefZLmObEnf0VKaRv7k/FeQo3JSCswFLTyJ?= =?us-ascii?Q?pAMbcvuzGhxOnc7oMjbQ8u0Sw6RtcLDcAI63whksxmQjlKI2xDHbbiiVXeq8?= =?us-ascii?Q?Z9fudGkwAH/M5J2nB6edoLfwEHp8hyPGUoXAnSZBVFcHBI/9/fYW2i4llbMQ?= =?us-ascii?Q?qX5amuI5lqUwZsgYNreHQAKWONj8dHV5jp5oxCcoBjdKwkHPsRNzFKB2FV7K?= =?us-ascii?Q?fa+OdkPNWNffDGOn8lrlqslwTakvxpO6xjPe?= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(7416014)(36860700013)(82310400026)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Jun 2025 14:16:18.3612 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1675f524-4152-4fb1-059e-08ddace05cbd X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF0000000A.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9618 Content-Type: text/plain; charset="utf-8" From: Saeed Mahameed The bulk of the work is done in mlx5e_queue_mem_alloc, where we allocate and create the new channel resources, similar to mlx5e_safe_switch_params, but here we do it for a single channel using existing params, sort of a clone channel. To swap the old channel with the new one, we deactivate and close the old channel then replace it with the new one, since the swap procedure doesn't fail in mlx5, we do it all in one place (mlx5e_queue_start). Signed-off-by: Saeed Mahameed Reviewed-by: Dragos Tatulea Reviewed-by: Tariq Toukan Signed-off-by: Mark Bloch Acked-by: Mina Almasry --- .../net/ethernet/mellanox/mlx5/core/en_main.c | 98 +++++++++++++++++++ 1 file changed, 98 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/en_main.c index a51e204bd364..873a42b4a82d 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -5494,6 +5494,103 @@ static const struct netdev_stat_ops mlx5e_stat_ops = =3D { .get_base_stats =3D mlx5e_get_base_stats, }; =20 +struct mlx5_qmgmt_data { + struct mlx5e_channel *c; + struct mlx5e_channel_param cparam; +}; + +static int mlx5e_queue_mem_alloc(struct net_device *dev, void *newq, + int queue_index) +{ + struct mlx5_qmgmt_data *new =3D (struct mlx5_qmgmt_data *)newq; + struct mlx5e_priv *priv =3D netdev_priv(dev); + struct mlx5e_channels *chs =3D &priv->channels; + struct mlx5e_params params =3D chs->params; + struct mlx5_core_dev *mdev; + int err; + + mutex_lock(&priv->state_lock); + if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) { + err =3D -ENODEV; + goto unlock; + } + + if (queue_index >=3D chs->num) { + err =3D -ERANGE; + goto unlock; + } + + if (MLX5E_GET_PFLAG(&chs->params, MLX5E_PFLAG_TX_PORT_TS) || + chs->params.ptp_rx || + chs->params.xdp_prog || + priv->htb) { + netdev_err(priv->netdev, + "Cloning channels with Port/rx PTP, XDP or HTB is not supported\n"); + err =3D -EOPNOTSUPP; + goto unlock; + } + + mdev =3D mlx5_sd_ch_ix_get_dev(priv->mdev, queue_index); + err =3D mlx5e_build_channel_param(mdev, ¶ms, &new->cparam); + if (err) + goto unlock; + + err =3D mlx5e_open_channel(priv, queue_index, ¶ms, NULL, &new->c); +unlock: + mutex_unlock(&priv->state_lock); + return err; +} + +static void mlx5e_queue_mem_free(struct net_device *dev, void *mem) +{ + struct mlx5_qmgmt_data *data =3D (struct mlx5_qmgmt_data *)mem; + + /* not supposed to happen since mlx5e_queue_start never fails + * but this is how this should be implemented just in case + */ + if (data->c) + mlx5e_close_channel(data->c); +} + +static int mlx5e_queue_stop(struct net_device *dev, void *oldq, int queue_= index) +{ + /* In mlx5 a txq cannot be simply stopped in isolation, only restarted. + * mlx5e_queue_start does not fail, we stop the old queue there. + * TODO: Improve this. + */ + return 0; +} + +static int mlx5e_queue_start(struct net_device *dev, void *newq, + int queue_index) +{ + struct mlx5_qmgmt_data *new =3D (struct mlx5_qmgmt_data *)newq; + struct mlx5e_priv *priv =3D netdev_priv(dev); + struct mlx5e_channel *old; + + mutex_lock(&priv->state_lock); + + /* stop and close the old */ + old =3D priv->channels.c[queue_index]; + mlx5e_deactivate_priv_channels(priv); + /* close old before activating new, to avoid napi conflict */ + mlx5e_close_channel(old); + + /* start the new */ + priv->channels.c[queue_index] =3D new->c; + mlx5e_activate_priv_channels(priv); + mutex_unlock(&priv->state_lock); + return 0; +} + +static const struct netdev_queue_mgmt_ops mlx5e_queue_mgmt_ops =3D { + .ndo_queue_mem_size =3D sizeof(struct mlx5_qmgmt_data), + .ndo_queue_mem_alloc =3D mlx5e_queue_mem_alloc, + .ndo_queue_mem_free =3D mlx5e_queue_mem_free, + .ndo_queue_start =3D mlx5e_queue_start, + .ndo_queue_stop =3D mlx5e_queue_stop, +}; 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" , Simon Horman CC: , , , , Leon Romanovsky , "Jesper Dangaard Brouer" , Ilias Apalodimas , Richard Cochran , Alexei Starovoitov , Daniel Borkmann , John Fastabend , Stanislav Fomichev , , , , , Cosmin Ratiu , Dragos Tatulea , Mark Bloch Subject: [PATCH net-next v6 11/12] net/mlx5e: Support ethtool tcp-data-split settings Date: Mon, 16 Jun 2025 17:14:40 +0300 Message-ID: <20250616141441.1243044-12-mbloch@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250616141441.1243044-1-mbloch@nvidia.com> References: <20250616141441.1243044-1-mbloch@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE3A:EE_|SA5PPF7F0CA3746:EE_ X-MS-Office365-Filtering-Correlation-Id: 3cad4270-46ef-4893-6503-08ddace05fee X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|36860700013|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?RZ2m8Le5hLRfQkQhqxaAGs0L9JuzLIy4yQEbMMSth/36m6RrPMOpJaXLjbEf?= =?us-ascii?Q?+xGPY0q4oA+PB7GnSZdMtqxxicaDkVWvUl3bIM49JNbiXklTLG8bTgImejxe?= =?us-ascii?Q?e5U70oz796vTSP+0X7j2ZixP2Q5NbXB44VmQVdOU/p0OAeCSqLagmh/n2Fkt?= =?us-ascii?Q?nguwiW5UBvfNpGOkPbImth0fT3j2w6seO7TkMFUwD0/eAIOH/Up7NzC0Jkyw?= =?us-ascii?Q?eVFUK1Uai+JF3WoFCN4Zk6g3VtYc8q7cQCvQWg3VA65pGYACwUaYeqOxvyIf?= =?us-ascii?Q?YRd6XMwqGekzyB53BvZ9gFL2ONF1sDRthQYBc/GKa+ozXeX/Yu3TcC4ExPjR?= =?us-ascii?Q?xaPXljHVUx2vtCeor1iAKiwwDPWDBBDHyQgkZ/6Got+04+3vwlZw4Es4wrVG?= =?us-ascii?Q?kz225hGVwszyHOllHHT/9al9zpjtycYGvL1LG15u1/Bmg18/BfxN0daTB1Wy?= =?us-ascii?Q?6gHQl2XpvMqp2nVZuWVUyF7wwlJx/A7fY+iyIb1zr1gMO5f11Rqr3ETde25v?= =?us-ascii?Q?n5E6vrcYsSmyxmSl7MfsH9XzKW8PHc/sgTcLF/TJp4WR3WDo2wEG7hLs9uwI?= =?us-ascii?Q?OABNt7CPkliheNHaqPeM338jS96RRy/vO/tDGx64ApcTINAyffjTbqfqP2mo?= =?us-ascii?Q?Fb7btNEZ0k+PYAF0P9XOQsMxy0kTZkCjTXrQzVpbJSWCLzFf5JnvC860d9wT?= =?us-ascii?Q?gi2nCkgZZtCSeYLkDovXRkk2LchLXbQNZ9dsgyARvTLuFImmO+WlNQek//yP?= =?us-ascii?Q?UyHA+lTl+158VSWXPf0xzd+Boh4uTNSlspQcTN3wuWIbz4yz2fRhE8/tcQ+K?= =?us-ascii?Q?AtpOY4cWNAWXxzTSuC+i1IkQV9QU9maCH1pywvhGo8emfILZ20XpdFtge01h?= =?us-ascii?Q?A5+rSc3sAxlTsgjoYZILoQ/PHomyq1JcF2c2NxOxiNca9s6apKnfo7xqLU2U?= =?us-ascii?Q?POFgFDgk7COc+03uAPxADLrEfCTKjKke6SvuunCd2M4zW01eC7gKDrXu3Mnm?= =?us-ascii?Q?8oERwrahQS8oKgOzuf9aC+3/kHkHPxUXtqUUYv2qjtob8Ih001kumscoda61?= =?us-ascii?Q?4EmP8FfUpuUDAdMStYpFvLB0IufwK6Xb409D3eeCIDLNfB/QPu0vOfKN0yB4?= =?us-ascii?Q?9ir96x7+4GqLa/6W+P6R/I+oPAdYhgPbW9du5qMXstWHL3OX/WqlGw0hPm/O?= =?us-ascii?Q?Znt509ph3S5EUpqVhmFzyqg/iVoqy84zSZ3WFAAFY73or7/KdbVCSLbrI7cT?= =?us-ascii?Q?ixO7/m4danDF4/MBuv6A/Jovq4X13fYg32KuCC2j3RvUsB5HsQ3AjR8bDTRN?= =?us-ascii?Q?xXiGB5X97orejs2SmsXLQKS76RE0SVhQFz7yQ8DkvnNRu8CvAcBMVPdfOnCo?= =?us-ascii?Q?Rue+NsFRAdp2pz2uGm9UYMGnG91VeOYMXuSFqujs7Glfj0vgTuJcenss/uz9?= =?us-ascii?Q?TTUjPruy8pcQ5MH4xbq0rqAZensSVAUS8MCkcWV/6nGaD8WnzgGE6DV0G4e6?= =?us-ascii?Q?9UvG5Wr7IjuztkX9eM8vg305wW17COAzYJBX?= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(376014)(36860700013)(82310400026)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Jun 2025 14:16:23.7545 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3cad4270-46ef-4893-6503-08ddace05fee X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE3A.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA5PPF7F0CA3746 Content-Type: text/plain; charset="utf-8" From: Saeed Mahameed In mlx5, tcp header-data split requires HW GRO to be on. Enabling it fails when HW GRO is off. mlx5e_fix_features now keeps HW GRO on when tcp data split is enabled. Finally, when tcp data split is disabled, features are updated to maybe remove the forced HW GRO. Signed-off-by: Saeed Mahameed Signed-off-by: Cosmin Ratiu Reviewed-by: Dragos Tatulea Reviewed-by: Tariq Toukan Signed-off-by: Mark Bloch --- .../ethernet/mellanox/mlx5/core/en_ethtool.c | 33 ++++++++++++++++--- .../net/ethernet/mellanox/mlx5/core/en_main.c | 8 +++++ 2 files changed, 36 insertions(+), 5 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c b/drivers= /net/ethernet/mellanox/mlx5/core/en_ethtool.c index 8b9ee8bac674..35479cbf98d5 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c @@ -32,6 +32,7 @@ =20 #include #include +#include =20 #include "en.h" #include "en/channels.h" @@ -365,11 +366,6 @@ void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *pr= iv, param->tx_max_pending =3D 1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE; param->rx_pending =3D 1 << priv->channels.params.log_rq_mtu_frames; param->tx_pending =3D 1 << priv->channels.params.log_sq_size; - - kernel_param->tcp_data_split =3D - (priv->channels.params.packet_merge.type =3D=3D MLX5E_PACKET_MERGE_SHAMP= O) ? - ETHTOOL_TCP_DATA_SPLIT_ENABLED : - ETHTOOL_TCP_DATA_SPLIT_DISABLED; } =20 static void mlx5e_get_ringparam(struct net_device *dev, @@ -382,6 +378,27 @@ static void mlx5e_get_ringparam(struct net_device *dev, mlx5e_ethtool_get_ringparam(priv, param, kernel_param); } =20 +static bool mlx5e_ethtool_set_tcp_data_split(struct mlx5e_priv *priv, + u8 tcp_data_split, + struct netlink_ext_ack *extack) +{ + struct net_device *dev =3D priv->netdev; + + if (tcp_data_split =3D=3D ETHTOOL_TCP_DATA_SPLIT_ENABLED && + !(dev->features & NETIF_F_GRO_HW)) { + NL_SET_ERR_MSG_MOD(extack, + "TCP-data-split is not supported when GRO HW is disabled"); + return false; + } + + /* Might need to disable HW-GRO if it was kept on due to hds. */ + if (tcp_data_split =3D=3D ETHTOOL_TCP_DATA_SPLIT_DISABLED && + dev->cfg->hds_config =3D=3D ETHTOOL_TCP_DATA_SPLIT_ENABLED) + netdev_update_features(priv->netdev); + + return true; +} + int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv, struct ethtool_ringparam *param, struct netlink_ext_ack *extack) @@ -440,6 +457,11 @@ static int mlx5e_set_ringparam(struct net_device *dev, { struct mlx5e_priv *priv =3D netdev_priv(dev); =20 + if (!mlx5e_ethtool_set_tcp_data_split(priv, + kernel_param->tcp_data_split, + extack)) + return -EINVAL; + return mlx5e_ethtool_set_ringparam(priv, param, extack); } =20 @@ -2623,6 +2645,7 @@ const struct ethtool_ops mlx5e_ethtool_ops =3D { ETHTOOL_COALESCE_USE_ADAPTIVE | ETHTOOL_COALESCE_USE_CQE, .supported_input_xfrm =3D RXH_XFRM_SYM_OR_XOR, + .supported_ring_params =3D ETHTOOL_RING_USE_TCP_DATA_SPLIT, .get_drvinfo =3D mlx5e_get_drvinfo, .get_link =3D ethtool_op_get_link, .get_link_ext_state =3D mlx5e_get_link_ext_state, diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/en_main.c index 873a42b4a82d..b4df62b58292 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -4413,6 +4413,7 @@ static netdev_features_t mlx5e_fix_uplink_rep_feature= s(struct net_device *netdev static netdev_features_t mlx5e_fix_features(struct net_device *netdev, netdev_features_t features) { + struct netdev_config *cfg =3D netdev->cfg_pending; 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Mon, 16 Jun 2025 07:16:19 -0700 Received: from drhqmail203.nvidia.com (10.126.190.182) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.14; Mon, 16 Jun 2025 07:16:18 -0700 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.182) with Microsoft SMTP Server id 15.2.1544.14 via Frontend Transport; Mon, 16 Jun 2025 07:16:13 -0700 From: Mark Bloch To: "David S. Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" , Simon Horman CC: , , , , Leon Romanovsky , "Jesper Dangaard Brouer" , Ilias Apalodimas , Richard Cochran , Alexei Starovoitov , Daniel Borkmann , John Fastabend , Stanislav Fomichev , , , , , Dragos Tatulea , Mina Almasry , Mark Bloch Subject: [PATCH net-next v6 12/12] net/mlx5e: Add TX support for netmems Date: Mon, 16 Jun 2025 17:14:41 +0300 Message-ID: <20250616141441.1243044-13-mbloch@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250616141441.1243044-1-mbloch@nvidia.com> References: <20250616141441.1243044-1-mbloch@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PEPF0000000A:EE_|DS4PR12MB9747:EE_ X-MS-Office365-Filtering-Correlation-Id: 4ea35797-476e-45fd-d7b8-08ddace06588 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|1800799024|7416014|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?uqJjo/0xgkneHVF6c7GOatwakpaLtVaYe5b7y7msxVI0yV3wk1zUBbxR/Qum?= =?us-ascii?Q?U9dnNlzHTqIPHfa4lj9WqhNxvHGqsBIWI7gIU2ixrphALMV4Z4W6PUZbaSDF?= =?us-ascii?Q?Zo4HrH9jPLwk9XCU7xjCdu7dRdVf5640tIdQlXxO6vXSdmktBkjCl7GluEz5?= =?us-ascii?Q?ia7TQinb7FDw5yqadLbqMAJo/CwGU+EMGpr1RDaZiXPbvuUCzXk7i+nBTFsd?= =?us-ascii?Q?8wCqWoQ+BtOywpwkuNDHQQrPP8boJRhldRq0eCf4+u+ShbSz8O96MALQ4dxJ?= =?us-ascii?Q?v7hzBzmF7b4VOEVKwjRJnhiv6F8q7i9J3GjwMR/liT8kYdpa24MrSbymYDtH?= =?us-ascii?Q?jkJrz61ZZkOkeB6FcKPszZBvJEavE+yQMdTCEPO6jvuoxwHqL0/OfhSlVnK1?= =?us-ascii?Q?2NZRnzNRO36VqkjXXMkdvpNTMgF2RXjv1KPa1VohXZkFdb9MQRcR+8t72Ten?= =?us-ascii?Q?teJVIm8oqz3o3wjehVZKdlDHq1Qo84Adrr9l5Qdjr+jf02x9MtoNtj1Dwf4x?= =?us-ascii?Q?Go9zB9s9on/hUFZC0Y9Sq+i1PdbnMAK3pFDUK9jPgbNhHgg0B6+J0NaqZ/ie?= =?us-ascii?Q?eGki4k+tf2zqsPzwVRgmx62ALZHWJiWIrk1MihEl9G1DTuNPVHidPwBbBMsC?= =?us-ascii?Q?cAkQp6nW1d4/wdExCb6/XzRZ8565urcQOjQJFlEfToNIc0cZe+jJxLkgDwEu?= =?us-ascii?Q?ZCWmwadlxM85ekwOf6yu3YnZGBoX5DwZ+yaj/bffFWS4smGO2ItN3DRigb1n?= =?us-ascii?Q?FemHYmcG9W0Zb7TxZoRelWpP0VmeFuFt0YBDwN9AmaNf7LzgiuaPYG8TXNb2?= =?us-ascii?Q?LRBc5KS9cLc78ishZ2VD8qxcot0/awcszOwlyew2I/sogsRIqAQBeI9cP/4J?= =?us-ascii?Q?XVwRY6Vt4H3g4sMwnvPnL/w/S0EeRXr5ToYuMuw1r+Z46ztA+ef/3hZ0GEat?= =?us-ascii?Q?XUo87Qxp/jTXEbv9keYbzFuRNwe7vuaE6FDPcSukVh8Vo7iIJlth9nfvF4pb?= =?us-ascii?Q?MgpC8WCg0rF1cZoKhw7lNkNszT8HBsgKNoSNzA1eOguuqj4vMJ45HS1lRTKM?= =?us-ascii?Q?WDxoHYsMMHYTiOczjIK0+jXcn2AISehfXK1mkGXB1MUfFgYxLiKt5GjX5A50?= =?us-ascii?Q?HI9n/IXyF5rxbCGHbaOXIkj+oV+PqieJET7auMN0kdnxABIqAftvNveMdsYn?= =?us-ascii?Q?CzObIL5/8+gVBWqnNFgNK5ry+LYjCjgCXpKMbDqCI/JaRPzoicyF6RapsQmL?= =?us-ascii?Q?9sjsVA+WTeGf0owJ/fo2+Stuyuuy08Evl7p4Tw/HQU133UP8XfSpok7KcD8b?= =?us-ascii?Q?oZa1VKdp3GOPZzEBugl7TLAUc3A/TxMBHs1p9AfQPblnp2KtCcLLN0ENyddV?= =?us-ascii?Q?I0vNjX7tqVF/fOiv7MW7dPsU2jWDnS01SoT/rM36qXzD2S4/0tv2gjha8Stl?= =?us-ascii?Q?KIKeZbQJEJ7olVsrfwOLdZPgUPABFQBWZ96YLwP1tXyPXxNW8j/GxR/GqMKl?= =?us-ascii?Q?NUkPcvFSkkW+hOyDcduMvmEduLGl/3VWiYCJ?= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(82310400026)(1800799024)(7416014)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Jun 2025 14:16:33.0850 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4ea35797-476e-45fd-d7b8-08ddace06588 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF0000000A.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS4PR12MB9747 Content-Type: text/plain; charset="utf-8" From: Dragos Tatulea Declare netmem TX support in netdev. As required, use the netmem aware dma unmapping APIs for unmapping netmems in tx completion path. Signed-off-by: Dragos Tatulea Reviewed-by: Tariq Toukan Reviewed-by: Mina Almasry Signed-off-by: Mark Bloch --- drivers/net/ethernet/mellanox/mlx5/core/en/txrx.h | 3 ++- drivers/net/ethernet/mellanox/mlx5/core/en_main.c | 2 ++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/txrx.h b/drivers/ne= t/ethernet/mellanox/mlx5/core/en/txrx.h index e837c21d3d21..6501252359b0 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/txrx.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/txrx.h @@ -362,7 +362,8 @@ mlx5e_tx_dma_unmap(struct device *pdev, struct mlx5e_sq= _dma *dma) dma_unmap_single(pdev, dma->addr, dma->size, DMA_TO_DEVICE); break; case MLX5E_DMA_MAP_PAGE: - dma_unmap_page(pdev, dma->addr, dma->size, DMA_TO_DEVICE); + netmem_dma_unmap_page_attrs(pdev, dma->addr, dma->size, + DMA_TO_DEVICE, 0); break; default: WARN_ONCE(true, "mlx5e_tx_dma_unmap unknown DMA type!\n"); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/en_main.c index b4df62b58292..24559cbcbfc2 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -5741,6 +5741,8 @@ static void mlx5e_build_nic_netdev(struct net_device = *netdev) =20 netdev->priv_flags |=3D IFF_UNICAST_FLT; =20 + netdev->netmem_tx =3D true; + netif_set_tso_max_size(netdev, GSO_MAX_SIZE); mlx5e_set_xdp_feature(netdev); mlx5e_set_netdev_dev_addr(netdev); --=20 2.34.1