From nobody Fri Oct 10 02:48:20 2025 Received: from naesa03.arrow.com (naesa03.arrow.com [216.150.161.23]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 792CD2BD5A8; Mon, 16 Jun 2025 11:23:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=216.150.161.23 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750073010; cv=none; b=iRoi76zOFkph4sM7+BqiKgaZrDJdBQoWLauRb6wF6BGGbKL+/0Ez3rsMaUBKiDjUgfanimHHNulnO3NYgD3rkhMyMXTP71GBgNoqiulUHVJAsGy8CLmYcfkgliXMl+gC4S3S3feup8vjHyLu7VndzvktCE3HgyUPXPCJpDaSkcA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750073010; c=relaxed/simple; bh=cn13MD+YqkkW+ZeWZc6YLX1Q9LAquq/3iQjwn6K8z9Q=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=JeH/6Hz7gLIojV8W5K/6LY0eotRcdNriERS23fZvsCRQ+9xKWnOnjz0YoxjS1bq6/95MlYSlm8QsKn+2x37ks70XpCM6+NWSCm57N4o7Jagw0aL4I0okWeBtKTQiX5tD+UyxpJe25NrGnFvkq3ubKEkQ0AyYfAm0d5xugXTrzRM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=einfochips.com; spf=pass smtp.mailfrom=einfochips.com; dkim=pass (2048-bit key) header.d=einfochips.com header.i=@einfochips.com header.b=qmZw4031; arc=none smtp.client-ip=216.150.161.23 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=einfochips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=einfochips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=einfochips.com header.i=@einfochips.com header.b="qmZw4031" DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=einfochips.com; i=@einfochips.com; l=2356; q=dns/txt; s=NAESA-Selector1; t=1750073008; x=1781609008; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=cn13MD+YqkkW+ZeWZc6YLX1Q9LAquq/3iQjwn6K8z9Q=; b=qmZw4031VUOFEH04WJ4PHvba2H1pdJsZ0WSa8J3n5blicbIBFlP9ys9R NN1kpli7c55MwDqsRlaxtf+/e7Y3qlQt0XLAsuSqub8F4ovIEJin8xqSv eic7nv8/D5zeAo39SaZmSBTrqdhEYtjrQ3rPfVMfrzxf13DjbKnmzgRom UZ+IUomxNH7z2UcsR7deP9i7SYSrEp+0BwWI9OcrTuRQWhmhQt3JC9w5c tmYtTPuxro9aD9IxSCogaJ0tWy4DYa8wRzGUVLY1YZYJ2QM3D8U+n61Gb maS5GCjAiGKHrgV9Xb9NGCuCz10Yj+2mPEYWS5cHAfKvQ6fYDHqf5W3Sh A==; X-CSE-ConnectionGUID: k75QcjoyQx2pmRDPyu10NA== X-CSE-MsgGUID: 8LBG/hAzSkGKbaTkaesCCw== X-IronPort-AV: E=Sophos;i="6.16,241,1744092000"; d="scan'208";a="86117911" Received: from unknown (HELO eicahmirelay01.einfochips.com) ([10.100.49.50]) by naesa03out.arrow.com with ESMTP; 16 Jun 2025 05:23:27 -0600 Received: from AHMCPU1888.ap.corp.arrow.com ([172.25.5.100]) by eicahmirelay01.einfochips.com with Microsoft SMTPSVC(10.0.14393.4169); Mon, 16 Jun 2025 16:53:16 +0530 From: Pinkesh Vaghela To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Thomas Gleixner Cc: Paul Walmsley , Samuel Holland , Palmer Dabbelt , Albert Ou , Daniel Lezcano , Min Lin , Pinkesh Vaghela , Pritesh Patel , Yangyu Chen , Lad Prabhakar , Yu Chien Peter Lin , Charlie Jenkins , Kanak Shilledar , Darshan Prajapati , Neil Armstrong , Heiko Stuebner , Aradhya Bhatia , rafal@milecki.pl, Anup Patel , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 7/7] riscv: dts: eswin: add HiFive Premier P550 board device tree Date: Mon, 16 Jun 2025 16:53:16 +0530 Message-Id: <20250616112316.3833343-8-pinkesh.vaghela@einfochips.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250616112316.3833343-1-pinkesh.vaghela@einfochips.com> References: <20250616112316.3833343-1-pinkesh.vaghela@einfochips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-OriginalArrivalTime: 16 Jun 2025 11:23:16.0865 (UTC) FILETIME=[0E55E710:01DBDEB1] Content-Type: text/plain; charset="utf-8" From: Min Lin Add minimal device tree for HiFive Premier P550 Development board Currently the data populated in this DT file is for UART. Signed-off-by: Min Lin Co-developed-by: Pinkesh Vaghela Signed-off-by: Pinkesh Vaghela Reviewed-by: Samuel Holland Tested-by: Samuel Holland Tested-by: Ariel D'Alessandro --- arch/riscv/boot/dts/Makefile | 1 + arch/riscv/boot/dts/eswin/Makefile | 2 ++ .../dts/eswin/eic7700-hifive-premier-p550.dts | 29 +++++++++++++++++++ 3 files changed, 32 insertions(+) create mode 100644 arch/riscv/boot/dts/eswin/Makefile create mode 100644 arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.d= ts diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile index 64a898da9aee..29a97a663ea2 100644 --- a/arch/riscv/boot/dts/Makefile +++ b/arch/riscv/boot/dts/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 subdir-y +=3D allwinner subdir-y +=3D canaan +subdir-y +=3D eswin subdir-y +=3D microchip subdir-y +=3D renesas subdir-y +=3D sifive diff --git a/arch/riscv/boot/dts/eswin/Makefile b/arch/riscv/boot/dts/eswin= /Makefile new file mode 100644 index 000000000000..224101ae471e --- /dev/null +++ b/arch/riscv/boot/dts/eswin/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_ESWIN) +=3D eic7700-hifive-premier-p550.dtb diff --git a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts b/ar= ch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts new file mode 100644 index 000000000000..131ed1fc6b2e --- /dev/null +++ b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (c) 2024, Beijing ESWIN Computing Technology Co., Ltd. + */ + +/dts-v1/; + +#include "eic7700.dtsi" + +/ { + compatible =3D "sifive,hifive-premier-p550", "eswin,eic7700"; + model =3D "SiFive HiFive Premier P550"; + + aliases { + serial0 =3D &uart0; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; +}; + +&uart0 { + status =3D "okay"; +}; + +&uart2 { + status =3D "okay"; +}; --=20 2.25.1