From nobody Fri Oct 10 02:48:20 2025 Received: from naesa03.arrow.com (naesa03.arrow.com [216.150.161.23]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 12C3C29ACEA; Mon, 16 Jun 2025 11:23:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=216.150.161.23 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750073009; cv=none; b=DUPwXx15+TukFcrhHDPE8amruLu5PAH64PyRFrzS2YvSMcrPLqgx4Q+vdyg2AXJ9F4l0Su0BY8uRgs1IL5zAykl4QzPx8fCSarFJh3uiU0vw8vZ0tXDpyRYjXVHJpB2rUMsUBh9TKns6dLFuV/bmvCH5nEFn0CQsAzmRqqfKV24= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750073009; c=relaxed/simple; bh=kzGngVQLKJmSvAj307fFJjLeD7Enh4XUOwI2qPpogm0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=NbtGxeB0vzoPJITHZHNQdDe3YtSpRKNS0wxZrqZX4D0BKwVTyH9fIXq5kKca4ARK845eUsXViPlIcvUanaxCKujFy2jwNUxM0isKbnCfsjjahnW8kLzhB0lggcVo2mbyZ2rkHHAMNSW/om/myXYoE5U2OjmfZHcl9RSTvSU3hn4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=einfochips.com; spf=pass smtp.mailfrom=einfochips.com; dkim=pass (2048-bit key) header.d=einfochips.com header.i=@einfochips.com header.b=FgRI8ApM; arc=none smtp.client-ip=216.150.161.23 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=einfochips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=einfochips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=einfochips.com header.i=@einfochips.com header.b="FgRI8ApM" DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=einfochips.com; i=@einfochips.com; l=11275; q=dns/txt; s=NAESA-Selector1; t=1750073007; x=1781609007; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=kzGngVQLKJmSvAj307fFJjLeD7Enh4XUOwI2qPpogm0=; b=FgRI8ApMgPw5OxTRfjpP85Ry/Ang9o91A1fVildB0FxqEsMWPYbZFMX4 H9s4re7L+EAyoignP0yWEwn2Mqzv6HatDGAxoLmXwV/PyXp2R+AX2q1T0 HwKU4xnoLiOA605CQPOHvr4Jse+QWzkVZ508tjIxS6oqhglUQx4HDMAAX KpgJJ716y5blCLVyZRfXeZS3uNPlAkX4B28LimAgJxrGmqzRwdukUuBoK 1WA1E0CCEnqiulRMi45mQ9tbkwE+zPgilVinaH/hNj6zJMrX5+gErSn9X WawC5D+eF5zHNCUX1KdgvV9okXpRJT09iXj+lefjcgUbwYOXRuOZZoxDD w==; X-CSE-ConnectionGUID: 3Kse2lV/Qtqmslc2Nb3/Cg== X-CSE-MsgGUID: qzX1TI/kRFan0IS3wBrpEg== X-IronPort-AV: E=Sophos;i="6.16,241,1744092000"; d="scan'208";a="86117909" Received: from unknown (HELO eicahmirelay01.einfochips.com) ([10.100.49.50]) by naesa03out.arrow.com with ESMTP; 16 Jun 2025 05:23:25 -0600 Received: from AHMCPU1888.ap.corp.arrow.com ([172.25.5.100]) by eicahmirelay01.einfochips.com with Microsoft SMTPSVC(10.0.14393.4169); Mon, 16 Jun 2025 16:53:16 +0530 From: Pinkesh Vaghela To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Thomas Gleixner Cc: Paul Walmsley , Samuel Holland , Palmer Dabbelt , Albert Ou , Daniel Lezcano , Min Lin , Pinkesh Vaghela , Pritesh Patel , Yangyu Chen , Lad Prabhakar , Yu Chien Peter Lin , Charlie Jenkins , Kanak Shilledar , Darshan Prajapati , Neil Armstrong , Heiko Stuebner , Aradhya Bhatia , rafal@milecki.pl, Anup Patel , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 6/7] riscv: dts: add initial support for EIC7700 SoC Date: Mon, 16 Jun 2025 16:53:15 +0530 Message-Id: <20250616112316.3833343-7-pinkesh.vaghela@einfochips.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250616112316.3833343-1-pinkesh.vaghela@einfochips.com> References: <20250616112316.3833343-1-pinkesh.vaghela@einfochips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-OriginalArrivalTime: 16 Jun 2025 11:23:16.0755 (UTC) FILETIME=[0E451E30:01DBDEB1] Content-Type: text/plain; charset="utf-8" From: Min Lin Add initial support for EIC7700 SoC that uses a SiFive Quad-Core P550 CPU cluster. This file is expected to grow as more device drivers are added to the kernel. Signed-off-by: Min Lin Co-developed-by: Pritesh Patel Signed-off-by: Pritesh Patel Co-developed-by: Darshan Prajapati Signed-off-by: Darshan Prajapati Reviewed-by: Samuel Holland Tested-by: Samuel Holland Signed-off-by: Pinkesh Vaghela --- MAINTAINERS | 2 + arch/riscv/boot/dts/eswin/eic7700.dtsi | 345 +++++++++++++++++++++++++ 2 files changed, 347 insertions(+) create mode 100644 arch/riscv/boot/dts/eswin/eic7700.dtsi diff --git a/MAINTAINERS b/MAINTAINERS index 8fadb4bae91f..84ecf004a59c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -8919,7 +8919,9 @@ M: Min Lin M: Pinkesh Vaghela M: Pritesh Patel S: Maintained +T: git https://github.com/eswincomputing/linux-next.git F: Documentation/devicetree/bindings/riscv/eswin.yaml +F: arch/riscv/boot/dts/eswin/ =20 ET131X NETWORK DRIVER M: Mark Einon diff --git a/arch/riscv/boot/dts/eswin/eic7700.dtsi b/arch/riscv/boot/dts/e= swin/eic7700.dtsi new file mode 100644 index 000000000000..c3ed93008bca --- /dev/null +++ b/arch/riscv/boot/dts/eswin/eic7700.dtsi @@ -0,0 +1,345 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (c) 2024 Beijing ESWIN Computing Technology Co., Ltd. + */ + +/dts-v1/; + +/ { + #address-cells =3D <2>; + #size-cells =3D <2>; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + timebase-frequency =3D <1000000>; + + cpu0: cpu@0 { + compatible =3D "sifive,p550", "riscv"; + device_type =3D "cpu"; + d-cache-block-size =3D <64>; + d-cache-sets =3D <128>; + d-cache-size =3D <32768>; + d-tlb-sets =3D <1>; + d-tlb-size =3D <32>; + i-cache-block-size =3D <64>; + i-cache-sets =3D <128>; + i-cache-size =3D <32768>; + i-tlb-sets =3D <1>; + i-tlb-size =3D <32>; + mmu-type =3D "riscv,sv48"; + next-level-cache =3D <&l2_cache_0>; + reg =3D <0x0>; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "h", "sscofpmf", + "zba", "zbb", "zicsr", "zifencei"; + tlb-split; + + cpu0_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + #interrupt-cells =3D <1>; + interrupt-controller; + }; + }; + + cpu1: cpu@1 { + compatible =3D "sifive,p550", "riscv"; + d-cache-block-size =3D <64>; + d-cache-sets =3D <128>; + d-cache-size =3D <32768>; + d-tlb-sets =3D <1>; + d-tlb-size =3D <32>; + device_type =3D "cpu"; + i-cache-block-size =3D <64>; + i-cache-sets =3D <128>; + i-cache-size =3D <32768>; + i-tlb-sets =3D <1>; + i-tlb-size =3D <32>; + mmu-type =3D "riscv,sv48"; + next-level-cache =3D <&l2_cache_1>; + reg =3D <0x1>; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "h", "sscofpmf", + "zba", "zbb", "zicsr", "zifencei"; + tlb-split; + + cpu1_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + #interrupt-cells =3D <1>; + interrupt-controller; + }; + }; + + cpu2: cpu@2 { + compatible =3D "sifive,p550", "riscv"; + d-cache-block-size =3D <64>; + d-cache-sets =3D <128>; + d-cache-size =3D <32768>; + d-tlb-sets =3D <1>; + d-tlb-size =3D <32>; + device_type =3D "cpu"; + i-cache-block-size =3D <64>; + i-cache-sets =3D <128>; + i-cache-size =3D <32768>; + i-tlb-sets =3D <1>; + i-tlb-size =3D <32>; + mmu-type =3D "riscv,sv48"; + next-level-cache =3D <&l2_cache_2>; + reg =3D <0x2>; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "h", "sscofpmf", + "zba", "zbb", "zicsr", "zifencei"; + tlb-split; + + cpu2_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + #interrupt-cells =3D <1>; + interrupt-controller; + }; + }; + + cpu3: cpu@3 { + compatible =3D "sifive,p550", "riscv"; + d-cache-block-size =3D <64>; + d-cache-sets =3D <128>; + d-cache-size =3D <32768>; + d-tlb-sets =3D <1>; + d-tlb-size =3D <32>; + device_type =3D "cpu"; + i-cache-block-size =3D <64>; + i-cache-sets =3D <128>; + i-cache-size =3D <32768>; + i-tlb-sets =3D <1>; + i-tlb-size =3D <32>; + mmu-type =3D "riscv,sv48"; + next-level-cache =3D <&l2_cache_3>; + reg =3D <0x3>; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "h", "sscofpmf", + "zba", "zbb", "zicsr", "zifencei"; + tlb-split; + + cpu3_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + #interrupt-cells =3D <1>; + interrupt-controller; + }; + }; + + l2_cache_0: l2-cache0 { + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-sets =3D <512>; + cache-size =3D <262144>; + cache-unified; + next-level-cache =3D <&ccache>; + }; + + l2_cache_1: l2-cache1 { + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-sets =3D <512>; + cache-size =3D <262144>; + cache-unified; + next-level-cache =3D <&ccache>; + }; + + l2_cache_2: l2-cache2 { + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-sets =3D <512>; + cache-size =3D <262144>; + cache-unified; + next-level-cache =3D <&ccache>; + }; + + l2_cache_3: l2-cache3 { + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-sets =3D <512>; + cache-size =3D <262144>; + cache-unified; + next-level-cache =3D <&ccache>; + }; + }; + + pmu { + compatible =3D "riscv,pmu"; + riscv,event-to-mhpmcounters =3D + <0x00001 0x00001 0x00000001>, + <0x00002 0x00002 0x00000004>, + <0x00004 0x00006 0x00000078>, + <0x10009 0x10009 0x00000078>, + <0x10019 0x10019 0x00000078>, + <0x10021 0x10021 0x00000078>; + riscv,event-to-mhpmevent =3D + <0x00004 0x00000000 0x00000202>, + <0x00005 0x00000000 0x00004000>, + <0x00006 0x00000000 0x00002001>, + <0x10009 0x00000000 0x00000102>, + <0x10019 0x00000000 0x00001002>, + <0x10021 0x00000000 0x00000802>; + riscv,raw-event-to-mhpmcounters =3D + <0x00000000 0x00000000 0xffffffff 0xfc0000ff 0x00000078>, + <0x00000000 0x00000001 0xffffffff 0xfffe07ff 0x00000078>, + <0x00000000 0x00000002 0xffffffff 0xfffe00ff 0x00000078>, + <0x00000000 0x00000003 0xfffffffc 0x000000ff 0x00000078>, + <0x00000000 0x00000004 0xffffffc0 0x000000ff 0x00000078>, + <0x00000000 0x00000005 0xffffffff 0xfffffdff 0x00000078>, + <0x00000000 0x00000006 0xfffffe00 0x110204ff 0x00000078>, + <0x00000000 0x00000007 0xffffffff 0xf00000ff 0x00000078>, + <0x00000000 0x00000008 0xfffffe04 0x000000ff 0x00000078>, + <0x00000000 0x00000009 0xffffffff 0xffffc0ff 0x00000078>, + <0x00000000 0x0000000a 0xffffffff 0xf00000ff 0x00000078>, + <0x00000000 0x0000000b 0xffffffff 0xfffffcff 0x00000078>, + <0x00000000 0x0000000c 0xfffffff0 0x000000ff 0x00000078>, + <0x00000000 0x0000000d 0xffffffff 0x800000ff 0x00000078>, + <0x00000000 0x0000000e 0xffffffff 0xf80000ff 0x00000078>, + <0x00000000 0x0000000f 0xfffffffc 0x000000ff 0x00000078>; + }; + + soc { + compatible =3D "simple-bus"; + ranges; + interrupt-parent =3D <&plic>; + #address-cells =3D <2>; + #size-cells =3D <2>; + dma-noncoherent; + + clint: timer@2000000 { + compatible =3D "eswin,eic7700-clint", "sifive,clint0"; + reg =3D <0x0 0x02000000 0x0 0x10000>; + interrupts-extended =3D + <&cpu0_intc 3>, <&cpu0_intc 7>, + <&cpu1_intc 3>, <&cpu1_intc 7>, + <&cpu2_intc 3>, <&cpu2_intc 7>, + <&cpu3_intc 3>, <&cpu3_intc 7>; + }; + + ccache: cache-controller@2010000 { + compatible =3D "eswin,eic7700-l3-cache", "sifive,ccache0", "cache"; + reg =3D <0x0 0x2010000 0x0 0x4000>; + interrupts =3D <1>, <3>, <4>, <2>; + cache-block-size =3D <64>; + cache-level =3D <3>; + cache-sets =3D <4096>; + cache-size =3D <4194304>; + cache-unified; + }; + + plic: interrupt-controller@c000000 { + compatible =3D "eswin,eic7700-plic", "sifive,plic-1.0.0"; + reg =3D <0x0 0xc000000 0x0 0x4000000>; + interrupt-controller; + interrupts-extended =3D + <&cpu0_intc 11>, <&cpu0_intc 9>, + <&cpu1_intc 11>, <&cpu1_intc 9>, + <&cpu2_intc 11>, <&cpu2_intc 9>, + <&cpu3_intc 11>, <&cpu3_intc 9>; + riscv,ndev =3D <520>; + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + }; + + uart0: serial@50900000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x0 0x50900000 0x0 0x10000>; + interrupts =3D <100>; + clock-frequency =3D <200000000>; + reg-io-width =3D <4>; + reg-shift =3D <2>; + status =3D "disabled"; + }; + + uart1: serial@50910000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x0 0x50910000 0x0 0x10000>; + interrupts =3D <101>; + clock-frequency =3D <200000000>; + reg-io-width =3D <4>; + reg-shift =3D <2>; + status =3D "disabled"; + }; + + uart2: serial@50920000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x0 0x50920000 0x0 0x10000>; + interrupts =3D <102>; + clock-frequency =3D <200000000>; + reg-io-width =3D <4>; + reg-shift =3D <2>; + status =3D "disabled"; + }; + + uart3: serial@50930000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x0 0x50930000 0x0 0x10000>; + interrupts =3D <103>; + clock-frequency =3D <200000000>; + reg-io-width =3D <4>; + reg-shift =3D <2>; + status =3D "disabled"; + }; + + uart4: serial@50940000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x0 0x50940000 0x0 0x10000>; + interrupts =3D <104>; + clock-frequency =3D <200000000>; + reg-io-width =3D <4>; + reg-shift =3D <2>; + status =3D "disabled"; + }; + + gpio@51600000 { + compatible =3D "snps,dw-apb-gpio"; + reg =3D <0x0 0x51600000 0x0 0x80>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + gpioA: gpio-port@0 { + compatible =3D "snps,dw-apb-gpio-port"; + reg =3D <0>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupts =3D + <303>, <304>, <305>, <306>, <307>, <308>, <309>, + <310>, <311>, <312>, <313>, <314>, <315>, <316>, + <317>, <318>, <319>, <320>, <321>, <322>, <323>, + <324>, <325>, <326>, <327>, <328>, <329>, <330>, + <331>, <332>, <333>, <334>; + gpio-controller; + ngpios =3D <32>; + #gpio-cells =3D <2>; + }; + + gpioB: gpio-port@1 { + compatible =3D "snps,dw-apb-gpio-port"; + reg =3D <1>; + gpio-controller; + ngpios =3D <32>; + #gpio-cells =3D <2>; + }; + + gpioC: gpio-port@2 { + compatible =3D "snps,dw-apb-gpio-port"; + reg =3D <2>; + gpio-controller; + ngpios =3D <32>; + #gpio-cells =3D <2>; + }; + + gpioD: gpio-port@3 { + compatible =3D "snps,dw-apb-gpio-port"; + reg =3D <3>; + gpio-controller; + ngpios =3D <16>; + #gpio-cells =3D <2>; + }; + }; + }; +}; --=20 2.25.1