From nobody Fri Oct 10 04:08:12 2025 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 26CBD28E594; Mon, 16 Jun 2025 03:11:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750043510; cv=none; b=lf0O30RFxqsRqyZXp/V3kJx+LuP2G+1FzHgMMQeO7MOxfMCgcyc838UT9W0KANI/9Y4ZPv9z8hFuoXHnBjDAkG5UEagPBSYkFhHV+mkFEKt9JeU1zcHivwkjukAJURTlVExf3EhwnjlXrzVHeTNU+P+VNIopw+rX4HMzGSbvB5M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750043510; c=relaxed/simple; bh=qf1MbNteaNFmIuHCeFXwy4QvVoxmZC5pLPaW/3wYq1g=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=OsZpZF9pRCdQxh99tFqLQapebRB2j7opNKpK3N/uPdL0ZrbumDfoD4Rcc3Xep2iOKgVbO2Jn2IG9sc1+0LZBfWFk0vfkfIPdUzqwjd1iURgxA8ZXy47KiapIm5k4ULmNPPy4auQllH6D27CjnZ3XztRqmBKoi/fLS9rXj4h6Sjg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=lF+ViI/Q; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="lF+ViI/Q" X-UUID: 848c90924a5d11f0b33aeb1e7f16c2b6-20250616 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=VBckLV6jNByzkSdMQw8AHIGDrw+A/A7qK4UW3zfX+Kk=; b=lF+ViI/Q55Q68ANrrcMRpas9q+fzGc4+qK7bItFPOojM6rJTXxnLHkMgLRojTMmCUrhN9mpNykZ8z+GmelHdJ1p7tpkqAkNL2ahA5yeFeGVQyx574RJp0xgRVPt+e0ZCSP28KeG30ZdK3mjmzv1fVo0jA7ZBzmgRkgwbs8w189I=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.2.3,REQID:b1412469-3fad-484e-aacd-083c9afda5d9,IP:0,UR L:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION:r elease,TS:0 X-CID-META: VersionHash:09905cf,CLOUDID:ce810277-7521-4364-b0ef-cd7d9c0ecbde,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102,TC:nil,Content:0|50,EDM:-3 ,IP:nil,URL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV :0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: 848c90924a5d11f0b33aeb1e7f16c2b6-20250616 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 985199707; Mon, 16 Jun 2025 10:56:36 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.39; Mon, 16 Jun 2025 10:56:34 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.39 via Frontend Transport; Mon, 16 Jun 2025 10:56:33 +0800 From: Xueqi Zhang To: Yong Wu , Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno CC: , Ning li , , , , , , Xueqi Zhang Subject: [RFC PATCH 1/8] dt-bindings: iommu: mediatek: Add mt8196 support Date: Mon, 16 Jun 2025 10:56:07 +0800 Message-ID: <20250616025628.25454-2-xueqi.zhang@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20250616025628.25454-1-xueqi.zhang@mediatek.com> References: <20250616025628.25454-1-xueqi.zhang@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" 1. Mediatek has its own implementation for wrapper interrupts and power management. Add the SoC specific compatible for MT8196 implementing arm,smmu-v3. 2. APU SMMU need wait until its power is ready, thus add a phandle smmu-mediatek-parents to its power node. Signed-off-by: Xueqi Zhang --- .../bindings/iommu/arm,smmu-v3.yaml | 24 ++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml b/Doc= umentation/devicetree/bindings/iommu/arm,smmu-v3.yaml index 75fcf4cb52d9..c9a99e54de69 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml @@ -20,7 +20,12 @@ properties: $nodename: pattern: "^iommu@[0-9a-f]*" compatible: - const: arm,smmu-v3 + - description: MediaTek SoCs implementing "arm,smmu-v3" + items: + - enum: + - mediatek,mt8196-apu-smmu + - mediatek,mt8196-mm-smmu + - const: arm,smmu-v3 =20 reg: maxItems: 1 @@ -69,11 +74,28 @@ properties: register access with page 0 offsets. Set for Cavium ThunderX2 silico= n that doesn't support SMMU page1 register space. =20 + mediatek,smmu-parents: + $ref: /schemas/types.yaml#/definitions/phandle + description: + A phandle to the SMMU's power node. The SMMU should wait until its p= ower + is ready + required: - compatible - reg - '#iommu-cells' =20 +allOf: + - if: # for SMMU need to wait its power node + properties: + compatible: + contains: + enum: + - mediatek,mt8196-apu-smmu + then: + required: + - mediatek,smmu-parents + additionalProperties: false =20 examples: --=20 2.46.0 From nobody Fri Oct 10 04:08:12 2025 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 346B417B50A; Mon, 16 Jun 2025 02:56:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.244.123.138 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750042606; cv=none; b=isq5jB9DZ3f3vew4+5mqhHCujx8EEHdBMJS0Xl0DhqI2GOQHUGvxehh/JbH34XHwh20QQLvpAEWTkjN/oytPYxW/3bIt3lb73Yribl5AKoemYtJHk8EDGmfKC55sb9vVGTpDwRNG+pwW1BMF29n50rRfQ67OUGwQEEk5b5rI2cc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750042606; c=relaxed/simple; bh=QTxndpX87zWcLNEBcDGGRY4zszTJXwnFeJhwseeADds=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=lbUwiXyHRmaFwGVS9N516Lm4xhdTCw2H5wXd2NdHo6eWlKR3x1tm1+Wb+mJ/U0SsSfhw2FzR4cLntYAeibQhm716TgHFoyvC1PEe0+Nx0mt4VAEzLn7HlQxCBuZzb5/4LadOIxwU3n/ru57QHJQAbfG0TnAFScVLafygWw/o1/Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=IZnFyciQ; arc=none smtp.client-ip=60.244.123.138 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="IZnFyciQ" X-UUID: 85ca8ffe4a5d11f0b910cdf5d4d8066a-20250616 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=mYmlyXHiNFhbRtbqPR7vS3N39bKSmKnGG7ZsjxUW5bQ=; b=IZnFyciQw7SEIA9pSs2ZUyqd4f1vPehHwj69n1W7IJFTy/gvpT8PhIN1LzcI7eGX1z4+SyBOCzOHzp0O0unOP7stw75k7dlxkwNNV3l1DgF7Ew4UtvAyQJgeohWu6VdRX63755MyYseXzrMt/PBmKPjasTVI8U2iz4WK78EyE+o=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.2.3,REQID:73dfd6af-10d2-44e3-a580-01c9e66a3860,IP:0,UR L:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION:r elease,TS:0 X-CID-META: VersionHash:09905cf,CLOUDID:be08b758-abad-4ac2-9923-3af0a8a9a079,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102,TC:nil,Content:0|50,EDM:-3 ,IP:nil,URL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV :0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: 85ca8ffe4a5d11f0b910cdf5d4d8066a-20250616 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 976834261; Mon, 16 Jun 2025 10:56:38 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.39; Mon, 16 Jun 2025 10:56:36 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.39 via Frontend Transport; Mon, 16 Jun 2025 10:56:35 +0800 From: Xueqi Zhang To: Yong Wu , Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno CC: , Ning li , , , , , , Xueqi Zhang Subject: [RFC PATCH 2/8] iommu/arm-smmu-v3: Add SMMU implementation Date: Mon, 16 Jun 2025 10:56:08 +0800 Message-ID: <20250616025628.25454-3-xueqi.zhang@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20250616025628.25454-1-xueqi.zhang@mediatek.com> References: <20250616025628.25454-1-xueqi.zhang@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Mediatek has its own implementation for wrapper interrupts and power management.So add SMMU implementation when smmu device probe. Signed-off-by: Xueqi Zhang --- drivers/iommu/arm/Kconfig | 7 +++++++ drivers/iommu/arm/arm-smmu-v3/Makefile | 3 ++- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-impl.c | 16 ++++++++++++++++ .../iommu/arm/arm-smmu-v3/arm-smmu-v3-mediatek.c | 13 +++++++++++++ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 3 +++ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 4 ++++ 6 files changed, 45 insertions(+), 1 deletion(-) create mode 100644 drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-impl.c create mode 100644 drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-mediatek.c diff --git a/drivers/iommu/arm/Kconfig b/drivers/iommu/arm/Kconfig index ef42bbe07dbe..a7f98fd0f2bf 100644 --- a/drivers/iommu/arm/Kconfig +++ b/drivers/iommu/arm/Kconfig @@ -88,6 +88,13 @@ config ARM_SMMU_V3 the ARM SMMUv3 architecture. =20 if ARM_SMMU_V3 +config ARM_SMMU_V3_MEDIATEK + bool "ARM Ltd. System MMU Version 3 (SMMUv3) MediaTek Support" + depends on ARM_SMMU_V3 && ARCH_MEDIATEK + help + When running on a MediaTek platform that has the custom variant + of the ARM SMMUv3, this needs to be built into the SMMU driver. + config ARM_SMMU_V3_SVA bool "Shared Virtual Addressing support for the ARM SMMUv3" select IOMMU_SVA diff --git a/drivers/iommu/arm/arm-smmu-v3/Makefile b/drivers/iommu/arm/arm= -smmu-v3/Makefile index 493a659cc66b..0670065d6e9a 100644 --- a/drivers/iommu/arm/arm-smmu-v3/Makefile +++ b/drivers/iommu/arm/arm-smmu-v3/Makefile @@ -1,7 +1,8 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_ARM_SMMU_V3) +=3D arm_smmu_v3.o -arm_smmu_v3-y :=3D arm-smmu-v3.o +arm_smmu_v3-y :=3D arm-smmu-v3.o arm-smmu-v3-impl.o arm_smmu_v3-$(CONFIG_ARM_SMMU_V3_IOMMUFD) +=3D arm-smmu-v3-iommufd.o +arm_smmu_v3-$(CONFIG_ARM_SMMU_V3_MEDIATEK) +=3D arm-smmu-v3-mediatek.o arm_smmu_v3-$(CONFIG_ARM_SMMU_V3_SVA) +=3D arm-smmu-v3-sva.o arm_smmu_v3-$(CONFIG_TEGRA241_CMDQV) +=3D tegra241-cmdqv.o =20 diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-impl.c b/drivers/iom= mu/arm/arm-smmu-v3/arm-smmu-v3-impl.c new file mode 100644 index 000000000000..d39587b965ef --- /dev/null +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-impl.c @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2025 MediaTek Inc. + * Author: Ning li + * Author: Xueqi Zhang + */ + +#include "arm-smmu-v3.h" + +struct arm_smmu_device *arm_smmu_v3_impl_init(struct arm_smmu_device *smmu) +{ +#if IS_ENABLED(CONFIG_ARM_SMMU_V3_MEDIATEK) + smmu =3D arm_smmu_v3_impl_mtk_init(smmu); +#endif + return smmu; +} diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-mediatek.c b/drivers= /iommu/arm/arm-smmu-v3/arm-smmu-v3-mediatek.c new file mode 100644 index 000000000000..381268968185 --- /dev/null +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-mediatek.c @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2025 MediaTek Inc. + * Author: Ning li + * Author: Xueqi Zhang + */ + +#include "arm-smmu-v3.h" + +struct arm_smmu_device *arm_smmu_v3_impl_mtk_init(struct arm_smmu_device *= smmu) +{ + return NULL; +} diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 10cc6dc26b7b..d36124a6bb54 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -4754,6 +4754,9 @@ static int arm_smmu_device_probe(struct platform_devi= ce *pdev) } ioaddr =3D res->start; =20 + smmu =3D arm_smmu_v3_impl_init(smmu); + if (IS_ERR(smmu)) + return PTR_ERR(smmu); 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charset="utf-8" Add implementation for mediatek MM SMMU. Signed-off-by: Xueqi Zhang --- .../arm/arm-smmu-v3/arm-smmu-v3-mediatek.c | 72 ++++++++++++++++++- 1 file changed, 71 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-mediatek.c b/drivers= /iommu/arm/arm-smmu-v3/arm-smmu-v3-mediatek.c index 381268968185..c00ee687d839 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-mediatek.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-mediatek.c @@ -4,10 +4,80 @@ * Author: Ning li * Author: Xueqi Zhang */ +#include +#include +#include +#include +#include +#include +#include =20 #include "arm-smmu-v3.h" =20 -struct arm_smmu_device *arm_smmu_v3_impl_mtk_init(struct arm_smmu_device *= smmu) +#define MTK_SMMU_COMP_STR_LEN 64 +#define MTK_SMMU_HAS_FLAG(pdata, _x) (!!(((pdata)->flags) & (_x))) + +enum mtk_smmu_type { + MTK_SMMU_MM, + MTK_SMMU_TYPE_NUM, +}; + +struct mtk_smmu_v3_plat { + enum mtk_smmu_type smmu_type; + u32 flags; +}; + +struct mtk_smmu_v3 { + struct arm_smmu_device smmu; + const struct mtk_smmu_v3_plat *plat_data; +}; + +static const struct mtk_smmu_v3_plat mt8196_data_mm =3D { + .smmu_type =3D MTK_SMMU_MM, +}; + +struct mtk_smmu_v3_of_device_data { + char compatible[MTK_SMMU_COMP_STR_LEN]; + const void *data; +}; + +static const struct mtk_smmu_v3_of_device_data mtk_smmu_v3_of_ids[] =3D { + { .compatible =3D "mediatek,mt8196-mm-smmu", .data =3D &mt8196_data_mm}, +}; + +static inline struct mtk_smmu_v3 *to_mtk_smmu_v3(struct arm_smmu_device *s= mmu) { + return container_of(smmu, struct mtk_smmu_v3, smmu); +} + +static const struct mtk_smmu_v3_plat *mtk_smmu_v3_get_plat_data(const stru= ct device_node *np) +{ + const struct mtk_smmu_v3_of_device_data *of_device =3D mtk_smmu_v3_of_ids; + int i; + + for (i =3D 0; i < ARRAY_SIZE(mtk_smmu_v3_of_ids); i++, of_device++) { + if (of_device_is_compatible(np, of_device->compatible)) + return of_device->data; + } return NULL; } + +struct arm_smmu_device *arm_smmu_v3_impl_mtk_init(struct arm_smmu_device *= smmu) +{ + struct mtk_smmu_v3 *mtk_smmu_v3; + struct device *dev =3D smmu->dev; + struct platform_device *parent_pdev; + struct device_node *parent_node; + + mtk_smmu_v3 =3D devm_krealloc(dev, smmu, sizeof(*mtk_smmu_v3), GFP_KERNEL= ); + if (!mtk_smmu_v3) + return ERR_PTR(-ENOMEM); + + mtk_smmu_v3->plat_data =3D mtk_smmu_v3_get_plat_data(dev->of_node); + if (!mtk_smmu_v3->plat_data) { + dev_err(dev, "Get platform data fail\n"); + return ERR_PTR(-EINVAL); + } + + return &mtk_smmu_v3->smmu; +} --=20 2.46.0 From nobody Fri Oct 10 04:08:12 2025 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BEBA02957AC; Mon, 16 Jun 2025 02:56:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.244.123.138 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750042611; cv=none; b=tO8ProWrvuQjiE+x1uTccyS9i9bAIwwTSrXXY76vPA2/Ax6lxBG5GeF5DjRj/wcpBTCPBatMWTYEGRXFhwnu/H/0y5qWXVeDCtU5ZthZFG73NEGx6b62CI7Lb7lgZqOklu32htKr/HZgdJDF/nAjWs+z8bImGD1H+ZtZwMEHUE4= ARC-Message-Signature: i=1; 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charset="utf-8" Add a special implementation for mediatek APU SMMU. APU SMMU need to wait APU SMMU's power which depends on APU driver. Therefore, add the label mediatek,smmu-parent to point to the power device that the smmu depends on. If the device has not finished probing, return -EPROBE_DEFER. Signed-off-by: Xueqi Zhang --- .../arm/arm-smmu-v3/arm-smmu-v3-mediatek.c | 32 +++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-mediatek.c b/drivers= /iommu/arm/arm-smmu-v3/arm-smmu-v3-mediatek.c index c00ee687d839..48290366e596 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-mediatek.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-mediatek.c @@ -15,10 +15,12 @@ #include "arm-smmu-v3.h" =20 #define MTK_SMMU_COMP_STR_LEN 64 +#define SMMU_REQUIRE_PARENT BIT(5) #define MTK_SMMU_HAS_FLAG(pdata, _x) (!!(((pdata)->flags) & (_x))) =20 enum mtk_smmu_type { MTK_SMMU_MM, + MTK_SMMU_APU, MTK_SMMU_TYPE_NUM, }; =20 @@ -36,12 +38,18 @@ static const struct mtk_smmu_v3_plat mt8196_data_mm =3D= { .smmu_type =3D MTK_SMMU_MM, }; =20 +static const struct mtk_smmu_v3_plat mt8196_data_apu =3D { + .smmu_type =3D MTK_SMMU_APU, + .flags =3D SMMU_REQUIRE_PARENT, +}; + struct mtk_smmu_v3_of_device_data { char compatible[MTK_SMMU_COMP_STR_LEN]; const void *data; }; =20 static const struct mtk_smmu_v3_of_device_data mtk_smmu_v3_of_ids[] =3D { + { .compatible =3D "mediatek,mt8196-apu-smmu", .data =3D &mt8196_data_apu}, { .compatible =3D "mediatek,mt8196-mm-smmu", .data =3D &mt8196_data_mm}, }; =20 @@ -79,5 +87,29 @@ struct arm_smmu_device *arm_smmu_v3_impl_mtk_init(struct= arm_smmu_device *smmu) return ERR_PTR(-EINVAL); } =20 + if (MTK_SMMU_HAS_FLAG(mtk_smmu_v3->plat_data, SMMU_REQUIRE_PARENT)) { + parent_node =3D of_parse_phandle(dev->of_node, "mediatek,smmu-parent", 0= ); + if (!parent_node) { + dev_err(dev, "Lack its parent node.\n"); + return ERR_PTR(-EINVAL); + } + if (!of_device_is_available(parent_node)) { + of_node_put(parent_node); + return ERR_PTR(-EINVAL); + } + + parent_pdev =3D of_find_device_by_node(parent_node); + of_node_put(parent_node); + if (!parent_pdev) { + dev_err(dev, "Lack its parent devices.\n"); + return ERR_PTR(-ENODEV); + } + + if (!platform_get_drvdata(parent_pdev)) { + dev_err(dev, "Delay since its parent driver is not ready.\n"); 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Mon, 16 Jun 2025 10:56:42 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.39 via Frontend Transport; Mon, 16 Jun 2025 10:56:41 +0800 From: Xueqi Zhang To: Yong Wu , Will Deacon , "Robin Murphy" , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno CC: , Ning li , , , , , , Xueqi Zhang Subject: [RFC PATCH 5/8] iommu/arm-smmu-v3: Add IRQ handle for smmu impl Date: Mon, 16 Jun 2025 10:56:11 +0800 Message-ID: <20250616025628.25454-6-xueqi.zhang@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20250616025628.25454-1-xueqi.zhang@mediatek.com> References: <20250616025628.25454-1-xueqi.zhang@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add IRQ handle for smmu impl Signed-off-by: Xueqi Zhang --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 9 ++++++++- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 8 ++++++++ 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index d36124a6bb54..154417b380fa 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1954,7 +1954,8 @@ static irqreturn_t arm_smmu_evtq_thread(int irq, void= *dev) arm_smmu_decode_event(smmu, evt, &event); if (arm_smmu_handle_event(smmu, evt, &event)) arm_smmu_dump_event(smmu, evt, &event, &rs); - + if (smmu->impl && smmu->impl->smmu_evt_handler) + smmu->impl->smmu_evt_handler(irq, smmu, evt, &rs); put_device(event.dev); cond_resched(); } @@ -2091,7 +2092,13 @@ static irqreturn_t arm_smmu_combined_irq_thread(int = irq, void *dev) =20 static irqreturn_t arm_smmu_combined_irq_handler(int irq, void *dev) { + struct arm_smmu_device *smmu =3D dev; + arm_smmu_gerror_handler(irq, dev); + + if (smmu->impl && smmu->impl->combined_irq_handle) + smmu->impl->combined_irq_handle(irq, smmu); + return IRQ_WAKE_THREAD; } =20 diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index 99eeb6143c49..f45c4bf84bc1 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -792,6 +792,7 @@ struct arm_smmu_device { =20 struct rb_root streams; struct mutex streams_mutex; + const struct arm_smmu_v3_impl *impl; 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charset="utf-8" Mediatek SMMU interrupt is low level active rather than the standard edge.Process Mediatek SMMU wrapper interrupt and dump detailed information when a translation fault occurs. Signed-off-by: Xueqi Zhang --- .../arm/arm-smmu-v3/arm-smmu-v3-mediatek.c | 349 +++++++++++++++++- 1 file changed, 347 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-mediatek.c b/drivers= /iommu/arm/arm-smmu-v3/arm-smmu-v3-mediatek.c index 48290366e596..448166c1ca64 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-mediatek.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-mediatek.c @@ -14,7 +14,122 @@ =20 #include "arm-smmu-v3.h" =20 +#include +#include + +#define SMMUWP_GLB_CTL0 (0x0) +#define CTL0_STD_AXI_MODE_DIS BIT(0) +#define CTL0_MON_DIS BIT(1) +#define CTL0_DCM_EN BIT(2) +#define CTL0_WRAPPER_CK_AOEN BIT(3) +#define CTL0_AUTO_AXDOMAIN_EN BIT(4) +#define CTL0_IRQ_BUSY_EN BIT(5) +#define CTL0_ABT_CNT_CLR BIT(6) +#define CTL0_LEGACY_AXCACHE BIT(7) +#define CTL0_COMMIT_DIS BIT(8) +#define CTL0_AUTO_SLP_DIS BIT(9) +#define CTL0_STTSL_DIS BIT(10) +#define CTL0_CFG_TAB_DCM_EN BIT(11) +#define CTL0_CPU_PARTID_DIS BIT(14) +/* New bits of SMMU wrapper extension */ +#define CTL0_TCU2SLC_DCM_EN BIT(18) +#define CTL0_APB_DCM_EN BIT(19) +#define CTL0_DVM_DCM_EN BIT(20) +#define CTL0_CPU_TBU_PARTID_DIS BIT(21) + +#define SMMUWP_IRQ_STA (0x80) +#define STA_TCU_GLB_INTR BIT(0) +#define STA_TCU_CMD_SYNC_INTR BIT(1) +#define STA_TCU_EVTQ_INTR BIT(2) +#define STA_TCU_PRI_INTR BIT(3) +#define STA_TCU_PMU_INTR BIT(4) +#define STA_TCU_RAS_CRI BIT(5) +#define STA_TCU_RAS_ERI BIT(6) +#define STA_TCU_RAS_FHI BIT(7) + +#define SMMUWP_IRQ_ACK (0x84) + +#define SMMUWP_IRQ_ACK_CNT (0x88) +#define IRQ_ACK_CNT_MSK GENMASK(7, 0) + +/* SMMU non-secure interrupt pending count register, count 20 */ +#define SMMUWP_IRQ_CNTx(cnt) (0x100 + 0x4 * (cnt)) + +#define SMMU_TCU_CTL1_AXSLC (0x204) +#define AXSLC_BIT_FIELD GENMASK(8, 4) +#define AXSLC_CACHE BIT(5) +#define AXSLC_ALLOCATE BIT(6) +#define AXSLC_SPECULATIVE BIT(7) +#define AXSLC_SET (AXSLC_CACHE | AXSLC_ALLOCATE | AXSLC_SPECULATIVE) +#define SLC_SB_ONLY_EN BIT(1) + +/* SMMU TBUx read translation fault monitor0 */ +#define SMMUWP_TBUx_RTFM0(tbu) (0x380 + 0x100 * (tbu)) +#define RTFM0_FAULT_AXI_ID GENMASK_ULL(19, 0) +#define RTFM0_FAULT_DET BIT(31) + +/* SMMU TBUx read translation fault monitor1 */ +#define SMMUWP_TBUx_RTFM1(tbu) (0x384 + 0x100 * (tbu)) +#define RTFM1_FAULT_VA_35_32 GENMASK_ULL(3, 0) +#define RTFM1_FAULT_VA_31_12 GENMASK_ULL(31, 12) + +/* SMMU TBUx read translation fault monitor2 */ +#define SMMUWP_TBUx_RTFM2(tbu) (0x388 + 0x100 * (tbu)) +#define RTFM2_FAULT_SID GENMASK_ULL(7, 0) +#define RTFM2_FAULT_SSID GENMASK_ULL(15, 8) +#define RTFM2_FAULT_SSIDV BIT(16) +#define RTFM2_FAULT_SECSID BIT(17) + +/* SMMU TBUx write translation fault monitor0 */ +#define SMMUWP_TBUx_WTFM0(tbu) (0x390 + 0x100 * (tbu)) +#define WTFM0_FAULT_AXI_ID GENMASK_ULL(19, 0) +#define WTFM0_FAULT_DET BIT(31) + +/* SMMU TBUx write translation fault monitor1 */ +#define SMMUWP_TBUx_WTFM1(tbu) (0x394 + 0x100 * (tbu)) +#define WTFM1_FAULT_VA_35_32 GENMASK_ULL(3, 0) +#define WTFM1_FAULT_VA_31_12 GENMASK_ULL(31, 12) + +/* SMMU TBUx write translation fault monitor2 */ +#define SMMUWP_TBUx_WTFM2(tbu) (0x398 + 0x100 * (tbu)) +#define WTFM2_FAULT_SID GENMASK_ULL(7, 0) +#define WTFM2_FAULT_SSID GENMASK_ULL(15, 8) +#define WTFM2_FAULT_SSIDV BIT(16) +#define WTFM2_FAULT_SECSID BIT(17) + +/* SMMU TBU Manual OG Control High Register0 */ +#define SMMUWP_TBU0_MOGH0 (0x3b4) +#define MOGH_EN BIT(29) +#define MOGH_RW BIT(28) + +/* SMMU translation fault TBUx */ +#define SMMUWP_TF_TBU_MSK GENMASK(26, 24) +#define SMMUWP_TF_TBU(tbu) FIELD_PREP(SMMUWP_TF_TBU_MSK, tbu) + +#define SMMU_FAULT_RS_INTERVAL DEFAULT_RATELIMIT_INTERVAL +#define SMMU_FAULT_RS_BURST (1) + +#define STRSEC(sec) ((sec) ? "SECURE" : "NORMAL") + +#define WP_OFFSET_MT8196 0x1e0000 + #define MTK_SMMU_COMP_STR_LEN 64 + +#define MTK_SMMU_FAULT_IOVA(low, high) ((low) | (((u64)(high) & 0xf) << 32= )) + +#define SMMU_SUCCESS (0) +#define SMMU_ID_ERR (1) +#define SMMU_CMD_ERR (2) +#define SMMU_PARA_INVALID (3) +#define SMMU_NEED (4) +#define SMMU_NONEED (5) + +/* plat flags: */ +#define SMMU_SKIP_PM_CLK BIT(0) +#define SMMU_CLK_AO_EN BIT(1) +#define SMMU_AXSLC_EN BIT(2) +#define SMMU_DIS_CPU_PARTID BIT(3) +#define SMMU_DIS_CPU_TBU_PARTID BIT(4) #define SMMU_REQUIRE_PARENT BIT(5) #define MTK_SMMU_HAS_FLAG(pdata, _x) (!!(((pdata)->flags) & (_x))) =20 @@ -25,22 +140,30 @@ enum mtk_smmu_type { }; =20 struct mtk_smmu_v3_plat { + u32 wp_offset; + unsigned int tbu_cnt; enum mtk_smmu_type smmu_type; u32 flags; }; =20 struct mtk_smmu_v3 { struct arm_smmu_device smmu; + void __iomem *wp_base; const struct mtk_smmu_v3_plat *plat_data; }; =20 static const struct mtk_smmu_v3_plat mt8196_data_mm =3D { + .wp_offset =3D WP_OFFSET_MT8196, + .tbu_cnt =3D 3, .smmu_type =3D MTK_SMMU_MM, + .flags =3D SMMU_AXSLC_EN, }; =20 static const struct mtk_smmu_v3_plat mt8196_data_apu =3D { + .wp_offset =3D WP_OFFSET_MT8196, + .tbu_cnt =3D 3, .smmu_type =3D MTK_SMMU_APU, - .flags =3D SMMU_REQUIRE_PARENT, + .flags =3D SMMU_AXSLC_EN | SMMU_REQUIRE_PARENT, }; =20 struct mtk_smmu_v3_of_device_data { @@ -70,17 +193,228 @@ static const struct mtk_smmu_v3_plat *mtk_smmu_v3_get= _plat_data(const struct dev return NULL; } =20 +static inline void smmu_write_field(void __iomem *base, + unsigned int reg, + unsigned int mask, + unsigned int val) +{ + unsigned int regval; + + regval =3D readl_relaxed(base + reg); + regval =3D (regval & (~mask)) | val; + writel_relaxed(regval, base + reg); +} + +static void smmu_init_wpcfg(struct arm_smmu_device *smmu) +{ + struct mtk_smmu_v3 *mtk_smmu_v3 =3D to_mtk_smmu_v3(smmu); + void __iomem *wp_base =3D mtk_smmu_v3->wp_base; + + /* DCM basic setting */ + smmu_write_field(wp_base, SMMUWP_GLB_CTL0, CTL0_DCM_EN, CTL0_DCM_EN); + smmu_write_field(wp_base, SMMUWP_GLB_CTL0, CTL0_CFG_TAB_DCM_EN, + CTL0_CFG_TAB_DCM_EN); + + smmu_write_field(wp_base, SMMUWP_GLB_CTL0, + CTL0_TCU2SLC_DCM_EN | CTL0_APB_DCM_EN | + CTL0_DVM_DCM_EN, + CTL0_TCU2SLC_DCM_EN | CTL0_APB_DCM_EN | + CTL0_DVM_DCM_EN); + + if (MTK_SMMU_HAS_FLAG(mtk_smmu_v3->plat_data, SMMU_DIS_CPU_PARTID)) + smmu_write_field(wp_base, SMMUWP_GLB_CTL0, CTL0_CPU_PARTID_DIS, + CTL0_CPU_PARTID_DIS); + if (MTK_SMMU_HAS_FLAG(mtk_smmu_v3->plat_data, SMMU_DIS_CPU_TBU_PARTID)) + smmu_write_field(wp_base, SMMUWP_GLB_CTL0, + CTL0_CPU_TBU_PARTID_DIS, CTL0_CPU_TBU_PARTID_DIS); + + /* Used for MM_SMMMU read command overtaking */ + if (mtk_smmu_v3->plat_data->smmu_type =3D=3D MTK_SMMU_MM) + smmu_write_field(wp_base, SMMUWP_GLB_CTL0, CTL0_STD_AXI_MODE_DIS, + CTL0_STD_AXI_MODE_DIS); + + /* Set AXSLC */ + if (MTK_SMMU_HAS_FLAG(mtk_smmu_v3->plat_data, SMMU_AXSLC_EN)) { + smmu_write_field(wp_base, SMMUWP_GLB_CTL0, + CTL0_STD_AXI_MODE_DIS, CTL0_STD_AXI_MODE_DIS); + smmu_write_field(wp_base, SMMU_TCU_CTL1_AXSLC, AXSLC_BIT_FIELD, + AXSLC_SET); + smmu_write_field(wp_base, SMMU_TCU_CTL1_AXSLC, SLC_SB_ONLY_EN, + SLC_SB_ONLY_EN); + } +} + +/* Consume SMMU wrapper interrupt bit */ +static unsigned int +smmuwp_consume_intr(void __iomem *wp_base, unsigned int irq_bit) +{ + unsigned int pend_cnt; + + pend_cnt =3D readl_relaxed(wp_base + SMMUWP_IRQ_CNTx(__ffs(irq_bit))); + smmu_write_field(wp_base, SMMUWP_IRQ_ACK_CNT, IRQ_ACK_CNT_MSK, pend_cnt); + writel_relaxed(irq_bit, wp_base + SMMUWP_IRQ_ACK); + + return pend_cnt; +} + +/* clear translation fault mark */ +static void smmuwp_clear_tf(void __iomem *wp_base) +{ + smmu_write_field(wp_base, SMMUWP_GLB_CTL0, CTL0_ABT_CNT_CLR, CTL0_ABT_CNT= _CLR); + smmu_write_field(wp_base, SMMUWP_GLB_CTL0, CTL0_ABT_CNT_CLR, 0); +} + +static u32 smmuwp_fault_id(u32 axi_id, u32 tbu_id) +{ + u32 fault_id =3D (axi_id & ~SMMUWP_TF_TBU_MSK) | (SMMUWP_TF_TBU(tbu_id)); + + return fault_id; +} + +/* Process TBU translation fault Monitor */ +static bool smmuwp_process_tf(struct arm_smmu_device *smmu) +{ + struct mtk_smmu_v3 *mtk_smmu_v3 =3D to_mtk_smmu_v3(smmu); + void __iomem *wp_base =3D mtk_smmu_v3->wp_base; + unsigned int sid, ssid, secsidv, ssidv; + u32 i, regval, va35_32, axiid, fault_id; + u64 fault_iova; + bool tf_det =3D false; + + for (i =3D 0; i < mtk_smmu_v3->plat_data->tbu_cnt; i++) { + regval =3D readl_relaxed(wp_base + SMMUWP_TBUx_RTFM0(i)); + if (!(regval & RTFM0_FAULT_DET)) + goto write; + + tf_det =3D true; + axiid =3D FIELD_GET(RTFM0_FAULT_AXI_ID, regval); + fault_id =3D smmuwp_fault_id(axiid, i); + + regval =3D readl_relaxed(wp_base + SMMUWP_TBUx_RTFM1(i)); + va35_32 =3D FIELD_GET(RTFM1_FAULT_VA_35_32, regval); + fault_iova =3D MTK_SMMU_FAULT_IOVA(regval & RTFM1_FAULT_VA_31_12, va35_3= 2); + + regval =3D readl_relaxed(wp_base + SMMUWP_TBUx_RTFM2(i)); + sid =3D FIELD_GET(RTFM2_FAULT_SID, regval); + ssid =3D FIELD_GET(RTFM2_FAULT_SSID, regval); + ssidv =3D FIELD_GET(RTFM2_FAULT_SSIDV, regval); + secsidv =3D FIELD_GET(RTFM2_FAULT_SECSID, regval); + dev_err_ratelimited(smmu->dev, "TF read in %s world, TBU_id-%d-fault_id:= 0x%x(0x%x)\n", + STRSEC(secsidv), i, fault_id, axiid); + dev_err_ratelimited(smmu->dev, + "iova:0x%llx, sid:%d, ssid:%d, ssidv:%d, secsidv:%d\n", + fault_iova, sid, ssid, ssidv, secsidv); + +write: + regval =3D readl_relaxed(wp_base + SMMUWP_TBUx_WTFM0(i)); + if (!(regval & WTFM0_FAULT_DET)) + continue; + + tf_det =3D true; + axiid =3D FIELD_GET(WTFM0_FAULT_AXI_ID, regval); + fault_id =3D smmuwp_fault_id(axiid, i); + + regval =3D readl_relaxed(wp_base + SMMUWP_TBUx_WTFM1(i)); + va35_32 =3D FIELD_GET(WTFM1_FAULT_VA_35_32, regval); + fault_iova =3D MTK_SMMU_FAULT_IOVA(regval & RTFM1_FAULT_VA_31_12, va35_3= 2); + + regval =3D readl_relaxed(wp_base + SMMUWP_TBUx_WTFM2(i)); + sid =3D FIELD_GET(WTFM2_FAULT_SID, regval); + ssid =3D FIELD_GET(WTFM2_FAULT_SSID, regval); + ssidv =3D FIELD_GET(WTFM2_FAULT_SSIDV, regval); + secsidv =3D FIELD_GET(WTFM2_FAULT_SECSID, regval); + dev_err_ratelimited(smmu->dev, "TF write in %s world, TBU_id-%d-fault_id= :0x%x(0x%x)\n", + STRSEC(secsidv), i, fault_id, axiid); + dev_err_ratelimited(smmu->dev, + "iova:0x%llx, sid:%d, ssid:%d, ssidv:%d, secsidv:%d\n", + fault_iova, sid, ssid, ssidv, secsidv); + } + + if (!tf_det) + dev_info(smmu->dev, "No TF detected or has been cleaned\n"); + + return tf_det; +} + +static int +mtk_smmu_evt_handler(int irq, struct arm_smmu_device *smmu, u64 *evt, stru= ct ratelimit_state *rs) +{ + if (!__ratelimit(rs)) { + smmuwp_clear_tf(smmu); + return 0; + } + + smmuwp_process_tf(smmu); + smmuwp_clear_tf(smmu); + + return 0; +} + +/* Process SMMU wrapper interrupt */ +static int mtk_smmu_v3_smmuwp_irq_handler(int irq, struct arm_smmu_device = *smmu) +{ + struct mtk_smmu_v3 *mtk_smmuv3 =3D to_mtk_smmu_v3(smmu); + void __iomem *wp_base =3D mtk_smmuv3->wp_base; + unsigned int irq_sta, pend_cnt; + + irq_sta =3D readl_relaxed(wp_base + SMMUWP_IRQ_STA); + if (irq_sta =3D=3D 0) + return 0; + + if (irq_sta & STA_TCU_GLB_INTR) { + pend_cnt =3D smmuwp_consume_intr(wp_base, STA_TCU_GLB_INTR); + dev_dbg(smmu->dev, + "IRQ_STA:0x%x, Non-secure TCU global interrupt detected pending_cnt: %d= \n", + irq_sta, pend_cnt); + } + + if (irq_sta & STA_TCU_CMD_SYNC_INTR) { + pend_cnt =3D smmuwp_consume_intr(wp_base, STA_TCU_CMD_SYNC_INTR); + dev_dbg(smmu->dev, + "IRQ_STA:0x%x, Non-secure TCU CMD_SYNC interrupt detected pending_cnt: = %d\n", + irq_sta, pend_cnt); + } + + if (irq_sta & STA_TCU_EVTQ_INTR) { + pend_cnt =3D smmuwp_consume_intr(wp_base, STA_TCU_EVTQ_INTR); + dev_dbg(smmu->dev, + "IRQ_STA:0x%x, Non-secure TCU EVTQ interrupt detected pending_cnt: %d\n= ", + irq_sta, pend_cnt); + } + + if (irq_sta & STA_TCU_PRI_INTR) { + pend_cnt =3D smmuwp_consume_intr(wp_base, STA_TCU_PRI_INTR); + dev_dbg(smmu->dev, "IRQ_STA:0x%x, TCU PRI interrupt detected pending_cnt= : %d\n", + irq_sta, pend_cnt); + } + + if (irq_sta & STA_TCU_PMU_INTR) { + pend_cnt =3D smmuwp_consume_intr(wp_base, STA_TCU_PMU_INTR); + dev_dbg(smmu->dev, "IRQ_STA:0x%x, TCU PMU interrupt detected pending_cnt= : %d\n", + irq_sta, pend_cnt); + } + + return 0; +} + +static const struct arm_smmu_v3_impl mtk_smmu_v3_impl =3D { + .combined_irq_handle =3D mtk_smmu_v3_smmuwp_irq_handler, + .smmu_evt_handler =3D mtk_smmu_evt_handler, +}; + struct arm_smmu_device *arm_smmu_v3_impl_mtk_init(struct arm_smmu_device *= smmu) { struct mtk_smmu_v3 *mtk_smmu_v3; struct device *dev =3D smmu->dev; - struct platform_device *parent_pdev; + struct platform_device *pdev =3D to_platform_device(dev), *parent_pdev; + struct resource *res, wp_res; struct device_node *parent_node; =20 mtk_smmu_v3 =3D devm_krealloc(dev, smmu, sizeof(*mtk_smmu_v3), GFP_KERNEL= ); if (!mtk_smmu_v3) return ERR_PTR(-ENOMEM); =20 + mtk_smmu_v3->smmu.impl =3D &mtk_smmu_v3_impl; mtk_smmu_v3->plat_data =3D mtk_smmu_v3_get_plat_data(dev->of_node); if (!mtk_smmu_v3->plat_data) { dev_err(dev, "Get platform data fail\n"); @@ -111,5 +445,16 @@ struct arm_smmu_device *arm_smmu_v3_impl_mtk_init(stru= ct arm_smmu_device *smmu) } } =20 + res =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return ERR_PTR(-EINVAL); + wp_res =3D DEFINE_RES_MEM(res->start + mtk_smmu_v3->plat_data->wp_offset,= SZ_4K); + mtk_smmu_v3->wp_base =3D devm_ioremap_resource(dev, &wp_res); + if (IS_ERR(mtk_smmu_v3->wp_base)) + return mtk_smmu_v3->wp_base; + + mtk_smmu_pm_get(dev, mtk_smmu_v3->plat_data->smmu_type); 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Mon, 16 Jun 2025 10:56:48 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.39; Mon, 16 Jun 2025 10:56:46 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.39 via Frontend Transport; Mon, 16 Jun 2025 10:56:45 +0800 From: Xueqi Zhang To: Yong Wu , Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno CC: , Ning li , , , , , , Xueqi Zhang Subject: [RFC PATCH 7/8] iommu/arm-smmu-v3: Invoke rpm operation before accessing the hw Date: Mon, 16 Jun 2025 10:56:13 +0800 Message-ID: <20250616025628.25454-8-xueqi.zhang@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20250616025628.25454-1-xueqi.zhang@mediatek.com> References: <20250616025628.25454-1-xueqi.zhang@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Invoke rpm operation before accessing the SMMU hw. Signed-off-by: Xueqi Zhang --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 84 ++++++++++++++++++++- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 3 + 2 files changed, 85 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 154417b380fa..88912b0f8132 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -122,6 +122,22 @@ static void parse_driver_options(struct arm_smmu_devic= e *smmu) } while (arm_smmu_options[++i].opt); } =20 +static int arm_smmu_rpm_get(struct arm_smmu_device *smmu) +{ + if (smmu && smmu->impl && smmu->impl->smmu_power_get) + return smmu->impl->smmu_power_get(smmu); + + return 0; +} + +static int arm_smmu_rpm_put(struct arm_smmu_device *smmu) +{ + if (smmu && smmu->impl && smmu->impl->smmu_power_put) + return smmu->impl->smmu_power_put(smmu); + + return 0; +} + /* Low-level queue manipulation functions */ static bool queue_has_space(struct arm_smmu_ll_queue *q, u32 n) { @@ -2082,23 +2098,35 @@ static irqreturn_t arm_smmu_gerror_handler(int irq,= void *dev) static irqreturn_t arm_smmu_combined_irq_thread(int irq, void *dev) { struct arm_smmu_device *smmu =3D dev; + int ret; + + ret =3D arm_smmu_rpm_get(smmu); + if (ret) + return IRQ_NONE; =20 arm_smmu_evtq_thread(irq, dev); if (smmu->features & ARM_SMMU_FEAT_PRI) arm_smmu_priq_thread(irq, dev); =20 + arm_smmu_rpm_put(smmu); return IRQ_HANDLED; } =20 static irqreturn_t arm_smmu_combined_irq_handler(int irq, void *dev) { struct arm_smmu_device *smmu =3D dev; + int ret; + + ret =3D arm_smmu_rpm_get(smmu); + if (ret) + return IRQ_WAKE_THREAD; =20 arm_smmu_gerror_handler(irq, dev); =20 if (smmu->impl && smmu->impl->combined_irq_handle) smmu->impl->combined_irq_handle(irq, smmu); =20 + arm_smmu_rpm_put(smmu); return IRQ_WAKE_THREAD; } =20 @@ -2255,6 +2283,11 @@ static void arm_smmu_tlb_inv_context(void *cookie) struct arm_smmu_domain *smmu_domain =3D cookie; struct arm_smmu_device *smmu =3D smmu_domain->smmu; struct arm_smmu_cmdq_ent cmd; + int ret; + + ret =3D arm_smmu_rpm_get(smmu); + if (ret) + return; =20 /* * NOTE: when io-pgtable is in non-strict mode, we may get here with @@ -2271,6 +2304,8 @@ static void arm_smmu_tlb_inv_context(void *cookie) arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd); } arm_smmu_atc_inv_domain(smmu_domain, 0, 0); + + arm_smmu_rpm_put(smmu); } =20 static void __arm_smmu_tlb_inv_range(struct arm_smmu_cmdq_ent *cmd, @@ -2353,6 +2388,11 @@ static void arm_smmu_tlb_inv_range_domain(unsigned l= ong iova, size_t size, .leaf =3D leaf, }, }; + int ret; + + ret =3D arm_smmu_rpm_get(smmu_domain->smmu); + if (ret) + return; =20 if (smmu_domain->stage =3D=3D ARM_SMMU_DOMAIN_S1) { cmd.opcode =3D smmu_domain->smmu->features & ARM_SMMU_FEAT_E2H ? @@ -2378,6 +2418,8 @@ static void arm_smmu_tlb_inv_range_domain(unsigned lo= ng iova, size_t size, * zapped an entire table. */ arm_smmu_atc_inv_domain(smmu_domain, iova, size); + + arm_smmu_rpm_put(smmu_domain->smmu); } =20 void arm_smmu_tlb_inv_range_asid(unsigned long iova, size_t size, int asid, @@ -2392,8 +2434,15 @@ void arm_smmu_tlb_inv_range_asid(unsigned long iova,= size_t size, int asid, .leaf =3D leaf, }, }; + int ret; + + ret =3D arm_smmu_rpm_get(smmu_domain->smmu); + if (ret) + return; =20 __arm_smmu_tlb_inv_range(&cmd, iova, size, granule, smmu_domain); + + arm_smmu_rpm_put(smmu_domain->smmu); } =20 static void arm_smmu_tlb_inv_page_nosync(struct iommu_iotlb_gather *gather, @@ -3038,6 +3087,12 @@ static int arm_smmu_attach_dev(struct iommu_domain *= domain, struct device *dev) } else if (arm_smmu_ssids_in_use(&master->cd_table)) return -EBUSY; =20 + ret =3D arm_smmu_rpm_get(smmu); + if (ret) { + dev_info(smmu->dev, "[%s] power_status:%d\n", __func__, ret); + return -EBUSY; + } + /* * Prevent arm_smmu_share_asid() from trying to change the ASID * of either the old or new domain while we are working on it. @@ -3049,6 +3104,7 @@ static int arm_smmu_attach_dev(struct iommu_domain *d= omain, struct device *dev) ret =3D arm_smmu_attach_prepare(&state, domain); if (ret) { mutex_unlock(&arm_smmu_asid_lock); + arm_smmu_rpm_put(smmu); return ret; } =20 @@ -3074,6 +3130,7 @@ static int arm_smmu_attach_dev(struct iommu_domain *d= omain, struct device *dev) =20 arm_smmu_attach_commit(&state); mutex_unlock(&arm_smmu_asid_lock); + arm_smmu_rpm_put(smmu); return 0; } =20 @@ -3216,7 +3273,13 @@ static void arm_smmu_attach_dev_ste(struct iommu_dom= ain *domain, .old_domain =3D iommu_get_domain_for_dev(dev), .ssid =3D IOMMU_NO_PASID, }; + int ret; =20 + ret =3D arm_smmu_rpm_get(master->smmu); + if (ret) { + dev_info(master->smmu->dev, "[%s] power_status:%d\n", __func__, ret); + return; + } /* * Do not allow any ASID to be changed while are working on the STE, * otherwise we could miss invalidations. @@ -3244,7 +3307,7 @@ static void arm_smmu_attach_dev_ste(struct iommu_doma= in *domain, arm_smmu_install_ste_for_dev(master, ste); arm_smmu_attach_commit(&state); mutex_unlock(&arm_smmu_asid_lock); - + arm_smmu_rpm_put(master->smmu); /* * This has to be done after removing the master from the * arm_smmu_domain->devices to avoid races updating the same context @@ -4799,10 +4862,17 @@ static int arm_smmu_device_probe(struct platform_de= vice *pdev) if (irq > 0) smmu->gerr_irq =3D irq; } + + ret =3D arm_smmu_rpm_get(smmu); + if (ret) { + dev_info(smmu->dev, "[%s] power_status fail:%d\n", __func__, ret); + return ret; + } + /* Probe the h/w */ ret =3D arm_smmu_device_hw_probe(smmu); if (ret) - return ret; + goto err_pm_put; =20 /* Initialise in-memory data structures */ ret =3D arm_smmu_init_structures(smmu); @@ -4840,6 +4910,8 @@ static int arm_smmu_device_probe(struct platform_devi= ce *pdev) arm_smmu_device_disable(smmu); err_free_iopf: iopf_queue_free(smmu->evtq.iopf); +err_pm_put: + arm_smmu_rpm_put(smmu); return ret; } =20 @@ -4857,8 +4929,16 @@ static void arm_smmu_device_remove(struct platform_d= evice *pdev) static void arm_smmu_device_shutdown(struct platform_device *pdev) { struct arm_smmu_device *smmu =3D platform_get_drvdata(pdev); + int ret; =20 + ret =3D arm_smmu_rpm_get(smmu); + if (ret) { + dev_info(smmu->dev, "[%s] power_status:%d\n", __func__, ret); + return; + } arm_smmu_device_disable(smmu); + + arm_smmu_rpm_put(smmu); } =20 static const struct of_device_id arm_smmu_of_match[] =3D { diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index f45c4bf84bc1..cd96ff9cbc54 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -792,6 +792,7 @@ struct arm_smmu_device { =20 struct rb_root streams; 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Mon, 16 Jun 2025 10:56:49 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.39; Mon, 16 Jun 2025 10:56:48 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.39 via Frontend Transport; Mon, 16 Jun 2025 10:56:47 +0800 From: Xueqi Zhang To: Yong Wu , Will Deacon , "Robin Murphy" , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno CC: , Ning li , , , , , , Xueqi Zhang Subject: [RFC PATCH 8/8] iommu/arm-smmu-v3: mediatek: Implement rpm get/put function Date: Mon, 16 Jun 2025 10:56:14 +0800 Message-ID: <20250616025628.25454-9-xueqi.zhang@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20250616025628.25454-1-xueqi.zhang@mediatek.com> References: <20250616025628.25454-1-xueqi.zhang@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In some projects, we also have EL2 driver, so we put the pm operation in TFA(EL3), then all the kernel and EL2 could control the pm. Implement rpm get/put function which send smc call to ATF to get/put SMMU power. Signed-off-by: Xueqi Zhang --- .../arm/arm-smmu-v3/arm-smmu-v3-mediatek.c | 78 +++++++++++++++++++ 1 file changed, 78 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-mediatek.c b/drivers= /iommu/arm/arm-smmu-v3/arm-smmu-v3-mediatek.c index 448166c1ca64..38c995e90469 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-mediatek.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-mediatek.c @@ -397,9 +397,87 @@ static int mtk_smmu_v3_smmuwp_irq_handler(int irq, str= uct arm_smmu_device *smmu) return 0; } =20 +/* + * SMMU TF-A SMC cmd format: + * sec[11:11] + smmu_type[10:8] + cmd_id[7:0] + */ +#define SMMU_ATF_SET_CMD(smmu_type, sec, cmd_id) \ + ((cmd_id) | ((smmu_type) << 8) | ((sec) << 11)) + +enum smmu_atf_cmd { + SMMU_SECURE_PM_GET, + SMMU_SECURE_PM_PUT, + SMMU_CMD_NUM +}; + +/* + * a0/in0 =3D MTK_IOMMU_SECURE_CONTROL(IOMMU SMC ID) + * a1/in1 =3D SMMU TF-A SMC cmd (sec + smmu_type + cmd_id) + * a2/in2 ~ a7/in7: user defined + */ +static int mtk_smmu_atf_call(u32 smmu_type, unsigned long cmd, + unsigned long in2, unsigned long in3, unsigned long in4, + unsigned long in5, unsigned long in6, unsigned long in7) +{ + struct arm_smccc_res res; + + arm_smccc_smc(MTK_SIP_KERNEL_IOMMU_CONTROL, cmd, in2, in3, in4, in5, in6,= in7, &res); + + return res.a0; +} + +static int mtk_smmu_atf_call_common(u32 smmu_type, unsigned long cmd_id) +{ + unsigned long cmd =3D SMMU_ATF_SET_CMD(smmu_type, 1, cmd_id); + + return mtk_smmu_atf_call(smmu_type, cmd, 0, 0, 0, 0, 0, 0); +} + +static int mtk_smmu_pm_get(struct device *dev, uint32_t smmu_type) +{ + int ret; + + ret =3D mtk_smmu_atf_call_common(smmu_type, SMMU_SECURE_PM_GET); + if (ret) { + dev_dbg(dev, "%s, smc call fail. ret:%d, type:%u\n", __func__, ret, smmu= _type); + return -ENODEV; + } + return 0; +} + +static int mtk_smmu_pm_put(struct device *dev, uint32_t smmu_type) +{ + int ret; + + ret =3D mtk_smmu_atf_call_common(smmu_type, SMMU_SECURE_PM_PUT); + if (ret) { + dev_dbg(dev, "%s, smc call fail:%d, type:%u\n", __func__, ret, smmu_type= ); + return -EINVAL; + } + return 0; +} + +static int mtk_smmu_power_get(struct arm_smmu_device *smmu) +{ + struct mtk_smmu_v3 *mtk_smmuv3 =3D to_mtk_smmu_v3(smmu); + const struct mtk_smmu_v3_plat *plat_data =3D mtk_smmuv3->plat_data; + + return mtk_smmu_pm_get(smmu->dev, plat_data->smmu_type); +} + +static int mtk_smmu_power_put(struct arm_smmu_device *smmu) +{ + struct mtk_smmu_v3 *mtk_smmuv3 =3D to_mtk_smmu_v3(smmu); + const struct mtk_smmu_v3_plat *plat_data =3D mtk_smmuv3->plat_data; + + return mtk_smmu_pm_put(smmu->dev, plat_data->smmu_type); +} + static const struct arm_smmu_v3_impl mtk_smmu_v3_impl =3D { .combined_irq_handle =3D mtk_smmu_v3_smmuwp_irq_handler, .smmu_evt_handler =3D mtk_smmu_evt_handler, + .smmu_power_get =3D mtk_smmu_power_get, + .smmu_power_put =3D mtk_smmu_power_put, }; =20 struct arm_smmu_device *arm_smmu_v3_impl_mtk_init(struct arm_smmu_device *= smmu) --=20 2.46.0