From nobody Fri Oct 3 07:42:40 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BB44F2BD01E; Wed, 3 Sep 2025 17:19:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756919953; cv=none; b=ZkWaRbmBUvATttf4OwqbOXq+bTcVKojn3SXXsik1xRXrf1G1jTfDCcmGXBPFlC1ID9HbloYKtBCAJMG4WrbjHa5hFpkLLOajMHtiySouYt5k3D+L65C58P8PES8q54LMUNKmeY/sl0gtHkiFtrusH7NCnNrQM4N3zhFIBw8gJ/c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756919953; c=relaxed/simple; bh=1sx3B1KICtDjf4DR2eWZu0vSeJzYHOxzQ4xJumzeAtc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=g9x/ALEYZ+0trPaJbZfGWrjZcCQhsSoDsdKEeAUKGNruk0hH8rF4OfbjDjIOOkLqnnKGiCjp0gWmnmbtlBrPFpx+fgWJgdSYLhATK9UcVvYvyNSUM+hz4Klp3bywiPPH0IHKPkvWqEGmSkcXMkQmPlmb7eki14UeJg9RIsO2FMo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=oCkYGDYu; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="oCkYGDYu" Received: by smtp.kernel.org (Postfix) with ESMTPS id 5C6DFC4CEF0; Wed, 3 Sep 2025 17:19:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1756919953; bh=1sx3B1KICtDjf4DR2eWZu0vSeJzYHOxzQ4xJumzeAtc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=oCkYGDYuNxsGC5YEQIMritYRJh4JK5wfWSJZRnSgH7wdcs3ur3qRIogLrUHpxoGT3 QGibnYcvQOnIi+zc9/y3XQgaAbfKXFPUhureJ0lgPfbS+HzK6ZxMMWUk7y9siIuV4l VAHcCAKJ74ar6t6PK7OTDjD/cBKSwneWLrtynRb135JgoZI8wz3C0NRWOYE4u88Mx+ 1//6XYv09eiHXr9tkQPNgNqncKtr2z/G0F4I+6/8jXn5biEDQR26sJDDXSBs91NoB7 8Qubq6Hs//g/IrLSakGMnokQw258Zagn6cG7ZW+MRCog6TXHIWw4aMVUDt8lbax6qJ Pp1SukXgAimWQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 48A1DCA1009; Wed, 3 Sep 2025 17:19:13 +0000 (UTC) From: Michael Riesch via B4 Relay Date: Wed, 03 Sep 2025 19:04:49 +0200 Subject: [PATCH v4 1/7] dt-bindings: soc: rockchip: add rk3588 csidphy grf syscon Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250616-rk3588-csi-dphy-v4-1-a4f340a7f0cf@collabora.com> References: <20250616-rk3588-csi-dphy-v4-0-a4f340a7f0cf@collabora.com> In-Reply-To: <20250616-rk3588-csi-dphy-v4-0-a4f340a7f0cf@collabora.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Vinod Koul , Kishon Vijay Abraham I , Philipp Zabel , Kever Yang , Jagan Teki , Sebastian Reichel , Diederik de Haas , Neil Armstrong , Heiko Stuebner , Collabora Kernel Team Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, Michael Riesch X-Mailer: b4 0.12.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756919100; l=927; i=michael.riesch@collabora.com; s=20250410; h=from:subject:message-id; bh=+caMXhRTVArPpx+x7pVyqXS9t7uDPpRu8sQdXP1mzpo=; b=wG1IidUa2QHST5Z3WZhLbs1BKkObhL4egG+9FfeF6DpRFd2akprZNyXGUXX5xJtY+UK3vNQ75 aViQTtHPXncDe6KTa09aaDns2yQsvZ3Th0vCUdmYP7FaUKaB96WVPya X-Developer-Key: i=michael.riesch@collabora.com; a=ed25519; pk=+MWX1fffLFZtTPG/I6XdYm/+OSvpRE8D9evQaWbiN04= X-Endpoint-Received: by B4 Relay for michael.riesch@collabora.com/20250410 with auth_id=371 X-Original-From: Michael Riesch Reply-To: michael.riesch@collabora.com From: Michael Riesch Add CSIDPHY GRF syscon compatible for the Rockchip RK3588. Acked-by: Rob Herring (Arm) Signed-off-by: Michael Riesch --- Documentation/devicetree/bindings/soc/rockchip/grf.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Docu= mentation/devicetree/bindings/soc/rockchip/grf.yaml index 1ab0b092e2a5..b6e04e6491e9 100644 --- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml +++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml @@ -47,6 +47,7 @@ properties: - rockchip,rk3576-vop-grf - rockchip,rk3588-bigcore0-grf - rockchip,rk3588-bigcore1-grf + - rockchip,rk3588-csidphy-grf - rockchip,rk3588-dcphy-grf - rockchip,rk3588-hdptxphy-grf - rockchip,rk3588-ioc --=20 2.39.5 From nobody Fri Oct 3 07:42:40 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D50962C0283; Wed, 3 Sep 2025 17:19:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756919953; cv=none; b=eM41AMgItmUtYMKsjDgDrmVR4zV1Wp6PT18E8plEx1+G+3+sN2wsKXLlgUmNcjVsh2bRKaQciLHvM72XIEMBLg70las117fEdb3nXmBGVEQiT+g4HJsVc/V6+qTrC8eQys/+xBppTyyTgOiU57VkmEEoU0OvHscyFEZbT2g6lSU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756919953; c=relaxed/simple; bh=z0cByXcqi0tiIJ45F3UR/xQzVAzSCSQJp8Fkj34rLJQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=WratdTyOnPsqfvXFBtDRrmmwcuVtaeMiHzs2EFcix9gAnbbNnGTrlMeKnSRRVKbP+QrihGx7dWiR776LhvXW3onAJvx707O3Fz1wSDdUlknRbOrwCJJdTfBnZqvE7mO1qAr9a5XTBw7+5u77fgy+dv7wL1bMz3vC3+hTe1N2Vh8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=WaLcUGxL; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="WaLcUGxL" Received: by smtp.kernel.org (Postfix) with ESMTPS id 6F156C4CEF7; Wed, 3 Sep 2025 17:19:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1756919953; bh=z0cByXcqi0tiIJ45F3UR/xQzVAzSCSQJp8Fkj34rLJQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=WaLcUGxLLoqpukdPs8yKExNZqR9boC6D/LASwFlW7+GSd0+IgLZbG0vXzobgc6K4+ I7xQBUp0BBTUhAK1WnV/QvqoMqld/fJEgoJ5bpOQ6OrnLd3nqfo/MfbV1ijGmSG45l Aebi44iR4BoXcqEe2/fbht1Ygv3trD4aBfZtdMB84MCuq3xp5jMDe+rpGxQMODBafC mROkO7ZiJLeRdy4fS4MjzaQZoE299Z9Jup2trBOYMjiZFyYh7BNswPn6BhmXySA7i6 9j8Pj/27ACAWumABap1aPUt526eI9B47ej8wLAo0eA2m3aPai3VcjQD1V3NNjVGKa/ Mu1akCWMM3F0g== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 571D9CA1012; Wed, 3 Sep 2025 17:19:13 +0000 (UTC) From: Michael Riesch via B4 Relay Date: Wed, 03 Sep 2025 19:04:50 +0200 Subject: [PATCH v4 2/7] dt-bindings: phy: rockchip-inno-csi-dphy: make power-domains non-required Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250616-rk3588-csi-dphy-v4-2-a4f340a7f0cf@collabora.com> References: <20250616-rk3588-csi-dphy-v4-0-a4f340a7f0cf@collabora.com> In-Reply-To: <20250616-rk3588-csi-dphy-v4-0-a4f340a7f0cf@collabora.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Vinod Koul , Kishon Vijay Abraham I , Philipp Zabel , Kever Yang , Jagan Teki , Sebastian Reichel , Diederik de Haas , Neil Armstrong , Heiko Stuebner , Collabora Kernel Team Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, Michael Riesch , stable@kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.12.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756919100; l=1518; i=michael.riesch@collabora.com; s=20250410; h=from:subject:message-id; bh=UY9k/CPSgZAnLld//8ZfWwv6Gh22vHYGKGPNRh5Nn0c=; b=eqrvA14lPudPcJ0HuzJerB94/LT2JWN09wGWEW9P+uiosVIJuYhOZHy9+edhlTU7bpXk2ePgV FhRofqJF7+MAB0j+vwm40TiJ+ScMZkN/tlltCZ/LdqOURSsAFJDwJKs X-Developer-Key: i=michael.riesch@collabora.com; a=ed25519; pk=+MWX1fffLFZtTPG/I6XdYm/+OSvpRE8D9evQaWbiN04= X-Endpoint-Received: by B4 Relay for michael.riesch@collabora.com/20250410 with auth_id=371 X-Original-From: Michael Riesch Reply-To: michael.riesch@collabora.com From: Michael Riesch There are variants of the Rockchip Innosilicon CSI DPHY (e.g., the RK3568 variant) that are powered on by default as they are part of the ALIVE power domain. Remove 'power-domains' from the required properties in order to avoid false positives. Fixes: 22c8e0a69b7f ("dt-bindings: phy: add compatible for rk356x to rockch= ip-inno-csi-dphy") Cc: stable@kernel.org Reviewed-by: Krzysztof Kozlowski Signed-off-by: Michael Riesch --- .../devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml | 15 +++++++++++= +++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.y= aml b/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml index 5ac994b3c0aa..b304bc5a08c4 100644 --- a/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml +++ b/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml @@ -57,11 +57,24 @@ required: - clocks - clock-names - '#phy-cells' - - power-domains - resets - reset-names - rockchip,grf =20 +allOf: + - if: + properties: + compatible: + contains: + enum: + - rockchip,px30-csi-dphy + - rockchip,rk1808-csi-dphy + - rockchip,rk3326-csi-dphy + - rockchip,rk3368-csi-dphy + then: + required: + - power-domains + additionalProperties: false =20 examples: --=20 2.39.5 From nobody Fri Oct 3 07:42:40 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D50282C027E; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250616-rk3588-csi-dphy-v4-3-a4f340a7f0cf@collabora.com> References: <20250616-rk3588-csi-dphy-v4-0-a4f340a7f0cf@collabora.com> In-Reply-To: <20250616-rk3588-csi-dphy-v4-0-a4f340a7f0cf@collabora.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Vinod Koul , Kishon Vijay Abraham I , Philipp Zabel , Kever Yang , Jagan Teki , Sebastian Reichel , Diederik de Haas , Neil Armstrong , Heiko Stuebner , Collabora Kernel Team Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, Michael Riesch X-Mailer: b4 0.12.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756919100; l=2731; i=michael.riesch@collabora.com; s=20250410; h=from:subject:message-id; bh=7bigeg1F5lPwfgStFZZ4wKFyLRk3XbHpIpD0M72GMm0=; b=LokOxU4EfIW0fGm4vKWQMR5FmC0PeGxu6+KsKQv2ROgNpcw1hbk8D+oy49nGl5PnLAz3/co7E Og8j+IhAP9wDMHvR1s0BysO7/GM+jaqAna8v3Mq7yibY4/J3iMRybe2 X-Developer-Key: i=michael.riesch@collabora.com; a=ed25519; pk=+MWX1fffLFZtTPG/I6XdYm/+OSvpRE8D9evQaWbiN04= X-Endpoint-Received: by B4 Relay for michael.riesch@collabora.com/20250410 with auth_id=371 X-Original-From: Michael Riesch Reply-To: michael.riesch@collabora.com From: Michael Riesch The Rockchip RK3588 variant of the CSI-2 DPHY features two reset lines. Add the variant and allow for the additional reset. While at it, fix the description of the first reset in order to avoid confusion. Signed-off-by: Michael Riesch Reviewed-by: Krzysztof Kozlowski --- .../bindings/phy/rockchip-inno-csi-dphy.yaml | 50 ++++++++++++++++++= +++- 1 file changed, 49 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.y= aml b/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml index b304bc5a08c4..03950b3cad08 100644 --- a/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml +++ b/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml @@ -21,6 +21,7 @@ properties: - rockchip,rk3326-csi-dphy - rockchip,rk3368-csi-dphy - rockchip,rk3568-csi-dphy + - rockchip,rk3588-csi-dphy =20 reg: maxItems: 1 @@ -40,11 +41,15 @@ properties: =20 resets: items: - - description: exclusive PHY reset line + - description: APB reset line + - description: PHY reset line + minItems: 1 =20 reset-names: items: - const: apb + - const: phy + minItems: 1 =20 rockchip,grf: $ref: /schemas/types.yaml#/definitions/phandle @@ -74,6 +79,30 @@ allOf: then: required: - power-domains + - if: + properties: + compatible: + contains: + enum: + - rockchip,px30-csi-dphy + - rockchip,rk1808-csi-dphy + - rockchip,rk3326-csi-dphy + - rockchip,rk3368-csi-dphy + - rockchip,rk3568-csi-dphy + then: + properties: + resets: + maxItems: 1 + + reset-names: + maxItems: 1 + else: + properties: + resets: + minItems: 2 + + reset-names: + minItems: 2 =20 additionalProperties: false =20 @@ -91,3 +120,22 @@ examples: reset-names =3D "apb"; rockchip,grf =3D <&grf>; }; + - | + #include + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + phy@fedc0000 { + compatible =3D "rockchip,rk3588-csi-dphy"; + reg =3D <0x0 0xfedc0000 0x0 0x8000>; + clocks =3D <&cru PCLK_CSIPHY0>; + clock-names =3D "pclk"; + #phy-cells =3D <0>; + resets =3D <&cru SRST_P_CSIPHY0>, <&cru SRST_CSIPHY0>; + reset-names =3D "apb", "phy"; + rockchip,grf =3D <&csidphy0_grf>; + }; + }; --=20 2.39.5 From nobody Fri Oct 3 07:42:40 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D4F9A2BE7B8; Wed, 3 Sep 2025 17:19:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756919953; cv=none; b=N8HhCLskK8KTmDdy2NjU1QueoixNZ9IXvAw+bYEYYIVsqPKPr4JZUkigDs1r7YPAtiNqm3lC0IY7tZzKg6jz2mZ6bVkYikiM54IYMnAd+QikWvXHRZZc7QsILrWbLb9HtmgLwKa/NtC/EYk20AQHacKgmO/NbwqYldPqL+UHoN0= ARC-Message-Signature: i=1; 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b=dn3tsSzudAg8L9PZhg+TO90PaiBGUQS5eUz9TInxk5VqlsByoUQ0c1osaxAV5PUjQ ar82Y/xLUBrhx9yDV0sY98jDmw5aJIZIubklqmEmPP7NT9f8n+Zs0RwZwaH9iFWqod prNbCOckRkOXqogYQhDcYBMU6Es0S7R1WtlDRi9ardpQtbL0SmTGTiCSYXgWk+Zwc8 xhIaC4LXNiYLLZ4c7PvZonkTOxvsmHB/hWwXyzXAfDe+YlLFzUE13Uio9v1V2MRj2f u7wiPaCkrdVq69fbohbAgab9yjx2GsZeqIakbLV4qSZqaGPRBTRegbOyhe6VQsvWZt CocBk/2oZ7KJg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 74EAFCA1016; Wed, 3 Sep 2025 17:19:13 +0000 (UTC) From: Michael Riesch via B4 Relay Date: Wed, 03 Sep 2025 19:04:52 +0200 Subject: [PATCH v4 4/7] phy: rockchip: phy-rockchip-inno-csidphy: allow writes to grf register 0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250616-rk3588-csi-dphy-v4-4-a4f340a7f0cf@collabora.com> References: <20250616-rk3588-csi-dphy-v4-0-a4f340a7f0cf@collabora.com> In-Reply-To: <20250616-rk3588-csi-dphy-v4-0-a4f340a7f0cf@collabora.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Vinod Koul , Kishon Vijay Abraham I , Philipp Zabel , Kever Yang , Jagan Teki , Sebastian Reichel , Diederik de Haas , Neil Armstrong , Heiko Stuebner , Collabora Kernel Team Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, Michael Riesch X-Mailer: b4 0.12.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756919100; l=1635; i=michael.riesch@collabora.com; s=20250410; h=from:subject:message-id; bh=l+DL7hvrQb52Alb7OjVyKnZ7Z6pkTmglNXwtSvoPg4M=; b=hux9Hi/hrFdC+fr/TFtPwShVrl0HCnByOxlQmOFhR4GbeK1nmM67xDBCiv0RTujZoeN/yY3bL Su+l7pFF4SIC+u5Lf28nxI84VUoBS06Vnc0Sp/h6XmIdEIgtQb4/2rK X-Developer-Key: i=michael.riesch@collabora.com; a=ed25519; pk=+MWX1fffLFZtTPG/I6XdYm/+OSvpRE8D9evQaWbiN04= X-Endpoint-Received: by B4 Relay for michael.riesch@collabora.com/20250410 with auth_id=371 X-Original-From: Michael Riesch Reply-To: michael.riesch@collabora.com From: Michael Riesch The driver for the Rockchip MIPI CSI-2 DPHY uses GRF register offset value 0 to sort out undefined registers. However, the RK3588 CSIDPHY GRF this offset is perfectly fine (in fact, register 0 is the only one in this register file). Introduce a boolean variable to indicate valid registers and allow writes to register 0. Reviewed-by: Neil Armstrong Signed-off-by: Michael Riesch --- drivers/phy/rockchip/phy-rockchip-inno-csidphy.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-inno-csidphy.c b/drivers/phy= /rockchip/phy-rockchip-inno-csidphy.c index 2ab99e1d47eb..75533d071025 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-csidphy.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-csidphy.c @@ -87,10 +87,11 @@ struct dphy_reg { u32 offset; u32 mask; u32 shift; + u8 valid; }; =20 #define PHY_REG(_offset, _width, _shift) \ - { .offset =3D _offset, .mask =3D BIT(_width) - 1, .shift =3D _shift, } + { .offset =3D _offset, .mask =3D BIT(_width) - 1, .shift =3D _shift, .val= id =3D 1, } =20 static const struct dphy_reg rk1808_grf_dphy_regs[] =3D { [GRF_DPHY_CSIPHY_FORCERXMODE] =3D PHY_REG(RK1808_GRF_PD_VI_CON_OFFSET, 4,= 0), @@ -145,7 +146,7 @@ static inline void write_grf_reg(struct rockchip_inno_c= sidphy *priv, const struct dphy_drv_data *drv_data =3D priv->drv_data; const struct dphy_reg *reg =3D &drv_data->grf_regs[index]; =20 - if (reg->offset) + if (reg->valid) regmap_write(priv->grf, reg->offset, HIWORD_UPDATE(value, reg->mask, reg->shift)); } --=20 2.39.5 From nobody Fri Oct 3 07:42:40 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 14A4E3126BF; Wed, 3 Sep 2025 17:19:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756919954; cv=none; b=YAqxvQ+BQFggwSUaPjtAZKB6sK1uuZsyRYUDyQ2Hn4eE0ir2hqUgN9m/y/JO0UIvLVIrlSntz5irNlbxiyFoeNRNMX/fxlDF6F6fjH3bK+7Ui3F+PZp5Xt17rVp9oRutq9hM8FJndC9t/D+D2LXVtw+1ouzKzBQ7c4fXDZmSzYE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756919954; c=relaxed/simple; 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Wed, 3 Sep 2025 17:19:13 +0000 (UTC) From: Michael Riesch via B4 Relay Date: Wed, 03 Sep 2025 19:04:53 +0200 Subject: [PATCH v4 5/7] phy: rockchip: phy-rockchip-inno-csidphy: allow for different reset lines Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250616-rk3588-csi-dphy-v4-5-a4f340a7f0cf@collabora.com> References: <20250616-rk3588-csi-dphy-v4-0-a4f340a7f0cf@collabora.com> In-Reply-To: <20250616-rk3588-csi-dphy-v4-0-a4f340a7f0cf@collabora.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Vinod Koul , Kishon Vijay Abraham I , Philipp Zabel , Kever Yang , Jagan Teki , Sebastian Reichel , Diederik de Haas , Neil Armstrong , Heiko Stuebner , Collabora Kernel Team Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, Michael Riesch X-Mailer: b4 0.12.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756919100; l=4524; i=michael.riesch@collabora.com; s=20250410; h=from:subject:message-id; bh=ouqlgbnwWSp9gE4kXLQdfgX4LelZawR0mUFaykrHL9U=; b=NRuarniyeddlvm8uHBr/1dfXaIebfkSTrMveSDbVes8hWlBDX9Cbj175m1OMiyAeFmHJLVISe gdtoUNWEX9MCU3fSObSPlZTSV4ciMzlw0cxfSAxYdndDufzBOAc8OYH X-Developer-Key: i=michael.riesch@collabora.com; a=ed25519; pk=+MWX1fffLFZtTPG/I6XdYm/+OSvpRE8D9evQaWbiN04= X-Endpoint-Received: by B4 Relay for michael.riesch@collabora.com/20250410 with auth_id=371 X-Original-From: Michael Riesch Reply-To: michael.riesch@collabora.com From: Michael Riesch The RK3588 MIPI CSI-2 DPHY variant requires two reset lines. Add support for different sets of reset lines to the phy-rockchip-inno-csidphy driver as preparation for the introduction of the RK3588 variant. Signed-off-by: Michael Riesch --- drivers/phy/rockchip/phy-rockchip-inno-csidphy.c | 34 ++++++++++++++++++++= +--- 1 file changed, 30 insertions(+), 4 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-inno-csidphy.c b/drivers/phy= /rockchip/phy-rockchip-inno-csidphy.c index 75533d071025..6c4ddcd7e5de 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-csidphy.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-csidphy.c @@ -67,6 +67,8 @@ #define RK1808_CSIDPHY_CLK_CALIB_EN 0x168 #define RK3568_CSIDPHY_CLK_CALIB_EN 0x168 =20 +#define RESETS_MAX 2 + /* * The higher 16-bit of this register is used for write protection * only if BIT(x + 16) set to 1 the BIT(x) can be written. @@ -127,6 +129,8 @@ struct dphy_drv_data { const struct hsfreq_range *hsfreq_ranges; int num_hsfreq_ranges; const struct dphy_reg *grf_regs; + const char *const *resets; + unsigned int resets_num; }; =20 struct rockchip_inno_csidphy { @@ -134,7 +138,8 @@ struct rockchip_inno_csidphy { void __iomem *phy_base; struct clk *pclk; struct regmap *grf; - struct reset_control *rst; + struct reset_control_bulk_data resets[RESETS_MAX]; + unsigned int resets_num; const struct dphy_drv_data *drv_data; struct phy_configure_opts_mipi_dphy config; u8 hsfreq; @@ -174,6 +179,10 @@ static const struct hsfreq_range rk3368_mipidphy_hsfre= q_ranges[] =3D { {1249, 0x0c}, {1349, 0x0d}, {1500, 0x0e} }; =20 +static const char *const rk3368_reset_names[] =3D { + "apb" +}; + static void rockchip_inno_csidphy_ths_settle(struct rockchip_inno_csidphy = *priv, int hsfreq, int offset) { @@ -344,6 +353,8 @@ static const struct dphy_drv_data rk1808_mipidphy_drv_d= ata =3D { .hsfreq_ranges =3D rk1808_mipidphy_hsfreq_ranges, .num_hsfreq_ranges =3D ARRAY_SIZE(rk1808_mipidphy_hsfreq_ranges), .grf_regs =3D rk1808_grf_dphy_regs, + .resets =3D rk3368_reset_names, + .resets_num =3D ARRAY_SIZE(rk3368_reset_names), }; =20 static const struct dphy_drv_data rk3326_mipidphy_drv_data =3D { @@ -353,6 +364,8 @@ static const struct dphy_drv_data rk3326_mipidphy_drv_d= ata =3D { .hsfreq_ranges =3D rk3326_mipidphy_hsfreq_ranges, .num_hsfreq_ranges =3D ARRAY_SIZE(rk3326_mipidphy_hsfreq_ranges), .grf_regs =3D rk3326_grf_dphy_regs, + .resets =3D rk3368_reset_names, + .resets_num =3D ARRAY_SIZE(rk3368_reset_names), }; =20 static const struct dphy_drv_data rk3368_mipidphy_drv_data =3D { @@ -362,6 +375,8 @@ static const struct dphy_drv_data rk3368_mipidphy_drv_d= ata =3D { .hsfreq_ranges =3D rk3368_mipidphy_hsfreq_ranges, .num_hsfreq_ranges =3D ARRAY_SIZE(rk3368_mipidphy_hsfreq_ranges), .grf_regs =3D rk3368_grf_dphy_regs, + .resets =3D rk3368_reset_names, + .resets_num =3D ARRAY_SIZE(rk3368_reset_names), }; =20 static const struct dphy_drv_data rk3568_mipidphy_drv_data =3D { @@ -371,6 +386,8 @@ static const struct dphy_drv_data rk3568_mipidphy_drv_d= ata =3D { .hsfreq_ranges =3D rk1808_mipidphy_hsfreq_ranges, .num_hsfreq_ranges =3D ARRAY_SIZE(rk1808_mipidphy_hsfreq_ranges), .grf_regs =3D rk3568_grf_dphy_regs, + .resets =3D rk3368_reset_names, + .resets_num =3D ARRAY_SIZE(rk3368_reset_names), }; =20 static const struct of_device_id rockchip_inno_csidphy_match_id[] =3D { @@ -404,6 +421,7 @@ static int rockchip_inno_csidphy_probe(struct platform_= device *pdev) struct device *dev =3D &pdev->dev; struct phy_provider *phy_provider; struct phy *phy; + int ret; =20 priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); if (!priv) @@ -435,10 +453,18 @@ static int rockchip_inno_csidphy_probe(struct platfor= m_device *pdev) return PTR_ERR(priv->pclk); } =20 - priv->rst =3D devm_reset_control_get(dev, "apb"); - if (IS_ERR(priv->rst)) { + if (priv->drv_data->resets_num > RESETS_MAX) { + dev_err(dev, "invalid number of resets\n"); + return -EINVAL; + } + priv->resets_num =3D priv->drv_data->resets_num; + for (unsigned int i =3D 0; i < priv->resets_num; i++) + priv->resets[i].id =3D priv->drv_data->resets[i]; + ret =3D devm_reset_control_bulk_get_exclusive(dev, priv->resets_num, + priv->resets); + if (ret) { dev_err(dev, "failed to get system reset control\n"); - return PTR_ERR(priv->rst); + return ret; } =20 phy =3D devm_phy_create(dev, NULL, &rockchip_inno_csidphy_ops); --=20 2.39.5 From nobody Fri Oct 3 07:42:40 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 16F25313E1D; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250616-rk3588-csi-dphy-v4-6-a4f340a7f0cf@collabora.com> References: <20250616-rk3588-csi-dphy-v4-0-a4f340a7f0cf@collabora.com> In-Reply-To: <20250616-rk3588-csi-dphy-v4-0-a4f340a7f0cf@collabora.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Vinod Koul , Kishon Vijay Abraham I , Philipp Zabel , Kever Yang , Jagan Teki , Sebastian Reichel , Diederik de Haas , Neil Armstrong , Heiko Stuebner , Collabora Kernel Team Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, Michael Riesch X-Mailer: b4 0.12.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756919100; l=2783; i=michael.riesch@collabora.com; s=20250410; h=from:subject:message-id; bh=yeQXRqZNa57y0uWiIJSkXVpQ6zTLhd7z989yNwE9ju8=; b=09kf8MWdVIJYt17xvFCMxwQMzZX4u4Brgl+1iUwO4QTsnjcHQsNMRCpKITxjEFx6OTIW6WZC7 UIWb9h766jYBnPxX3zwxp41iqewKxuENTlmphSwD+LVqfdfDCL3HtRr X-Developer-Key: i=michael.riesch@collabora.com; a=ed25519; pk=+MWX1fffLFZtTPG/I6XdYm/+OSvpRE8D9evQaWbiN04= X-Endpoint-Received: by B4 Relay for michael.riesch@collabora.com/20250410 with auth_id=371 X-Original-From: Michael Riesch Reply-To: michael.riesch@collabora.com From: Michael Riesch The Rockchip RK3588 MIPI CSI-2 DPHY can be supported using the existing phy-rockchip-inno-csidphy driver, the notable differences being - the control bits in the GRF - the additional reset line Add support for this variant. Signed-off-by: Michael Riesch --- drivers/phy/rockchip/phy-rockchip-inno-csidphy.c | 28 ++++++++++++++++++++= ++++ 1 file changed, 28 insertions(+) diff --git a/drivers/phy/rockchip/phy-rockchip-inno-csidphy.c b/drivers/phy= /rockchip/phy-rockchip-inno-csidphy.c index 6c4ddcd7e5de..c79fb53d8ee5 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-csidphy.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-csidphy.c @@ -30,6 +30,8 @@ #define RK3568_GRF_VI_CON0 0x0340 #define RK3568_GRF_VI_CON1 0x0344 =20 +#define RK3588_CSIDPHY_GRF_CON0 0x0000 + /* PHY */ #define CSIDPHY_CTRL_LANE_ENABLE 0x00 #define CSIDPHY_CTRL_LANE_ENABLE_CK BIT(6) @@ -117,6 +119,12 @@ static const struct dphy_reg rk3568_grf_dphy_regs[] = =3D { [GRF_DPHY_CSIPHY_CLKLANE_EN] =3D PHY_REG(RK3568_GRF_VI_CON0, 1, 8), }; =20 +static const struct dphy_reg rk3588_grf_dphy_regs[] =3D { + [GRF_DPHY_CSIPHY_FORCERXMODE] =3D PHY_REG(RK3588_CSIDPHY_GRF_CON0, 4, 0), + [GRF_DPHY_CSIPHY_DATALANE_EN] =3D PHY_REG(RK3588_CSIDPHY_GRF_CON0, 4, 4), + [GRF_DPHY_CSIPHY_CLKLANE_EN] =3D PHY_REG(RK3588_CSIDPHY_GRF_CON0, 1, 8), +}; + struct hsfreq_range { u32 range_h; u8 cfg_bit; @@ -183,6 +191,11 @@ static const char *const rk3368_reset_names[] =3D { "apb" }; =20 +static const char *const rk3588_reset_names[] =3D { + "apb", + "phy" +}; + static void rockchip_inno_csidphy_ths_settle(struct rockchip_inno_csidphy = *priv, int hsfreq, int offset) { @@ -390,6 +403,17 @@ static const struct dphy_drv_data rk3568_mipidphy_drv_= data =3D { .resets_num =3D ARRAY_SIZE(rk3368_reset_names), }; =20 +static const struct dphy_drv_data rk3588_mipidphy_drv_data =3D { + .pwrctl_offset =3D -1, + .ths_settle_offset =3D RK3568_CSIDPHY_CLK_WR_THS_SETTLE, + .calib_offset =3D RK3568_CSIDPHY_CLK_CALIB_EN, + .hsfreq_ranges =3D rk1808_mipidphy_hsfreq_ranges, + .num_hsfreq_ranges =3D ARRAY_SIZE(rk1808_mipidphy_hsfreq_ranges), + .grf_regs =3D rk3588_grf_dphy_regs, + .resets =3D rk3588_reset_names, + .resets_num =3D ARRAY_SIZE(rk3588_reset_names), +}; + static const struct of_device_id rockchip_inno_csidphy_match_id[] =3D { { .compatible =3D "rockchip,px30-csi-dphy", @@ -411,6 +435,10 @@ static const struct of_device_id rockchip_inno_csidphy= _match_id[] =3D { .compatible =3D "rockchip,rk3568-csi-dphy", .data =3D &rk3568_mipidphy_drv_data, }, + { + .compatible =3D "rockchip,rk3588-csi-dphy", + .data =3D &rk3588_mipidphy_drv_data, + }, {} }; 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Wed, 3 Sep 2025 17:19:13 +0000 (UTC) From: Michael Riesch via B4 Relay Date: Wed, 03 Sep 2025 19:04:55 +0200 Subject: [PATCH v4 7/7] arm64: dts: rockchip: add mipi csi-2 dphy nodes to rk3588 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250616-rk3588-csi-dphy-v4-7-a4f340a7f0cf@collabora.com> References: <20250616-rk3588-csi-dphy-v4-0-a4f340a7f0cf@collabora.com> In-Reply-To: <20250616-rk3588-csi-dphy-v4-0-a4f340a7f0cf@collabora.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Vinod Koul , Kishon Vijay Abraham I , Philipp Zabel , Kever Yang , Jagan Teki , Sebastian Reichel , Diederik de Haas , Neil Armstrong , Heiko Stuebner , Collabora Kernel Team Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, Michael Riesch X-Mailer: b4 0.12.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756919100; l=1971; i=michael.riesch@collabora.com; s=20250410; h=from:subject:message-id; bh=EOeNg7P2XmUPLOzLBrcxGPzX6tkgiFkIQtNnjJusr/w=; b=Tmen4hPVQ8EHstuJqdsTDkixieFXQyEUDYNYXsTEOdpGe3owz93Y94SPBObYOtj3lz5pZzdyz CzI7aEQr8tRA+RdzaY+Qv2gxoD0LCowf7kQjFilyAkgjgwTOh/YamsN X-Developer-Key: i=michael.riesch@collabora.com; a=ed25519; pk=+MWX1fffLFZtTPG/I6XdYm/+OSvpRE8D9evQaWbiN04= X-Endpoint-Received: by B4 Relay for michael.riesch@collabora.com/20250410 with auth_id=371 X-Original-From: Michael Riesch Reply-To: michael.riesch@collabora.com From: Michael Riesch The Rockchip RK3588 features two MIPI CSI-2 DPHYs. Add the device tree nodes for them. Signed-off-by: Michael Riesch --- arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 34 +++++++++++++++++++++++= ++++ 1 file changed, 34 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boo= t/dts/rockchip/rk3588-base.dtsi index 70f03e68ba55..72a0022d1b74 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -621,6 +621,16 @@ php_grf: syscon@fd5b0000 { reg =3D <0x0 0xfd5b0000 0x0 0x1000>; }; =20 + csidphy0_grf: syscon@fd5b4000 { + compatible =3D "rockchip,rk3588-csidphy-grf", "syscon"; + reg =3D <0x0 0xfd5b4000 0x0 0x1000>; + }; + + csidphy1_grf: syscon@fd5b5000 { + compatible =3D "rockchip,rk3588-csidphy-grf", "syscon"; + reg =3D <0x0 0xfd5b5000 0x0 0x1000>; + }; + pipe_phy0_grf: syscon@fd5bc000 { compatible =3D "rockchip,rk3588-pipe-phy-grf", "syscon"; reg =3D <0x0 0xfd5bc000 0x0 0x100>; @@ -3055,6 +3065,30 @@ mipidcphy1: phy@fedb0000 { status =3D "disabled"; }; =20 + csi_dphy0: phy@fedc0000 { + compatible =3D "rockchip,rk3588-csi-dphy"; + reg =3D <0x0 0xfedc0000 0x0 0x8000>; + clocks =3D <&cru PCLK_CSIPHY0>; + clock-names =3D "pclk"; + #phy-cells =3D <0>; + resets =3D <&cru SRST_P_CSIPHY0>, <&cru SRST_CSIPHY0>; + reset-names =3D "apb", "phy"; + rockchip,grf =3D <&csidphy0_grf>; + status =3D "disabled"; + }; + + csi_dphy1: phy@fedc8000 { + compatible =3D "rockchip,rk3588-csi-dphy"; + reg =3D <0x0 0xfedc8000 0x0 0x8000>; + clocks =3D <&cru PCLK_CSIPHY1>; + clock-names =3D "pclk"; + #phy-cells =3D <0>; + resets =3D <&cru SRST_P_CSIPHY1>, <&cru SRST_CSIPHY1>; + reset-names =3D "apb", "phy"; + rockchip,grf =3D <&csidphy1_grf>; + status =3D "disabled"; + }; + combphy0_ps: phy@fee00000 { compatible =3D "rockchip,rk3588-naneng-combphy"; reg =3D <0x0 0xfee00000 0x0 0x100>; --=20 2.39.5