From nobody Fri Oct 3 11:26:44 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2E88223E355; Mon, 1 Sep 2025 21:01:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756760513; cv=none; b=WsOV9isXMuE0UHFEknQCnKPZUzhaZlHVFoWBWuqegVibtKS/wo7D0dQ91vwZMFWLFeKv61ffcvnJ5phaNU2ww8xAFbaUmQcDLHXlb+mysZ9N9kC9UVXIvR+Mxcvyp1wEoxsB22NFHDP7u3ymNeNn303ry7yC+cj2BwL2dxwlAxo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756760513; c=relaxed/simple; bh=1sx3B1KICtDjf4DR2eWZu0vSeJzYHOxzQ4xJumzeAtc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=K6js5t325QPXvoaeHroqQzjb7ktqvrebFoZIbRrEV8fSQRWfnfkM81qrKc4KZgg5Zu81KDwtRjsNgUioQY0k3KSvWW+rpaj3IIVUSejzZn1sGNEJGrRU3lZs8ckVetMI+Z9zXRRsQ592F4thPaz/vciN/TPXGszVxGNY0PrbmSQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=XkoWhKMj; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="XkoWhKMj" Received: by smtp.kernel.org (Postfix) with ESMTPS id A7BB4C4CEF7; Mon, 1 Sep 2025 21:01:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1756760512; bh=1sx3B1KICtDjf4DR2eWZu0vSeJzYHOxzQ4xJumzeAtc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=XkoWhKMjQB6gbvpKIp/AOEGBepJ0nRjMBF3GTFxzyUOGfcIFueD+Cc9AFgAsMhDeO 0emRqz1xu2gN8aoMwgRDCKJGmI4nJgTCAoCnjH/K7fJ9TkRYOkSDawEaw2iFVu8ax6 o04mXEEjcnW44L/02dN/pn8sWZdGD4puIFf3a0P0vIHyRghAyWztzMPHFsOGNEV3sD GHSJ2aF/+Vgwb8+7Suxz2QP9teYQpz7ckdr3DDXD6XSnNUlbKUCNQdb3zpN6QkXQGB cBuo5S/m79+QASQ+XTKHkgnMr53URgN6v5K2VtyNkrFnlLyvtuJPfujwM3tj2D5m9U HdgxhX9ek0Ipw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8F57ACA1005; Mon, 1 Sep 2025 21:01:52 +0000 (UTC) From: Michael Riesch via B4 Relay Date: Mon, 01 Sep 2025 22:47:42 +0200 Subject: [PATCH v3 1/7] dt-bindings: soc: rockchip: add rk3588 csidphy grf syscon Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250616-rk3588-csi-dphy-v3-1-a5ccd5f1f438@collabora.com> References: <20250616-rk3588-csi-dphy-v3-0-a5ccd5f1f438@collabora.com> In-Reply-To: <20250616-rk3588-csi-dphy-v3-0-a5ccd5f1f438@collabora.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Vinod Koul , Kishon Vijay Abraham I , Philipp Zabel , Kever Yang , Jagan Teki , Sebastian Reichel , Diederik de Haas , Neil Armstrong , Heiko Stuebner , Collabora Kernel Team Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, Michael Riesch X-Mailer: b4 0.12.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756759662; l=927; i=michael.riesch@collabora.com; s=20250410; h=from:subject:message-id; bh=+caMXhRTVArPpx+x7pVyqXS9t7uDPpRu8sQdXP1mzpo=; b=GhQI9Eco07YwwzPj4YTacxR9ShNGnxBwmititeHbHW1kIAEG2Bw+zEuUCgD/mYM9Ly6AOr296 l4E1Rg7ApYBDnXLv/WBlnyGdN7ZTjKeScLWhpLvyf0aUIDe7NY2fqHA X-Developer-Key: i=michael.riesch@collabora.com; a=ed25519; pk=+MWX1fffLFZtTPG/I6XdYm/+OSvpRE8D9evQaWbiN04= X-Endpoint-Received: by B4 Relay for michael.riesch@collabora.com/20250410 with auth_id=371 X-Original-From: Michael Riesch Reply-To: michael.riesch@collabora.com From: Michael Riesch Add CSIDPHY GRF syscon compatible for the Rockchip RK3588. Acked-by: Rob Herring (Arm) Signed-off-by: Michael Riesch --- Documentation/devicetree/bindings/soc/rockchip/grf.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Docu= mentation/devicetree/bindings/soc/rockchip/grf.yaml index 1ab0b092e2a5..b6e04e6491e9 100644 --- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml +++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml @@ -47,6 +47,7 @@ properties: - rockchip,rk3576-vop-grf - rockchip,rk3588-bigcore0-grf - rockchip,rk3588-bigcore1-grf + - rockchip,rk3588-csidphy-grf - rockchip,rk3588-dcphy-grf - rockchip,rk3588-hdptxphy-grf - rockchip,rk3588-ioc --=20 2.39.5 From nobody Fri Oct 3 11:26:44 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EC64D1DEFDD; Mon, 1 Sep 2025 21:01:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756760513; cv=none; b=KDh5sTy6eCLSZsNpb5I2WgoEMF1SdBOIgtxgWJthfzycUhVQ/2cGHo0t+9NNGjVxaVywhPAhrAt/sC39bCf/iVymrhdNyOIKmjRtsJESXc9VE1g0XxG8uzaVyONYA6uMh2AatyolFJ2ecVKgfMkLUgRdu0Fc7GauIChgoQPLpO8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756760513; c=relaxed/simple; bh=vBYv6MXUwCuhAbpabDwzBwOgMyTdiJM8q4aGv6VxvME=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=K8yByQGxN42mTXfm/dWxYvCwxCTpyHt5bIeaLzMy9SEykspmL/J2S5FMvWe4euM0JzeKkCfUNVz1SHWeHwZ42I4CxWelMTWkBzvSNfBOLn8D6ZH/HKNHF+OSft3GQLuagolsb7+C6jY7Q0fZ7azoUZyrsCIHPehAwmQ/G5Cyi5o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=aPdsJbkR; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="aPdsJbkR" Received: by smtp.kernel.org (Postfix) with ESMTPS id B3C6AC4CEF8; Mon, 1 Sep 2025 21:01:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1756760512; bh=vBYv6MXUwCuhAbpabDwzBwOgMyTdiJM8q4aGv6VxvME=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=aPdsJbkRjCQLOpTsKDW49YistbX/BPcUZoZ34Ki7srfAsN/FKLgFZ29duWyTr1F0H D5cwHWqPgq+u7gCmVOqyJc+jb55xtC3/H1B4Gc1sZhVH21FbotV9N03WCcFpt1yeKk ZgzKisZR+qSsl+wk7tkVcejOSOnC0NKUNoobCmJOTMO8Mnz8aiPqV3OhK4v3oMPxHc ynN4UVHMoMsaVKP6KdSZvqPXlRly6uwDVTL6oxJJ3r+5O7TUtnanI5K+TR7kscX2Y7 Bp3axnfp8niaXYhVKdj3b/KiqxKJWarke0e7Q7lD+2ZkobtdGi6ac3XeshlNu6iYJQ zYUQa5DV6Xpqg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id A0D47CA100A; Mon, 1 Sep 2025 21:01:52 +0000 (UTC) From: Michael Riesch via B4 Relay Date: Mon, 01 Sep 2025 22:47:43 +0200 Subject: [PATCH v3 2/7] dt-bindings: phy: rockchip-inno-csi-dphy: make power-domains non-required Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250616-rk3588-csi-dphy-v3-2-a5ccd5f1f438@collabora.com> References: <20250616-rk3588-csi-dphy-v3-0-a5ccd5f1f438@collabora.com> In-Reply-To: <20250616-rk3588-csi-dphy-v3-0-a5ccd5f1f438@collabora.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Vinod Koul , Kishon Vijay Abraham I , Philipp Zabel , Kever Yang , Jagan Teki , Sebastian Reichel , Diederik de Haas , Neil Armstrong , Heiko Stuebner , Collabora Kernel Team Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, Michael Riesch , stable@kernel.org X-Mailer: b4 0.12.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756759662; l=1532; i=michael.riesch@collabora.com; s=20250410; h=from:subject:message-id; bh=GUfdT8g95f8R9qP58as/tdyx1X3jOtQiZxdNeML59g4=; b=DuKH0e/OtkdKKwqW8M1VcwKl51XChDQIf7z5nZn4GekS4KRFKM7SBl7RIlzRLjARVw+cyOq7K X77ZmFyW07WAXDc8vQbjEz4rupfXT9JoXWqtm7LZ3beawyE8IACb5Do X-Developer-Key: i=michael.riesch@collabora.com; a=ed25519; pk=+MWX1fffLFZtTPG/I6XdYm/+OSvpRE8D9evQaWbiN04= X-Endpoint-Received: by B4 Relay for michael.riesch@collabora.com/20250410 with auth_id=371 X-Original-From: Michael Riesch Reply-To: michael.riesch@collabora.com From: Michael Riesch There are variants of the Rockchip Innosilicon CSI DPHY (e.g., the RK3568 variant) that are powered on by default as they are part of the ALIVE power domain. Remove 'power-domains' from the required properties in order to avoid false negatives. Fixes: 22c8e0a69b7f ("dt-bindings: phy: add compatible for rk356x to rockch= ip-inno-csi-dphy") Cc: stable@kernel.org Signed-off-by: Michael Riesch Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml | 15 +++++++++++= +++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.y= aml b/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml index 5ac994b3c0aa..9ad72518e6da 100644 --- a/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml +++ b/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml @@ -51,13 +51,26 @@ properties: description: Some additional phy settings are access through GRF regs. =20 +allOf: + - if: + properties: + compatible: + contains: + enum: + - rockchip,px30-csi-dphy + - rockchip,rk1808-csi-dphy + - rockchip,rk3326-csi-dphy + - rockchip,rk3368-csi-dphy + then: + required: + - power-domains + required: - compatible - reg - clocks - clock-names - '#phy-cells' - - power-domains - resets - reset-names - rockchip,grf --=20 2.39.5 From nobody Fri Oct 3 11:26:44 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 37340244694; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250616-rk3588-csi-dphy-v3-3-a5ccd5f1f438@collabora.com> References: <20250616-rk3588-csi-dphy-v3-0-a5ccd5f1f438@collabora.com> In-Reply-To: <20250616-rk3588-csi-dphy-v3-0-a5ccd5f1f438@collabora.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Vinod Koul , Kishon Vijay Abraham I , Philipp Zabel , Kever Yang , Jagan Teki , Sebastian Reichel , Diederik de Haas , Neil Armstrong , Heiko Stuebner , Collabora Kernel Team Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, Michael Riesch X-Mailer: b4 0.12.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756759662; l=2642; i=michael.riesch@collabora.com; s=20250410; h=from:subject:message-id; bh=BWFwRKFAbzrCTHgoNhrC2467CbLUxPGoZVsDuHv4H7c=; b=0czArA1ITOmxFWBtw11FrbEGI1xv6KFhDnksdNLZ753DqIkLziGJrhhdwnO+Pi5szSnee6/M1 U6abVJH6hw+BdIljo8oHXnmvoHr6GhbsF3cF9KaV9J4tiTp23SdwzHc X-Developer-Key: i=michael.riesch@collabora.com; a=ed25519; pk=+MWX1fffLFZtTPG/I6XdYm/+OSvpRE8D9evQaWbiN04= X-Endpoint-Received: by B4 Relay for michael.riesch@collabora.com/20250410 with auth_id=371 X-Original-From: Michael Riesch Reply-To: michael.riesch@collabora.com From: Michael Riesch The Rockchip RK3588 variant of the CSI-2 DPHY features two reset lines. Add the variant and allow for the additional reset. Signed-off-by: Michael Riesch --- .../bindings/phy/rockchip-inno-csi-dphy.yaml | 50 ++++++++++++++++++= +++- 1 file changed, 49 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.y= aml b/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml index 9ad72518e6da..e37c9fd74788 100644 --- a/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml +++ b/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml @@ -21,6 +21,7 @@ properties: - rockchip,rk3326-csi-dphy - rockchip,rk3368-csi-dphy - rockchip,rk3568-csi-dphy + - rockchip,rk3588-csi-dphy =20 reg: maxItems: 1 @@ -40,11 +41,15 @@ properties: =20 resets: items: - - description: exclusive PHY reset line + - description: APB reset line + - description: PHY reset line + minItems: 1 =20 reset-names: items: - const: apb + - const: phy + minItems: 1 =20 rockchip,grf: $ref: /schemas/types.yaml#/definitions/phandle @@ -64,6 +69,30 @@ allOf: then: required: - power-domains + - if: + properties: + compatible: + contains: + enum: + - rockchip,px30-csi-dphy + - rockchip,rk1808-csi-dphy + - rockchip,rk3326-csi-dphy + - rockchip,rk3368-csi-dphy + - rockchip,rk3568-csi-dphy + then: + properties: + resets: + maxItems: 1 + + reset-names: + maxItems: 1 + else: + properties: + resets: + minItems: 2 + + reset-names: + minItems: 2 =20 required: - compatible @@ -91,3 +120,22 @@ examples: reset-names =3D "apb"; rockchip,grf =3D <&grf>; }; + - | + #include + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + phy@fedc0000 { + compatible =3D "rockchip,rk3588-csi-dphy"; + reg =3D <0x0 0xfedc0000 0x0 0x8000>; + clocks =3D <&cru PCLK_CSIPHY0>; + clock-names =3D "pclk"; + #phy-cells =3D <0>; + resets =3D <&cru SRST_P_CSIPHY0>, <&cru SRST_CSIPHY0>; + reset-names =3D "apb", "phy"; + rockchip,grf =3D <&csidphy0_grf>; + }; + }; --=20 2.39.5 From nobody Fri Oct 3 11:26:44 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3931C2459D1; Mon, 1 Sep 2025 21:01:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756760513; cv=none; b=dHtdVwGVso7aMMUP82/v80sjJxcxEef6DkmAgBJwLyzrCMTybXivQT7c53cpdiSJHwu9ZQRr51u+OF3q7TOP5H/wycN0I+++ubWrTV6Ji62p4Zrn6KODr7q4ADiyhbYpIss/ONAv+88JLb0/1HEbEcqtNgGNOZVnufELp08Zn0M= ARC-Message-Signature: i=1; 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b=KrgHM3SeV6URt8G9/vWzTXxnVaHDOEDBGUPwCbk7K1eEHgAgdOerbADZGKoiSS6RL ZptWcoQffh2gYydUz7q9XmrChuVYEZiw0p1WmgXOjI1fd5pubZFShhklnpGV8/JNxt D3y/eXTCuGtQDrEdLkzW7mLoMvcPAitpcsf8ezg+vTRRDBMcSXD3SbFA/6GCHMd0/x dGexMiigs+HM2hgJN3711Iy3gQvRNKp+VHs6R87Ojc5xrtxCALry2iW9Dp0kVzReXr tCViXTT02Xfk0VDLstipWaaWHVTAtTLNNa3isN0lmBNU4afHDhzRXNdDaOAJERCDf1 PAjSfTf+9Er8w== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id C0C16CA1007; Mon, 1 Sep 2025 21:01:52 +0000 (UTC) From: Michael Riesch via B4 Relay Date: Mon, 01 Sep 2025 22:47:45 +0200 Subject: [PATCH v3 4/7] phy: rockchip: phy-rockchip-inno-csidphy: allow writes to grf register 0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250616-rk3588-csi-dphy-v3-4-a5ccd5f1f438@collabora.com> References: <20250616-rk3588-csi-dphy-v3-0-a5ccd5f1f438@collabora.com> In-Reply-To: <20250616-rk3588-csi-dphy-v3-0-a5ccd5f1f438@collabora.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Vinod Koul , Kishon Vijay Abraham I , Philipp Zabel , Kever Yang , Jagan Teki , Sebastian Reichel , Diederik de Haas , Neil Armstrong , Heiko Stuebner , Collabora Kernel Team Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, Michael Riesch X-Mailer: b4 0.12.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756759662; l=1635; i=michael.riesch@collabora.com; s=20250410; h=from:subject:message-id; bh=l+DL7hvrQb52Alb7OjVyKnZ7Z6pkTmglNXwtSvoPg4M=; b=VBFa5PVV+22ZkBz4mEv89SE3mpULD6Gqp49UwNptsIWrtomhKNQUoNYSe2JnT756e/eyHOWH6 Vftcu8BdJF/Dil2nAXwnqCv++Sxfomn8BmTNbQv4p96wHKkSqjH2reL X-Developer-Key: i=michael.riesch@collabora.com; a=ed25519; pk=+MWX1fffLFZtTPG/I6XdYm/+OSvpRE8D9evQaWbiN04= X-Endpoint-Received: by B4 Relay for michael.riesch@collabora.com/20250410 with auth_id=371 X-Original-From: Michael Riesch Reply-To: michael.riesch@collabora.com From: Michael Riesch The driver for the Rockchip MIPI CSI-2 DPHY uses GRF register offset value 0 to sort out undefined registers. However, the RK3588 CSIDPHY GRF this offset is perfectly fine (in fact, register 0 is the only one in this register file). Introduce a boolean variable to indicate valid registers and allow writes to register 0. Reviewed-by: Neil Armstrong Signed-off-by: Michael Riesch --- drivers/phy/rockchip/phy-rockchip-inno-csidphy.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-inno-csidphy.c b/drivers/phy= /rockchip/phy-rockchip-inno-csidphy.c index 2ab99e1d47eb..75533d071025 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-csidphy.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-csidphy.c @@ -87,10 +87,11 @@ struct dphy_reg { u32 offset; u32 mask; u32 shift; + u8 valid; }; =20 #define PHY_REG(_offset, _width, _shift) \ - { .offset =3D _offset, .mask =3D BIT(_width) - 1, .shift =3D _shift, } + { .offset =3D _offset, .mask =3D BIT(_width) - 1, .shift =3D _shift, .val= id =3D 1, } =20 static const struct dphy_reg rk1808_grf_dphy_regs[] =3D { [GRF_DPHY_CSIPHY_FORCERXMODE] =3D PHY_REG(RK1808_GRF_PD_VI_CON_OFFSET, 4,= 0), @@ -145,7 +146,7 @@ static inline void write_grf_reg(struct rockchip_inno_c= sidphy *priv, const struct dphy_drv_data *drv_data =3D priv->drv_data; const struct dphy_reg *reg =3D &drv_data->grf_regs[index]; =20 - if (reg->offset) + if (reg->valid) regmap_write(priv->grf, reg->offset, HIWORD_UPDATE(value, reg->mask, reg->shift)); } --=20 2.39.5 From nobody Fri Oct 3 11:26:44 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 13EDE20B1F5; Mon, 1 Sep 2025 21:01:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756760513; cv=none; b=NDR39JOTXInr2dh0uq6ZfZ12aEAEI57cFMSX3MyJBJnehM6rgN2rTuG41ZtfTtZZ5CklkIDEpAKz4ULbUiDnmoa2qsNDJbtrAFFTU24/dan/hdjL7dBxmWpB5U9gL4ct9MKkoEVyxD3Gpa3LFT95SxATBcwGsmpAMn1hO3UWtgk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756760513; c=relaxed/simple; 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Mon, 1 Sep 2025 21:01:52 +0000 (UTC) From: Michael Riesch via B4 Relay Date: Mon, 01 Sep 2025 22:47:46 +0200 Subject: [PATCH v3 5/7] phy: rockchip: phy-rockchip-inno-csidphy: allow for different reset lines Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250616-rk3588-csi-dphy-v3-5-a5ccd5f1f438@collabora.com> References: <20250616-rk3588-csi-dphy-v3-0-a5ccd5f1f438@collabora.com> In-Reply-To: <20250616-rk3588-csi-dphy-v3-0-a5ccd5f1f438@collabora.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Vinod Koul , Kishon Vijay Abraham I , Philipp Zabel , Kever Yang , Jagan Teki , Sebastian Reichel , Diederik de Haas , Neil Armstrong , Heiko Stuebner , Collabora Kernel Team Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, Michael Riesch X-Mailer: b4 0.12.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756759662; l=4524; i=michael.riesch@collabora.com; s=20250410; h=from:subject:message-id; bh=ouqlgbnwWSp9gE4kXLQdfgX4LelZawR0mUFaykrHL9U=; b=iIw40vlnqv7ELAPioeNy9fNahML68VfNknHBX8bNvDq/Q++vyjwVq9KwJHjq3DUEIa+ffqc40 msCSS1kBtTIC5eI9qI1Rf6+nzQldjKi8zqvPXc3H0x5St48/voapoXl X-Developer-Key: i=michael.riesch@collabora.com; a=ed25519; pk=+MWX1fffLFZtTPG/I6XdYm/+OSvpRE8D9evQaWbiN04= X-Endpoint-Received: by B4 Relay for michael.riesch@collabora.com/20250410 with auth_id=371 X-Original-From: Michael Riesch Reply-To: michael.riesch@collabora.com From: Michael Riesch The RK3588 MIPI CSI-2 DPHY variant requires two reset lines. Add support for different sets of reset lines to the phy-rockchip-inno-csidphy driver as preparation for the introduction of the RK3588 variant. Signed-off-by: Michael Riesch --- drivers/phy/rockchip/phy-rockchip-inno-csidphy.c | 34 ++++++++++++++++++++= +--- 1 file changed, 30 insertions(+), 4 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-inno-csidphy.c b/drivers/phy= /rockchip/phy-rockchip-inno-csidphy.c index 75533d071025..6c4ddcd7e5de 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-csidphy.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-csidphy.c @@ -67,6 +67,8 @@ #define RK1808_CSIDPHY_CLK_CALIB_EN 0x168 #define RK3568_CSIDPHY_CLK_CALIB_EN 0x168 =20 +#define RESETS_MAX 2 + /* * The higher 16-bit of this register is used for write protection * only if BIT(x + 16) set to 1 the BIT(x) can be written. @@ -127,6 +129,8 @@ struct dphy_drv_data { const struct hsfreq_range *hsfreq_ranges; int num_hsfreq_ranges; const struct dphy_reg *grf_regs; + const char *const *resets; + unsigned int resets_num; }; =20 struct rockchip_inno_csidphy { @@ -134,7 +138,8 @@ struct rockchip_inno_csidphy { void __iomem *phy_base; struct clk *pclk; struct regmap *grf; - struct reset_control *rst; + struct reset_control_bulk_data resets[RESETS_MAX]; + unsigned int resets_num; const struct dphy_drv_data *drv_data; struct phy_configure_opts_mipi_dphy config; u8 hsfreq; @@ -174,6 +179,10 @@ static const struct hsfreq_range rk3368_mipidphy_hsfre= q_ranges[] =3D { {1249, 0x0c}, {1349, 0x0d}, {1500, 0x0e} }; =20 +static const char *const rk3368_reset_names[] =3D { + "apb" +}; + static void rockchip_inno_csidphy_ths_settle(struct rockchip_inno_csidphy = *priv, int hsfreq, int offset) { @@ -344,6 +353,8 @@ static const struct dphy_drv_data rk1808_mipidphy_drv_d= ata =3D { .hsfreq_ranges =3D rk1808_mipidphy_hsfreq_ranges, .num_hsfreq_ranges =3D ARRAY_SIZE(rk1808_mipidphy_hsfreq_ranges), .grf_regs =3D rk1808_grf_dphy_regs, + .resets =3D rk3368_reset_names, + .resets_num =3D ARRAY_SIZE(rk3368_reset_names), }; =20 static const struct dphy_drv_data rk3326_mipidphy_drv_data =3D { @@ -353,6 +364,8 @@ static const struct dphy_drv_data rk3326_mipidphy_drv_d= ata =3D { .hsfreq_ranges =3D rk3326_mipidphy_hsfreq_ranges, .num_hsfreq_ranges =3D ARRAY_SIZE(rk3326_mipidphy_hsfreq_ranges), .grf_regs =3D rk3326_grf_dphy_regs, + .resets =3D rk3368_reset_names, + .resets_num =3D ARRAY_SIZE(rk3368_reset_names), }; =20 static const struct dphy_drv_data rk3368_mipidphy_drv_data =3D { @@ -362,6 +375,8 @@ static const struct dphy_drv_data rk3368_mipidphy_drv_d= ata =3D { .hsfreq_ranges =3D rk3368_mipidphy_hsfreq_ranges, .num_hsfreq_ranges =3D ARRAY_SIZE(rk3368_mipidphy_hsfreq_ranges), .grf_regs =3D rk3368_grf_dphy_regs, + .resets =3D rk3368_reset_names, + .resets_num =3D ARRAY_SIZE(rk3368_reset_names), }; =20 static const struct dphy_drv_data rk3568_mipidphy_drv_data =3D { @@ -371,6 +386,8 @@ static const struct dphy_drv_data rk3568_mipidphy_drv_d= ata =3D { .hsfreq_ranges =3D rk1808_mipidphy_hsfreq_ranges, .num_hsfreq_ranges =3D ARRAY_SIZE(rk1808_mipidphy_hsfreq_ranges), .grf_regs =3D rk3568_grf_dphy_regs, + .resets =3D rk3368_reset_names, + .resets_num =3D ARRAY_SIZE(rk3368_reset_names), }; =20 static const struct of_device_id rockchip_inno_csidphy_match_id[] =3D { @@ -404,6 +421,7 @@ static int rockchip_inno_csidphy_probe(struct platform_= device *pdev) struct device *dev =3D &pdev->dev; struct phy_provider *phy_provider; struct phy *phy; + int ret; =20 priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); if (!priv) @@ -435,10 +453,18 @@ static int rockchip_inno_csidphy_probe(struct platfor= m_device *pdev) return PTR_ERR(priv->pclk); } =20 - priv->rst =3D devm_reset_control_get(dev, "apb"); - if (IS_ERR(priv->rst)) { + if (priv->drv_data->resets_num > RESETS_MAX) { + dev_err(dev, "invalid number of resets\n"); + return -EINVAL; + } + priv->resets_num =3D priv->drv_data->resets_num; + for (unsigned int i =3D 0; i < priv->resets_num; i++) + priv->resets[i].id =3D priv->drv_data->resets[i]; + ret =3D devm_reset_control_bulk_get_exclusive(dev, priv->resets_num, + priv->resets); + if (ret) { dev_err(dev, "failed to get system reset control\n"); - return PTR_ERR(priv->rst); + return ret; } =20 phy =3D devm_phy_create(dev, NULL, &rockchip_inno_csidphy_ops); --=20 2.39.5 From nobody Fri Oct 3 11:26:44 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 39D3A246348; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250616-rk3588-csi-dphy-v3-6-a5ccd5f1f438@collabora.com> References: <20250616-rk3588-csi-dphy-v3-0-a5ccd5f1f438@collabora.com> In-Reply-To: <20250616-rk3588-csi-dphy-v3-0-a5ccd5f1f438@collabora.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Vinod Koul , Kishon Vijay Abraham I , Philipp Zabel , Kever Yang , Jagan Teki , Sebastian Reichel , Diederik de Haas , Neil Armstrong , Heiko Stuebner , Collabora Kernel Team Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, Michael Riesch X-Mailer: b4 0.12.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756759662; l=2783; i=michael.riesch@collabora.com; s=20250410; h=from:subject:message-id; bh=yeQXRqZNa57y0uWiIJSkXVpQ6zTLhd7z989yNwE9ju8=; b=axGHdEEOobUeI3zoNKyi3w/BvIeQnc8c0vieQuJvuILqmfq0hDhf2j9lz4n1HHC+mpZpcMGlQ sfnI99iovo6Aet9/dP2floam3L5KHcJtMU5lA8hHcrkYTxJ+rk2qwrA X-Developer-Key: i=michael.riesch@collabora.com; a=ed25519; pk=+MWX1fffLFZtTPG/I6XdYm/+OSvpRE8D9evQaWbiN04= X-Endpoint-Received: by B4 Relay for michael.riesch@collabora.com/20250410 with auth_id=371 X-Original-From: Michael Riesch Reply-To: michael.riesch@collabora.com From: Michael Riesch The Rockchip RK3588 MIPI CSI-2 DPHY can be supported using the existing phy-rockchip-inno-csidphy driver, the notable differences being - the control bits in the GRF - the additional reset line Add support for this variant. Signed-off-by: Michael Riesch --- drivers/phy/rockchip/phy-rockchip-inno-csidphy.c | 28 ++++++++++++++++++++= ++++ 1 file changed, 28 insertions(+) diff --git a/drivers/phy/rockchip/phy-rockchip-inno-csidphy.c b/drivers/phy= /rockchip/phy-rockchip-inno-csidphy.c index 6c4ddcd7e5de..c79fb53d8ee5 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-csidphy.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-csidphy.c @@ -30,6 +30,8 @@ #define RK3568_GRF_VI_CON0 0x0340 #define RK3568_GRF_VI_CON1 0x0344 =20 +#define RK3588_CSIDPHY_GRF_CON0 0x0000 + /* PHY */ #define CSIDPHY_CTRL_LANE_ENABLE 0x00 #define CSIDPHY_CTRL_LANE_ENABLE_CK BIT(6) @@ -117,6 +119,12 @@ static const struct dphy_reg rk3568_grf_dphy_regs[] = =3D { [GRF_DPHY_CSIPHY_CLKLANE_EN] =3D PHY_REG(RK3568_GRF_VI_CON0, 1, 8), }; =20 +static const struct dphy_reg rk3588_grf_dphy_regs[] =3D { + [GRF_DPHY_CSIPHY_FORCERXMODE] =3D PHY_REG(RK3588_CSIDPHY_GRF_CON0, 4, 0), + [GRF_DPHY_CSIPHY_DATALANE_EN] =3D PHY_REG(RK3588_CSIDPHY_GRF_CON0, 4, 4), + [GRF_DPHY_CSIPHY_CLKLANE_EN] =3D PHY_REG(RK3588_CSIDPHY_GRF_CON0, 1, 8), +}; + struct hsfreq_range { u32 range_h; u8 cfg_bit; @@ -183,6 +191,11 @@ static const char *const rk3368_reset_names[] =3D { "apb" }; =20 +static const char *const rk3588_reset_names[] =3D { + "apb", + "phy" +}; + static void rockchip_inno_csidphy_ths_settle(struct rockchip_inno_csidphy = *priv, int hsfreq, int offset) { @@ -390,6 +403,17 @@ static const struct dphy_drv_data rk3568_mipidphy_drv_= data =3D { .resets_num =3D ARRAY_SIZE(rk3368_reset_names), }; =20 +static const struct dphy_drv_data rk3588_mipidphy_drv_data =3D { + .pwrctl_offset =3D -1, + .ths_settle_offset =3D RK3568_CSIDPHY_CLK_WR_THS_SETTLE, + .calib_offset =3D RK3568_CSIDPHY_CLK_CALIB_EN, + .hsfreq_ranges =3D rk1808_mipidphy_hsfreq_ranges, + .num_hsfreq_ranges =3D ARRAY_SIZE(rk1808_mipidphy_hsfreq_ranges), + .grf_regs =3D rk3588_grf_dphy_regs, + .resets =3D rk3588_reset_names, + .resets_num =3D ARRAY_SIZE(rk3588_reset_names), +}; + static const struct of_device_id rockchip_inno_csidphy_match_id[] =3D { { .compatible =3D "rockchip,px30-csi-dphy", @@ -411,6 +435,10 @@ static const struct of_device_id rockchip_inno_csidphy= _match_id[] =3D { .compatible =3D "rockchip,rk3568-csi-dphy", .data =3D &rk3568_mipidphy_drv_data, }, + { + .compatible =3D "rockchip,rk3588-csi-dphy", + .data =3D &rk3588_mipidphy_drv_data, + }, {} }; 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Mon, 1 Sep 2025 21:01:52 +0000 (UTC) From: Michael Riesch via B4 Relay Date: Mon, 01 Sep 2025 22:47:48 +0200 Subject: [PATCH v3 7/7] arm64: dts: rockchip: add mipi csi-2 dphy nodes to rk3588 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250616-rk3588-csi-dphy-v3-7-a5ccd5f1f438@collabora.com> References: <20250616-rk3588-csi-dphy-v3-0-a5ccd5f1f438@collabora.com> In-Reply-To: <20250616-rk3588-csi-dphy-v3-0-a5ccd5f1f438@collabora.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Vinod Koul , Kishon Vijay Abraham I , Philipp Zabel , Kever Yang , Jagan Teki , Sebastian Reichel , Diederik de Haas , Neil Armstrong , Heiko Stuebner , Collabora Kernel Team Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, Michael Riesch X-Mailer: b4 0.12.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756759662; l=1931; i=michael.riesch@collabora.com; s=20250410; h=from:subject:message-id; bh=6HJuYpXttybyTSrCNqhc1jbMr3cQPoLfqzHZNqsOuiw=; b=McvJKQT7Br08M3TRS8UuRnrp3U7iZxUgI1O6Ym5fvVFYb8DPOOC7ruTNqjDKBlXnXRXmYEO7U x6hhasYYQPLA/WfT5QixZLRluPyl/iZyhzekZ4+vHruZ7iXZWWUvIqB X-Developer-Key: i=michael.riesch@collabora.com; a=ed25519; pk=+MWX1fffLFZtTPG/I6XdYm/+OSvpRE8D9evQaWbiN04= X-Endpoint-Received: by B4 Relay for michael.riesch@collabora.com/20250410 with auth_id=371 X-Original-From: Michael Riesch Reply-To: michael.riesch@collabora.com From: Michael Riesch The Rockchip RK3588 features two MIPI CSI-2 DPHYs. Add the device tree nodes for them. Signed-off-by: Michael Riesch --- arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 33 +++++++++++++++++++++++= ++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boo= t/dts/rockchip/rk3588-base.dtsi index 70f03e68ba55..eedf93247e9c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -621,6 +621,16 @@ php_grf: syscon@fd5b0000 { reg =3D <0x0 0xfd5b0000 0x0 0x1000>; }; =20 + csidphy0_grf: syscon@fd5b4000 { + compatible =3D "rockchip,rk3588-csidphy-grf", "syscon"; + reg =3D <0x0 0xfd5b4000 0x0 0x1000>; + }; + + csidphy1_grf: syscon@fd5b5000 { + compatible =3D "rockchip,rk3588-csidphy-grf", "syscon"; + reg =3D <0x0 0xfd5b5000 0x0 0x1000>; + }; + pipe_phy0_grf: syscon@fd5bc000 { compatible =3D "rockchip,rk3588-pipe-phy-grf", "syscon"; reg =3D <0x0 0xfd5bc000 0x0 0x100>; @@ -3052,6 +3062,29 @@ mipidcphy1: phy@fedb0000 { <&cru SRST_S_MIPI_DCPHY1>; reset-names =3D "m_phy", "apb", "grf", "s_phy"; #phy-cells =3D <1>; + }; + + csi_dphy0: phy@fedc0000 { + compatible =3D "rockchip,rk3588-csi-dphy"; + reg =3D <0x0 0xfedc0000 0x0 0x8000>; + clocks =3D <&cru PCLK_CSIPHY0>; + clock-names =3D "pclk"; + #phy-cells =3D <0>; + resets =3D <&cru SRST_P_CSIPHY0>, <&cru SRST_CSIPHY0>; + reset-names =3D "apb", "phy"; + rockchip,grf =3D <&csidphy0_grf>; + status =3D "disabled"; + }; + + csi_dphy1: phy@fedc8000 { + compatible =3D "rockchip,rk3588-csi-dphy"; + reg =3D <0x0 0xfedc8000 0x0 0x8000>; + clocks =3D <&cru PCLK_CSIPHY1>; + clock-names =3D "pclk"; + #phy-cells =3D <0>; + resets =3D <&cru SRST_P_CSIPHY1>, <&cru SRST_CSIPHY1>; + reset-names =3D "apb", "phy"; + rockchip,grf =3D <&csidphy1_grf>; status =3D "disabled"; }; =20 --=20 2.39.5