From nobody Sat Oct 4 08:05:11 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BCF503451B0; Mon, 18 Aug 2025 23:14:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755558873; cv=none; b=EtppewdgiuxHmUsN2iynapFAeHCAXpJxtg2abic/IsYjjPTz3DkUdw2c8AEgfBKsFZdy7WYqk9GxSCIsX5uVp/0Qommmzc1WSCunX7REFX1GpQAgV4HtrRpqNihNRNrih6OW0T0ZJjbDWCKAGyDwIdDJ3yH+EIBoItmv4i7mDG4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755558873; c=relaxed/simple; bh=1sx3B1KICtDjf4DR2eWZu0vSeJzYHOxzQ4xJumzeAtc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=uS5OAlWZsD3+BlRMpSkVokQB+2Fs/+wkjewJnigtpMLFGSNs4GOWRyIGw3jvs6Uthz2chmDqpmDuKnB9E9+793pL895p4ZH0PjkDflbgw4INo2WyHNYGPUkAGBPKtmPvX7RkyZZGmYO5Rgju6ASSR1mCAG1cHRVWpXPFCPhrPoc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=kp5TBcx5; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="kp5TBcx5" Received: by smtp.kernel.org (Postfix) with ESMTPS id 65358C4CEF1; Mon, 18 Aug 2025 23:14:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755558873; bh=1sx3B1KICtDjf4DR2eWZu0vSeJzYHOxzQ4xJumzeAtc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=kp5TBcx5Et95AVIF80WQgYameSH77W80k98u6hqqbT8XzHN2hNZGQpMZt/eD6VLw5 mMYVyk/aBPJparD/w/9SKCrKD+LYNPAvFgBh1YVQQcctliVOgNMzDiffKzzuBdYeGP HvIB9cjaTf9kfH4pVI8m9z8gLDKQgc69Zur+n6abDgQ47ZZZdYNg91qD6BSoqFQdEY IXdeX69O/fuSHZ8UTl0jQArVjLtS1MFnlAYer5AGFPhbzzNQ15OJVhELHS3xHQa4mg MtoUeANZRV+pxsNT6q7VVVANpDkQTNRS4XVmh8+B/UvVbXUTJQSOuW1Mchfv8qyB+Y fIXvh6o4l2+qw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5449ACA0ED1; Mon, 18 Aug 2025 23:14:33 +0000 (UTC) From: Michael Riesch via B4 Relay Date: Tue, 19 Aug 2025 01:00:35 +0200 Subject: [PATCH v2 1/7] dt-bindings: soc: rockchip: add rk3588 csidphy grf syscon Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250616-rk3588-csi-dphy-v2-1-7a94f079b712@collabora.com> References: <20250616-rk3588-csi-dphy-v2-0-7a94f079b712@collabora.com> In-Reply-To: <20250616-rk3588-csi-dphy-v2-0-7a94f079b712@collabora.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Vinod Koul , Kishon Vijay Abraham I , Philipp Zabel , Kever Yang , Jagan Teki , Sebastian Reichel , Diederik de Haas , Neil Armstrong , Heiko Stuebner , Collabora Kernel Team Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, Michael Riesch X-Mailer: b4 0.12.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1755558041; l=927; i=michael.riesch@collabora.com; s=20250410; h=from:subject:message-id; bh=+caMXhRTVArPpx+x7pVyqXS9t7uDPpRu8sQdXP1mzpo=; b=mJW2C/Sgu9YPmlfYtkC+t4kXopDPZCvY9eIm5X81XBhFsZaeowIt+14ocQDcDKAc018WvOPlQ WBDDe2to+igBcK/Q3l2DVWYyg2rCmxf+2fbYTmWIH+YEx0HVj9GH3J6 X-Developer-Key: i=michael.riesch@collabora.com; a=ed25519; pk=+MWX1fffLFZtTPG/I6XdYm/+OSvpRE8D9evQaWbiN04= X-Endpoint-Received: by B4 Relay for michael.riesch@collabora.com/20250410 with auth_id=371 X-Original-From: Michael Riesch Reply-To: michael.riesch@collabora.com From: Michael Riesch Add CSIDPHY GRF syscon compatible for the Rockchip RK3588. Acked-by: Rob Herring (Arm) Signed-off-by: Michael Riesch --- Documentation/devicetree/bindings/soc/rockchip/grf.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Docu= mentation/devicetree/bindings/soc/rockchip/grf.yaml index 1ab0b092e2a5..b6e04e6491e9 100644 --- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml +++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml @@ -47,6 +47,7 @@ properties: - rockchip,rk3576-vop-grf - rockchip,rk3588-bigcore0-grf - rockchip,rk3588-bigcore1-grf + - rockchip,rk3588-csidphy-grf - rockchip,rk3588-dcphy-grf - rockchip,rk3588-hdptxphy-grf - rockchip,rk3588-ioc --=20 2.39.5 From nobody Sat Oct 4 08:05:11 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D4DD6271479; Mon, 18 Aug 2025 23:14:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755558873; cv=none; b=JjIKUdrymnBUlaggmgJt9gX2W2JxkgEsqk5uHV45n814XS6NgbXoCAWhJy+oeiEZ76+x7X91KCFBYrK7GUeC0juReA013IYmw7yBkuU5/AEZlZFVtbwPW+z+E3NZjxEFlEFtgHDz09yDjncYxWItemcJlYba9BWVFG+iV5ZDz74= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755558873; c=relaxed/simple; bh=0xx0IJoMzOucP0haOQqdQWmzEebko4LTzBsDTQcA7Mo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=caSTWHQHCT9ISOqpoBgatdagTgigWRtEq7C1at2D3o2xHWK3qApdMkG+pHfpcwgO50o+hPn3JIXdnpTUN/qo0f8KkWTQVfrepYrpSwSVvy7u1uSWdYkIDSkC66I49sDENPT6XNgZgQEQuF20mLnKa8uHQXFQFdYzhFkuOxOGY2c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ERDuXmB5; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ERDuXmB5" Received: by smtp.kernel.org (Postfix) with ESMTPS id 72660C116C6; Mon, 18 Aug 2025 23:14:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755558873; bh=0xx0IJoMzOucP0haOQqdQWmzEebko4LTzBsDTQcA7Mo=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=ERDuXmB5lB9maQtFAB+RIRVWamyRF2dRwA3I30HdV2xeolXCeNCZ/THEG+sROyiOL x7Qnnpxu9/Go3IMJ9HWrnJu+unEOOCRVx69UxFP6NSmLgEW/KFjC/6XKctPCoQ7R5n Hp8rwWz+QHSMhiPXOn2sQ64HaxLcJkw/9RpY4faz0/Gg7/aQn4MQyo4lgbEghQB7Ff V816OuOFvkiS1gR2AfwWrXHaa8izQfo0oR6vLpyJDzyCSQO7Gr9iM9GRGFZFbl5faN /QWcFoT3Wwz56BMAv8vWE5yh5Ki+oVyZbxGoHLnjl7oEhbTWeGg0gBnfUh3rL/5VMb 03DNdJ0McfZSA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 63104CA0EE4; Mon, 18 Aug 2025 23:14:33 +0000 (UTC) From: Michael Riesch via B4 Relay Date: Tue, 19 Aug 2025 01:00:36 +0200 Subject: [PATCH v2 2/7] dt-bindings: phy: rockchip-inno-csi-dphy: make power-domains non-required Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250616-rk3588-csi-dphy-v2-2-7a94f079b712@collabora.com> References: <20250616-rk3588-csi-dphy-v2-0-7a94f079b712@collabora.com> In-Reply-To: <20250616-rk3588-csi-dphy-v2-0-7a94f079b712@collabora.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Vinod Koul , Kishon Vijay Abraham I , Philipp Zabel , Kever Yang , Jagan Teki , Sebastian Reichel , Diederik de Haas , Neil Armstrong , Heiko Stuebner , Collabora Kernel Team Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, Michael Riesch , stable@kernel.org X-Mailer: b4 0.12.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1755558041; l=1044; i=michael.riesch@collabora.com; s=20250410; h=from:subject:message-id; bh=Go0u6t1x/ipwgH+GR3AzJirmRWY+4+iYdBgXNBVJROU=; b=LRvqcmRsfi+qNcFR50w3OSyZhd3H4xAWaGzAUW/3tRJeUk/K7JfpQIr3eEisnHF/HQXqwjwH2 2yocIw/v3I4DPtSQxqHpr+kuwYNjhpQJIldjuwHWgLcUy3U7x7opAhA X-Developer-Key: i=michael.riesch@collabora.com; a=ed25519; pk=+MWX1fffLFZtTPG/I6XdYm/+OSvpRE8D9evQaWbiN04= X-Endpoint-Received: by B4 Relay for michael.riesch@collabora.com/20250410 with auth_id=371 X-Original-From: Michael Riesch Reply-To: michael.riesch@collabora.com From: Michael Riesch There are variants of the Rockchip Innosilicon CSI DPHY (e.g., the RK3568 variant) that are powered on by default as they are part of the ALIVE power domain. Remove 'power-domains' from the required properties in order to avoid false negatives. Fixes: 22c8e0a69b7f ("dt-bindings: phy: add compatible for rk356x to rockch= ip-inno-csi-dphy") Cc: stable@kernel.org Signed-off-by: Michael Riesch --- Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml | 1 - 1 file changed, 1 deletion(-) diff --git a/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.y= aml b/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml index 5ac994b3c0aa..42da616ae2e3 100644 --- a/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml +++ b/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml @@ -57,7 +57,6 @@ required: - clocks - clock-names - '#phy-cells' - - power-domains - resets - reset-names - rockchip,grf --=20 2.39.5 From nobody Sat Oct 4 08:05:11 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D4D6C26FA6F; Mon, 18 Aug 2025 23:14:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755558873; cv=none; b=lbWSNZVOmKl/0rBPMUVR+UvJfeWps2b2QMkHPuQqz/Nn+GbF23QZ/NMC2B+4pWTU7DIi9C657s5tjbthheHuZN0cacgmBSTVZbxiZwILiB0M8avBHUV0YDyxweX1BjOgaUmwQmmzmr9WeGbSimcCUWx/Sg6TYxiEow8/YRdMoZM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755558873; c=relaxed/simple; bh=C8JbbdDqM8lge0snDOXhphGmPRbweJnkcQYl4O2Lpuk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=LeoJkdWzl0VA8E3JbIKFRt3nNYJ482+eAp1BYm04gvKFHbx+XQ+BBcZIOWK6HdAFII5SF5HpxpFMbF007Nnwv5z1O6gnZVjJ8O4YE8dvYlodfFNWYC3ujA+6J+2F7P6ehXkwsc/1ufCznCH1c278iFYjCy+r3A1ig9p+dE/+y3I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=M8oa5Jd7; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="M8oa5Jd7" Received: by smtp.kernel.org (Postfix) with ESMTPS id 79E4FC19421; Mon, 18 Aug 2025 23:14:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755558873; bh=C8JbbdDqM8lge0snDOXhphGmPRbweJnkcQYl4O2Lpuk=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=M8oa5Jd73CLwo3dCzUa7TgbVZrBH+pXaskBKXW5ypYFF9nD9xQu8MsIXmIiLBLBq/ jPJh6p/yOiVu/Exxt8famo5syinIp1GfwLXgYa9SrIubDy5kkR0D7qULRKMinz2LLV MWxdJWjwPs697lCFUwLke8uYvZyXotSf/zP/sZ/CLqWrGiW8Qd1Z1IK845Jcr1jVNg nbFoJ/hP/1AFPUoaf+KLcFkwHxmfkquIQo3lpya79QxY7UTH8Lthyom7lj8rLPMAqi bS8ONHQ1U3MPPCtcVsllK7ct42SRFrAQWcCWRIGlIUq0PvT/ZQfF/ttsFD/2GIWwIF M9buD6BtQp6nA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 70EB6CA0EF1; Mon, 18 Aug 2025 23:14:33 +0000 (UTC) From: Michael Riesch via B4 Relay Date: Tue, 19 Aug 2025 01:00:37 +0200 Subject: [PATCH v2 3/7] dt-bindings: phy: rockchip-inno-csi-dphy: add rk3588 variant Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250616-rk3588-csi-dphy-v2-3-7a94f079b712@collabora.com> References: <20250616-rk3588-csi-dphy-v2-0-7a94f079b712@collabora.com> In-Reply-To: <20250616-rk3588-csi-dphy-v2-0-7a94f079b712@collabora.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Vinod Koul , Kishon Vijay Abraham I , Philipp Zabel , Kever Yang , Jagan Teki , Sebastian Reichel , Diederik de Haas , Neil Armstrong , Heiko Stuebner , Collabora Kernel Team Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, Michael Riesch X-Mailer: b4 0.12.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1755558041; l=2827; i=michael.riesch@collabora.com; s=20250410; h=from:subject:message-id; bh=PMDzlrQeY+NRmFqopM/ChR6/5pYbe3wSrubFJu+0sMU=; b=AEtLzU240l3giMFwyKl21EH9Gejgiu6qeYmvs3lvFhzWFKQ1tm7t0mCqCxz29QeDKQCU7vmKM w70rtAqj0rKAfrDEtilu6hzdb8YHSeHoMX79gE1BCU3lqkrWLYpYDVC X-Developer-Key: i=michael.riesch@collabora.com; a=ed25519; pk=+MWX1fffLFZtTPG/I6XdYm/+OSvpRE8D9evQaWbiN04= X-Endpoint-Received: by B4 Relay for michael.riesch@collabora.com/20250410 with auth_id=371 X-Original-From: Michael Riesch Reply-To: michael.riesch@collabora.com From: Michael Riesch The Rockchip RK3588 variant of the CSI-2 DPHY features two reset lines. Add the variant and allow for the additional reset. Signed-off-by: Michael Riesch --- .../bindings/phy/rockchip-inno-csi-dphy.yaml | 60 ++++++++++++++++++= ++-- 1 file changed, 56 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.y= aml b/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml index 42da616ae2e3..10197cc9dc47 100644 --- a/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml +++ b/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml @@ -21,6 +21,7 @@ properties: - rockchip,rk3326-csi-dphy - rockchip,rk3368-csi-dphy - rockchip,rk3568-csi-dphy + - rockchip,rk3588-csi-dphy =20 reg: maxItems: 1 @@ -39,18 +40,50 @@ properties: maxItems: 1 =20 resets: - items: - - description: exclusive PHY reset line + minItems: 1 + maxItems: 2 =20 reset-names: - items: - - const: apb + minItems: 1 + maxItems: 2 =20 rockchip,grf: $ref: /schemas/types.yaml#/definitions/phandle description: Some additional phy settings are access through GRF regs. =20 +allOf: + - if: + properties: + compatible: + contains: + enum: + - rockchip,px30-csi-dphy + - rockchip,rk1808-csi-dphy + - rockchip,rk3326-csi-dphy + - rockchip,rk3368-csi-dphy + - rockchip,rk3568-csi-dphy + then: + properties: + resets: + items: + - description: exclusive PHY reset line + + reset-names: + items: + - const: apb + else: + properties: + resets: + items: + - description: APB reset line + - description: PHY reset line + + reset-names: + items: + - const: apb + - const: phy + required: - compatible - reg @@ -77,3 +110,22 @@ examples: reset-names =3D "apb"; rockchip,grf =3D <&grf>; }; + - | + #include + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + phy@fedc0000 { + compatible =3D "rockchip,rk3588-csi-dphy"; + reg =3D <0x0 0xfedc0000 0x0 0x8000>; + clocks =3D <&cru PCLK_CSIPHY0>; + clock-names =3D "pclk"; + #phy-cells =3D <0>; + resets =3D <&cru SRST_P_CSIPHY0>, <&cru SRST_CSIPHY0>; + reset-names =3D "apb", "phy"; + rockchip,grf =3D <&csidphy0_grf>; + }; + }; --=20 2.39.5 From nobody Sat Oct 4 08:05:11 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F19F12765C1; Mon, 18 Aug 2025 23:14:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755558874; cv=none; b=ue+cJ9miZPFaB7vythPqyHdMi9VD6Dd533h2YOooOeNfm6WQN7smzirrNVi2lR20+lBhyfN9BDSXGgfJnWugPcWEIOuu9I2PaxLKR5MhILHBIccxv4yPLJhGgT9LeH9VjK5GfzCphJ/kaVJvWbNM+aYFBmRT8LWs5gKoN7INXl8= ARC-Message-Signature: i=1; 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b=L9ucp7Uc0m8SjWdcDmIQXxiOl51ybpRVUE07PHOWyBiCmBI0rRCH06d4EGEArP+6d 1Sj1yIldLWSRSUONlREC6FYRwJgLL+k7xeiRO2bKsiX/dpu0ZUmzdEjm39MMYHmCbm r+ag05HrAk8COsjTfcYl4IgZCZg40XB2JAh6385czQsGEUxpWXGD65a2tSlCRUjlIp QLSqKJ9WNMuS1eK1IPGV7uTRgIC31Y/tUGlZZlBNOmC3aItamImegnP+o5Ak+tSWG0 yaPllTB+wylW7Zt/q7FRN3P9LrmzjBGd4I53+/LyA8/ZkB2f/rHzsJsrVmAPXa7Mv9 ti+E9E31Pf29g== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7E4CECA0EEB; Mon, 18 Aug 2025 23:14:33 +0000 (UTC) From: Michael Riesch via B4 Relay Date: Tue, 19 Aug 2025 01:00:38 +0200 Subject: [PATCH v2 4/7] phy: rockchip: phy-rockchip-inno-csidphy: allow writes to grf register 0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250616-rk3588-csi-dphy-v2-4-7a94f079b712@collabora.com> References: <20250616-rk3588-csi-dphy-v2-0-7a94f079b712@collabora.com> In-Reply-To: <20250616-rk3588-csi-dphy-v2-0-7a94f079b712@collabora.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Vinod Koul , Kishon Vijay Abraham I , Philipp Zabel , Kever Yang , Jagan Teki , Sebastian Reichel , Diederik de Haas , Neil Armstrong , Heiko Stuebner , Collabora Kernel Team Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, Michael Riesch X-Mailer: b4 0.12.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1755558041; l=1635; i=michael.riesch@collabora.com; s=20250410; h=from:subject:message-id; bh=l+DL7hvrQb52Alb7OjVyKnZ7Z6pkTmglNXwtSvoPg4M=; b=pXPJZwAy06i273TUpg9KStsF+R+c795F7yrhSxnbDxTPGjyeDidNQSJcylokou69ywyeFxbSe DW2SJ7n2sj3C+8v1jwb9/XmlIWoeYc+HwLDA+foqYa9v4RP1NChfR7J X-Developer-Key: i=michael.riesch@collabora.com; a=ed25519; pk=+MWX1fffLFZtTPG/I6XdYm/+OSvpRE8D9evQaWbiN04= X-Endpoint-Received: by B4 Relay for michael.riesch@collabora.com/20250410 with auth_id=371 X-Original-From: Michael Riesch Reply-To: michael.riesch@collabora.com From: Michael Riesch The driver for the Rockchip MIPI CSI-2 DPHY uses GRF register offset value 0 to sort out undefined registers. However, the RK3588 CSIDPHY GRF this offset is perfectly fine (in fact, register 0 is the only one in this register file). Introduce a boolean variable to indicate valid registers and allow writes to register 0. Reviewed-by: Neil Armstrong Signed-off-by: Michael Riesch --- drivers/phy/rockchip/phy-rockchip-inno-csidphy.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-inno-csidphy.c b/drivers/phy= /rockchip/phy-rockchip-inno-csidphy.c index 2ab99e1d47eb..75533d071025 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-csidphy.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-csidphy.c @@ -87,10 +87,11 @@ struct dphy_reg { u32 offset; u32 mask; u32 shift; + u8 valid; }; =20 #define PHY_REG(_offset, _width, _shift) \ - { .offset =3D _offset, .mask =3D BIT(_width) - 1, .shift =3D _shift, } + { .offset =3D _offset, .mask =3D BIT(_width) - 1, .shift =3D _shift, .val= id =3D 1, } =20 static const struct dphy_reg rk1808_grf_dphy_regs[] =3D { [GRF_DPHY_CSIPHY_FORCERXMODE] =3D PHY_REG(RK1808_GRF_PD_VI_CON_OFFSET, 4,= 0), @@ -145,7 +146,7 @@ static inline void write_grf_reg(struct rockchip_inno_c= sidphy *priv, const struct dphy_drv_data *drv_data =3D priv->drv_data; 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Mon, 18 Aug 2025 23:14:33 +0000 (UTC) From: Michael Riesch via B4 Relay Date: Tue, 19 Aug 2025 01:00:39 +0200 Subject: [PATCH v2 5/7] phy: rockchip: phy-rockchip-inno-csidphy: allow for different reset lines Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250616-rk3588-csi-dphy-v2-5-7a94f079b712@collabora.com> References: <20250616-rk3588-csi-dphy-v2-0-7a94f079b712@collabora.com> In-Reply-To: <20250616-rk3588-csi-dphy-v2-0-7a94f079b712@collabora.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Vinod Koul , Kishon Vijay Abraham I , Philipp Zabel , Kever Yang , Jagan Teki , Sebastian Reichel , Diederik de Haas , Neil Armstrong , Heiko Stuebner , Collabora Kernel Team Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, Michael Riesch X-Mailer: b4 0.12.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1755558041; l=4524; i=michael.riesch@collabora.com; s=20250410; h=from:subject:message-id; bh=ouqlgbnwWSp9gE4kXLQdfgX4LelZawR0mUFaykrHL9U=; b=utUoFVHlrsr4EU8QIQaS8DXpH6Av+lCw93f/ogF5lB54RmpAC+ET7PyeB/kzafXJXO1Dg3t9a VdY27HlGRn2Cn8Ld1C9NaqszxaVUxo3dQlPp9sAgirtBHnvFKcZLHbC X-Developer-Key: i=michael.riesch@collabora.com; a=ed25519; pk=+MWX1fffLFZtTPG/I6XdYm/+OSvpRE8D9evQaWbiN04= X-Endpoint-Received: by B4 Relay for michael.riesch@collabora.com/20250410 with auth_id=371 X-Original-From: Michael Riesch Reply-To: michael.riesch@collabora.com From: Michael Riesch The RK3588 MIPI CSI-2 DPHY variant requires two reset lines. Add support for different sets of reset lines to the phy-rockchip-inno-csidphy driver as preparation for the introduction of the RK3588 variant. Signed-off-by: Michael Riesch --- drivers/phy/rockchip/phy-rockchip-inno-csidphy.c | 34 ++++++++++++++++++++= +--- 1 file changed, 30 insertions(+), 4 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-inno-csidphy.c b/drivers/phy= /rockchip/phy-rockchip-inno-csidphy.c index 75533d071025..6c4ddcd7e5de 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-csidphy.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-csidphy.c @@ -67,6 +67,8 @@ #define RK1808_CSIDPHY_CLK_CALIB_EN 0x168 #define RK3568_CSIDPHY_CLK_CALIB_EN 0x168 =20 +#define RESETS_MAX 2 + /* * The higher 16-bit of this register is used for write protection * only if BIT(x + 16) set to 1 the BIT(x) can be written. @@ -127,6 +129,8 @@ struct dphy_drv_data { const struct hsfreq_range *hsfreq_ranges; int num_hsfreq_ranges; const struct dphy_reg *grf_regs; + const char *const *resets; + unsigned int resets_num; }; =20 struct rockchip_inno_csidphy { @@ -134,7 +138,8 @@ struct rockchip_inno_csidphy { void __iomem *phy_base; struct clk *pclk; struct regmap *grf; - struct reset_control *rst; + struct reset_control_bulk_data resets[RESETS_MAX]; + unsigned int resets_num; const struct dphy_drv_data *drv_data; struct phy_configure_opts_mipi_dphy config; u8 hsfreq; @@ -174,6 +179,10 @@ static const struct hsfreq_range rk3368_mipidphy_hsfre= q_ranges[] =3D { {1249, 0x0c}, {1349, 0x0d}, {1500, 0x0e} }; =20 +static const char *const rk3368_reset_names[] =3D { + "apb" +}; + static void rockchip_inno_csidphy_ths_settle(struct rockchip_inno_csidphy = *priv, int hsfreq, int offset) { @@ -344,6 +353,8 @@ static const struct dphy_drv_data rk1808_mipidphy_drv_d= ata =3D { .hsfreq_ranges =3D rk1808_mipidphy_hsfreq_ranges, .num_hsfreq_ranges =3D ARRAY_SIZE(rk1808_mipidphy_hsfreq_ranges), .grf_regs =3D rk1808_grf_dphy_regs, + .resets =3D rk3368_reset_names, + .resets_num =3D ARRAY_SIZE(rk3368_reset_names), }; =20 static const struct dphy_drv_data rk3326_mipidphy_drv_data =3D { @@ -353,6 +364,8 @@ static const struct dphy_drv_data rk3326_mipidphy_drv_d= ata =3D { .hsfreq_ranges =3D rk3326_mipidphy_hsfreq_ranges, .num_hsfreq_ranges =3D ARRAY_SIZE(rk3326_mipidphy_hsfreq_ranges), .grf_regs =3D rk3326_grf_dphy_regs, + .resets =3D rk3368_reset_names, + .resets_num =3D ARRAY_SIZE(rk3368_reset_names), }; =20 static const struct dphy_drv_data rk3368_mipidphy_drv_data =3D { @@ -362,6 +375,8 @@ static const struct dphy_drv_data rk3368_mipidphy_drv_d= ata =3D { .hsfreq_ranges =3D rk3368_mipidphy_hsfreq_ranges, .num_hsfreq_ranges =3D ARRAY_SIZE(rk3368_mipidphy_hsfreq_ranges), .grf_regs =3D rk3368_grf_dphy_regs, + .resets =3D rk3368_reset_names, + .resets_num =3D ARRAY_SIZE(rk3368_reset_names), }; =20 static const struct dphy_drv_data rk3568_mipidphy_drv_data =3D { @@ -371,6 +386,8 @@ static const struct dphy_drv_data rk3568_mipidphy_drv_d= ata =3D { .hsfreq_ranges =3D rk1808_mipidphy_hsfreq_ranges, .num_hsfreq_ranges =3D ARRAY_SIZE(rk1808_mipidphy_hsfreq_ranges), .grf_regs =3D rk3568_grf_dphy_regs, + .resets =3D rk3368_reset_names, + .resets_num =3D ARRAY_SIZE(rk3368_reset_names), }; =20 static const struct of_device_id rockchip_inno_csidphy_match_id[] =3D { @@ -404,6 +421,7 @@ static int rockchip_inno_csidphy_probe(struct platform_= device *pdev) struct device *dev =3D &pdev->dev; struct phy_provider *phy_provider; struct phy *phy; + int ret; =20 priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); if (!priv) @@ -435,10 +453,18 @@ static int rockchip_inno_csidphy_probe(struct platfor= m_device *pdev) return PTR_ERR(priv->pclk); } =20 - priv->rst =3D devm_reset_control_get(dev, "apb"); - if (IS_ERR(priv->rst)) { + if (priv->drv_data->resets_num > RESETS_MAX) { + dev_err(dev, "invalid number of resets\n"); + return -EINVAL; + } + priv->resets_num =3D priv->drv_data->resets_num; + for (unsigned int i =3D 0; i < priv->resets_num; i++) + priv->resets[i].id =3D priv->drv_data->resets[i]; + ret =3D devm_reset_control_bulk_get_exclusive(dev, priv->resets_num, + priv->resets); + if (ret) { dev_err(dev, "failed to get system reset control\n"); - return PTR_ERR(priv->rst); + return ret; } =20 phy =3D devm_phy_create(dev, NULL, &rockchip_inno_csidphy_ops); --=20 2.39.5 From nobody Sat Oct 4 08:05:11 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 00BC62765C5; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250616-rk3588-csi-dphy-v2-6-7a94f079b712@collabora.com> References: <20250616-rk3588-csi-dphy-v2-0-7a94f079b712@collabora.com> In-Reply-To: <20250616-rk3588-csi-dphy-v2-0-7a94f079b712@collabora.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Vinod Koul , Kishon Vijay Abraham I , Philipp Zabel , Kever Yang , Jagan Teki , Sebastian Reichel , Diederik de Haas , Neil Armstrong , Heiko Stuebner , Collabora Kernel Team Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, Michael Riesch X-Mailer: b4 0.12.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1755558041; l=2783; i=michael.riesch@collabora.com; s=20250410; h=from:subject:message-id; bh=yeQXRqZNa57y0uWiIJSkXVpQ6zTLhd7z989yNwE9ju8=; b=RAqZc+sTzvtEYxcjM95kNf/fWfwbUtNUOI2A4eF7RkP6L/dHfgQkU1m4ecM9kE8gKbmcJbXvI 9+mrsrc9e/gCdjvGNQCt0+H+Hn6AeQ0LJUSBfgPoaPPGupnSKwk+tab X-Developer-Key: i=michael.riesch@collabora.com; a=ed25519; pk=+MWX1fffLFZtTPG/I6XdYm/+OSvpRE8D9evQaWbiN04= X-Endpoint-Received: by B4 Relay for michael.riesch@collabora.com/20250410 with auth_id=371 X-Original-From: Michael Riesch Reply-To: michael.riesch@collabora.com From: Michael Riesch The Rockchip RK3588 MIPI CSI-2 DPHY can be supported using the existing phy-rockchip-inno-csidphy driver, the notable differences being - the control bits in the GRF - the additional reset line Add support for this variant. Signed-off-by: Michael Riesch --- drivers/phy/rockchip/phy-rockchip-inno-csidphy.c | 28 ++++++++++++++++++++= ++++ 1 file changed, 28 insertions(+) diff --git a/drivers/phy/rockchip/phy-rockchip-inno-csidphy.c b/drivers/phy= /rockchip/phy-rockchip-inno-csidphy.c index 6c4ddcd7e5de..c79fb53d8ee5 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-csidphy.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-csidphy.c @@ -30,6 +30,8 @@ #define RK3568_GRF_VI_CON0 0x0340 #define RK3568_GRF_VI_CON1 0x0344 =20 +#define RK3588_CSIDPHY_GRF_CON0 0x0000 + /* PHY */ #define CSIDPHY_CTRL_LANE_ENABLE 0x00 #define CSIDPHY_CTRL_LANE_ENABLE_CK BIT(6) @@ -117,6 +119,12 @@ static const struct dphy_reg rk3568_grf_dphy_regs[] = =3D { [GRF_DPHY_CSIPHY_CLKLANE_EN] =3D PHY_REG(RK3568_GRF_VI_CON0, 1, 8), }; =20 +static const struct dphy_reg rk3588_grf_dphy_regs[] =3D { + [GRF_DPHY_CSIPHY_FORCERXMODE] =3D PHY_REG(RK3588_CSIDPHY_GRF_CON0, 4, 0), + [GRF_DPHY_CSIPHY_DATALANE_EN] =3D PHY_REG(RK3588_CSIDPHY_GRF_CON0, 4, 4), + [GRF_DPHY_CSIPHY_CLKLANE_EN] =3D PHY_REG(RK3588_CSIDPHY_GRF_CON0, 1, 8), +}; + struct hsfreq_range { u32 range_h; u8 cfg_bit; @@ -183,6 +191,11 @@ static const char *const rk3368_reset_names[] =3D { "apb" }; =20 +static const char *const rk3588_reset_names[] =3D { + "apb", + "phy" +}; + static void rockchip_inno_csidphy_ths_settle(struct rockchip_inno_csidphy = *priv, int hsfreq, int offset) { @@ -390,6 +403,17 @@ static const struct dphy_drv_data rk3568_mipidphy_drv_= data =3D { .resets_num =3D ARRAY_SIZE(rk3368_reset_names), }; =20 +static const struct dphy_drv_data rk3588_mipidphy_drv_data =3D { + .pwrctl_offset =3D -1, + .ths_settle_offset =3D RK3568_CSIDPHY_CLK_WR_THS_SETTLE, + .calib_offset =3D RK3568_CSIDPHY_CLK_CALIB_EN, + .hsfreq_ranges =3D rk1808_mipidphy_hsfreq_ranges, + .num_hsfreq_ranges =3D ARRAY_SIZE(rk1808_mipidphy_hsfreq_ranges), + .grf_regs =3D rk3588_grf_dphy_regs, + .resets =3D rk3588_reset_names, + .resets_num =3D ARRAY_SIZE(rk3588_reset_names), +}; + static const struct of_device_id rockchip_inno_csidphy_match_id[] =3D { { .compatible =3D "rockchip,px30-csi-dphy", @@ -411,6 +435,10 @@ static const struct of_device_id rockchip_inno_csidphy= _match_id[] =3D { .compatible =3D "rockchip,rk3568-csi-dphy", .data =3D &rk3568_mipidphy_drv_data, }, + { + .compatible =3D "rockchip,rk3588-csi-dphy", + .data =3D &rk3588_mipidphy_drv_data, + }, {} }; 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Mon, 18 Aug 2025 23:14:33 +0000 (UTC) From: Michael Riesch via B4 Relay Date: Tue, 19 Aug 2025 01:00:41 +0200 Subject: [PATCH v2 7/7] arm64: dts: rockchip: add mipi csi-2 dphy nodes to rk3588 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250616-rk3588-csi-dphy-v2-7-7a94f079b712@collabora.com> References: <20250616-rk3588-csi-dphy-v2-0-7a94f079b712@collabora.com> In-Reply-To: <20250616-rk3588-csi-dphy-v2-0-7a94f079b712@collabora.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Vinod Koul , Kishon Vijay Abraham I , Philipp Zabel , Kever Yang , Jagan Teki , Sebastian Reichel , Diederik de Haas , Neil Armstrong , Heiko Stuebner , Collabora Kernel Team Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, Michael Riesch X-Mailer: b4 0.12.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1755558041; l=1931; i=michael.riesch@collabora.com; s=20250410; h=from:subject:message-id; bh=6HJuYpXttybyTSrCNqhc1jbMr3cQPoLfqzHZNqsOuiw=; b=dThNvGwBMkmXKG+AhU7ciXQUVnux6gzGpI59Dpjh9kbcJ23Uwp6Ns9rovVkFIyVg0Wg+AHiVa N4K8WTKXYigDlb4fcIfOsq0rVvxWv5H0RKfv/AvzcRYzo7LShqpnc+N X-Developer-Key: i=michael.riesch@collabora.com; a=ed25519; pk=+MWX1fffLFZtTPG/I6XdYm/+OSvpRE8D9evQaWbiN04= X-Endpoint-Received: by B4 Relay for michael.riesch@collabora.com/20250410 with auth_id=371 X-Original-From: Michael Riesch Reply-To: michael.riesch@collabora.com From: Michael Riesch The Rockchip RK3588 features two MIPI CSI-2 DPHYs. Add the device tree nodes for them. Signed-off-by: Michael Riesch --- arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 33 +++++++++++++++++++++++= ++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boo= t/dts/rockchip/rk3588-base.dtsi index 70f03e68ba55..eedf93247e9c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -621,6 +621,16 @@ php_grf: syscon@fd5b0000 { reg =3D <0x0 0xfd5b0000 0x0 0x1000>; }; =20 + csidphy0_grf: syscon@fd5b4000 { + compatible =3D "rockchip,rk3588-csidphy-grf", "syscon"; + reg =3D <0x0 0xfd5b4000 0x0 0x1000>; + }; + + csidphy1_grf: syscon@fd5b5000 { + compatible =3D "rockchip,rk3588-csidphy-grf", "syscon"; + reg =3D <0x0 0xfd5b5000 0x0 0x1000>; + }; + pipe_phy0_grf: syscon@fd5bc000 { compatible =3D "rockchip,rk3588-pipe-phy-grf", "syscon"; reg =3D <0x0 0xfd5bc000 0x0 0x100>; @@ -3052,6 +3062,29 @@ mipidcphy1: phy@fedb0000 { <&cru SRST_S_MIPI_DCPHY1>; reset-names =3D "m_phy", "apb", "grf", "s_phy"; #phy-cells =3D <1>; + }; + + csi_dphy0: phy@fedc0000 { + compatible =3D "rockchip,rk3588-csi-dphy"; + reg =3D <0x0 0xfedc0000 0x0 0x8000>; + clocks =3D <&cru PCLK_CSIPHY0>; + clock-names =3D "pclk"; + #phy-cells =3D <0>; + resets =3D <&cru SRST_P_CSIPHY0>, <&cru SRST_CSIPHY0>; + reset-names =3D "apb", "phy"; + rockchip,grf =3D <&csidphy0_grf>; + status =3D "disabled"; + }; + + csi_dphy1: phy@fedc8000 { + compatible =3D "rockchip,rk3588-csi-dphy"; + reg =3D <0x0 0xfedc8000 0x0 0x8000>; + clocks =3D <&cru PCLK_CSIPHY1>; + clock-names =3D "pclk"; + #phy-cells =3D <0>; + resets =3D <&cru SRST_P_CSIPHY1>, <&cru SRST_CSIPHY1>; + reset-names =3D "apb", "phy"; + rockchip,grf =3D <&csidphy1_grf>; status =3D "disabled"; }; =20 --=20 2.39.5