From nobody Fri Oct 10 09:53:04 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B8AB4295520; Tue, 17 Jun 2025 09:07:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750151247; cv=none; b=DjDDt73sR4pggYeAeSDg/vTUVa2OwRjL1tyrscnTOyFm0MvGOyokrOPdEizJUPGsQk7ciD+TQrPrhN7QPz5IBYAI6pec4pYHU8sEL92TSk2qZIGA+hyOixGFC9pp15IZ+LXq3ubw/KifzIslWewJ2J1BBlEe4Pw+2en4ulKdHzE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750151247; c=relaxed/simple; bh=EDT1SOtdCggXefr4ykTCKllYEE6DBQiIGJowVV/i1Nw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=j5+CE4FxypwP5KYnRC+VvIaSDPnB62N2dILLE9fElwqfnidBZUSreXX+/wjTQhPP6UXS5svWp/IfGgPXZw2wIhSYL9W4K7aSFrkAcr+Z0MLbQGKuhjGCA63fCzJR9OazrRL/uZjhRT5WdAMp/E35+kGmXQb8k1tTbmYErrjJ32E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=pZkKdaf7; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="pZkKdaf7" Received: by smtp.kernel.org (Postfix) with ESMTPS id 59AE0C4CEEE; Tue, 17 Jun 2025 09:07:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1750151247; bh=EDT1SOtdCggXefr4ykTCKllYEE6DBQiIGJowVV/i1Nw=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=pZkKdaf7pPUdj89QYS+SN6yvqZQ3rGVid+caRFWjc7ZEM51z05mA6RWxJuqKL7Wz8 WkU/qB+pAEUhj4ueuhnjX36cx48963ZxRIOu9sxcNZjK0mC100JWEjhLV8UvccQF5K t41CIFTW4/jrpnj2P9jpFMMjM5PGJjT0xErbGeszaTjNMh0arKHseL9EvVY3GNhlFe sh4RJVolSAivZWJim5KrMAKJ1XSRUc3QTEoEwnqrGZaVXTIUzALoULkromF8jShgpa 9cY0/VOu/F0rawJj6kipvThP0K71FL+4J7+oXl3Rh8XfVUo32QBtHr/Y1+Y+JrClbY nv9x3byRIlSmw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4A79FC71136; Tue, 17 Jun 2025 09:07:27 +0000 (UTC) From: Michael Riesch via B4 Relay Date: Tue, 17 Jun 2025 10:54:42 +0200 Subject: [PATCH 1/5] dt-bindings: soc: rockchip: add rk3588 csidphy grf syscon Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250616-rk3588-csi-dphy-v1-1-84eb3b2a736c@collabora.com> References: <20250616-rk3588-csi-dphy-v1-0-84eb3b2a736c@collabora.com> In-Reply-To: <20250616-rk3588-csi-dphy-v1-0-84eb3b2a736c@collabora.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Vinod Koul , Kishon Vijay Abraham I , Philipp Zabel , Jagan Teki , Sebastian Reichel , Collabora Kernel Team Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, Michael Riesch X-Mailer: b4 0.12.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1750150493; l=880; i=michael.riesch@collabora.com; s=20250410; h=from:subject:message-id; bh=BZKRYDbmVz180lFPXWMOf8qDnvWsNoqRKtTqFJ29J6s=; b=KDsB8HxjAL81/CjJwei3iWocX3CiIBzGjbMYboyngZq1YbWERYJzG0QE7dxwhHn03FwCTHPZK qyKSOs80bmIDLHBOQdfIVqaaXjrMkYhxox9EA5jsA++LIKXClDbf5ru X-Developer-Key: i=michael.riesch@collabora.com; a=ed25519; pk=+MWX1fffLFZtTPG/I6XdYm/+OSvpRE8D9evQaWbiN04= X-Endpoint-Received: by B4 Relay for michael.riesch@collabora.com/20250410 with auth_id=371 X-Original-From: Michael Riesch Reply-To: michael.riesch@collabora.com From: Michael Riesch Add CSIDPHY GRF syscon compatible for the Rockchip RK3588. Signed-off-by: Michael Riesch Acked-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/soc/rockchip/grf.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Docu= mentation/devicetree/bindings/soc/rockchip/grf.yaml index ccdcc889ba8e..3a1035fbd8dc 100644 --- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml +++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml @@ -47,6 +47,7 @@ properties: - rockchip,rk3576-vop-grf - rockchip,rk3588-bigcore0-grf - rockchip,rk3588-bigcore1-grf + - rockchip,rk3588-csidphy-grf - rockchip,rk3588-dcphy-grf - rockchip,rk3588-hdptxphy-grf - rockchip,rk3588-ioc --=20 2.39.5 From nobody Fri Oct 10 09:53:04 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C2C47295528; Tue, 17 Jun 2025 09:07:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750151247; cv=none; b=fG0yOHLRy0B/K5xdJ48AGlBNxnVnFf0EadZyZGpbVzbZfNIdooDMFAufGSCxYc4hJeFF7+PWvW993uNBsjYPtXcSSlFk/mSFnTX5tdGJCYD1DlfliKLoO7pa0jgchM5JMzm28/lqE2+FenYQEFuuna6agH/NgtxnjPdA0xbZNkU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750151247; c=relaxed/simple; bh=LVht+9sV1xKC2IxkJr8nOMxbiinkz8Wotsr17dJSVnY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=YcDFmtmxF/Nyozv3VRKaJlHZkqA2A5pp22pBpGZyaTAANS92Xc9PmHC5gw1jIbFAhdbyd4ihdvx5VRj0BzmOBceKL/imjOFpbWb0Xzd0vkLpEh/zdtFzaJkfHFrLBrvEzDqNzR6wZitFHU6e+BI2rZ1AM+rjzJGmF4cEAzBvBEw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ZiJ643pW; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ZiJ643pW" Received: by smtp.kernel.org (Postfix) with ESMTPS id 6A278C4CEF4; Tue, 17 Jun 2025 09:07:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1750151247; bh=LVht+9sV1xKC2IxkJr8nOMxbiinkz8Wotsr17dJSVnY=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=ZiJ643pWiECMkR4MlVHS3tyl/tyLl4SqhSFwISTvAVoEu3JdQ1oYlBlC9hyRkuE0D 0XjTVwjdHLHic4zB2ZniOX6tnkjI9dWw+WERPDzFmjBScn96AiSqY1kdxa/IXMy5GI tR/IQWFxuvNgPE/cK75DD1/UErcS2zH5n5h7xe6Z1lRfPQ06TGlfMNyMkU+5uQJsU4 WBOx/s6HdEJ3DNP7Pdm+R4oF48hUmJ275RSvACpD/UQ5LEUm9eKqCEFd/RCbxNja1f 9IgR0Oo8t4/kF07HafW640oIG7OtFcSwOjpqquDyyihonS3vzniMwB6qBa0mhG0Bwi GpUMTkoLkmnHw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5A05BC7115A; Tue, 17 Jun 2025 09:07:27 +0000 (UTC) From: Michael Riesch via B4 Relay Date: Tue, 17 Jun 2025 10:54:43 +0200 Subject: [PATCH 2/5] dt-bindings: phy: rockchip-inno-csi-dphy: add rk3588 variant Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250616-rk3588-csi-dphy-v1-2-84eb3b2a736c@collabora.com> References: <20250616-rk3588-csi-dphy-v1-0-84eb3b2a736c@collabora.com> In-Reply-To: <20250616-rk3588-csi-dphy-v1-0-84eb3b2a736c@collabora.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Vinod Koul , Kishon Vijay Abraham I , Philipp Zabel , Jagan Teki , Sebastian Reichel , Collabora Kernel Team Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, Michael Riesch X-Mailer: b4 0.12.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1750150493; l=2895; i=michael.riesch@collabora.com; s=20250410; h=from:subject:message-id; bh=fLuP6l4pge2OTjFyNlRHCdovdOVbah0f1mpcQE7Vn4A=; b=iM0cTXpH/DwAzcZlyAonVYAbPzQZPRRtV6DKJjpdidZlu4LHinT+I+CdhJ85/XpAL9xC1JBDF /7tnNDJymhMAFmqdlEvoCE6njPm3L1Br/wa3FmtQfRJOviM+mrtKQlx X-Developer-Key: i=michael.riesch@collabora.com; a=ed25519; pk=+MWX1fffLFZtTPG/I6XdYm/+OSvpRE8D9evQaWbiN04= X-Endpoint-Received: by B4 Relay for michael.riesch@collabora.com/20250410 with auth_id=371 X-Original-From: Michael Riesch Reply-To: michael.riesch@collabora.com From: Michael Riesch The Rockchip RK3588 variant of the CSI-2 DPHY features two reset lines. Add the variant and allow for the additional reset. Signed-off-by: Michael Riesch --- .../bindings/phy/rockchip-inno-csi-dphy.yaml | 60 ++++++++++++++++++= ++-- 1 file changed, 55 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.y= aml b/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml index 5ac994b3c0aa..6755738b13ee 100644 --- a/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml +++ b/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml @@ -21,6 +21,7 @@ properties: - rockchip,rk3326-csi-dphy - rockchip,rk3368-csi-dphy - rockchip,rk3568-csi-dphy + - rockchip,rk3588-csi-dphy =20 reg: maxItems: 1 @@ -39,18 +40,49 @@ properties: maxItems: 1 =20 resets: - items: - - description: exclusive PHY reset line + minItems: 1 + maxItems: 2 =20 reset-names: - items: - - const: apb + minItems: 1 + maxItems: 2 =20 rockchip,grf: $ref: /schemas/types.yaml#/definitions/phandle description: Some additional phy settings are access through GRF regs. =20 +allOf: + - if: + properties: + compatible: + contains: + enum: + - rockchip,px30-csi-dphy + - rockchip,rk1808-csi-dphy + - rockchip,rk3326-csi-dphy + - rockchip,rk3368-csi-dphy + - rockchip,rk3568-csi-dphy + then: + properties: + resets: + items: + - description: exclusive PHY reset line + + reset-names: + items: + - const: apb + + required: + - reset-names + else: + properties: + resets: + minItems: 2 + + reset-names: + minItems: 2 + required: - compatible - reg @@ -59,7 +91,6 @@ required: - '#phy-cells' - power-domains - resets - - reset-names - rockchip,grf =20 additionalProperties: false @@ -78,3 +109,22 @@ examples: reset-names =3D "apb"; rockchip,grf =3D <&grf>; }; + - | + #include + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + csi_dphy0: phy@fedc0000 { + compatible =3D "rockchip,rk3588-csi-dphy"; + reg =3D <0x0 0xfedc0000 0x0 0x8000>; + clocks =3D <&cru PCLK_CSIPHY0>; + clock-names =3D "pclk"; + #phy-cells =3D <0>; + resets =3D <&cru SRST_CSIPHY0>, <&cru SRST_P_CSIPHY0>; + rockchip,grf =3D <&csidphy0_grf>; + status =3D "disabled"; + }; + }; --=20 2.39.5 From nobody Fri Oct 10 09:53:04 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C2BDE295525; Tue, 17 Jun 2025 09:07:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750151247; cv=none; b=BFDgSOk1YZvN4tcGFzSlgByLG73hfgLIDCYbZ7nEi6+GhLB3ltEiiJjZt9CG99WWgYP9MbPzHuYXgvmkHz0We0xHc/EEz9ZxJliuzmtUgnuCYTW2YRbq+Fk8skefbL7eDw+FD5BjRAPCvIVRYa2XONmIgQYloKXx6xcvbn1vG7w= ARC-Message-Signature: i=1; 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b=QNHgDxh5HOEE0cpViNxl4/KsDAEqHUWNtltpPz4qNJ43oaOrKzrfEBC1ePCYPqi6N 4fzsPTyCWcK9I1xPBmLHQ6bayYH2AGrVnZ/MYMWNj8PZoq0yrsZ4HosBWQ7i0YgpuB 1BpMnFwm5FPvFZvCjbILKhiDL175t4C1sWmBAbd11aWU4mfqrrBHORzHQYtcyOFJAB zpsrh+YZXOcwklz3XthHfU8oeQD4HWc6ZV+HjzhjXy3hbxhAvU+GvWw4Ndh548txlV LYuv4lvRXx1pV3JhHdS81N6mVbybCe7DlQd3Xi56wbrmn5bIJBTiqajZVQtapCvSl6 lh4dT00brhEBQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 67F74C71155; Tue, 17 Jun 2025 09:07:27 +0000 (UTC) From: Michael Riesch via B4 Relay Date: Tue, 17 Jun 2025 10:54:44 +0200 Subject: [PATCH 3/5] phy: rockchip: phy-rockchip-inno-csidphy: allow writes to grf register 0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250616-rk3588-csi-dphy-v1-3-84eb3b2a736c@collabora.com> References: <20250616-rk3588-csi-dphy-v1-0-84eb3b2a736c@collabora.com> In-Reply-To: <20250616-rk3588-csi-dphy-v1-0-84eb3b2a736c@collabora.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Vinod Koul , Kishon Vijay Abraham I , Philipp Zabel , Jagan Teki , Sebastian Reichel , Collabora Kernel Team Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, Michael Riesch X-Mailer: b4 0.12.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1750150493; l=1581; i=michael.riesch@collabora.com; s=20250410; h=from:subject:message-id; bh=aJtpf6aQN4QLph0ogcfZ1mD08/jLTu4SOK+/3Mu671g=; b=drrf3+HeksVsYIPQ4fnsIhnaijJd8eMomUwXxWI2N4VbIJ2R95gmKEtFtWU8P6IjdaGMzoQxK W/+iCOohunKB6elFsuV74lb0DK+H3IULwG7/AvOkAxwHuw1DZoC7vPN X-Developer-Key: i=michael.riesch@collabora.com; a=ed25519; pk=+MWX1fffLFZtTPG/I6XdYm/+OSvpRE8D9evQaWbiN04= X-Endpoint-Received: by B4 Relay for michael.riesch@collabora.com/20250410 with auth_id=371 X-Original-From: Michael Riesch Reply-To: michael.riesch@collabora.com From: Michael Riesch The driver for the Rockchip MIPI CSI-2 DPHY uses GRF register offset value 0 to sort out undefined registers. However, the RK3588 CSIDPHY GRF this offset is perfectly fine (in fact, register 0 is the only one in this register y file). Introduce a boolean variable to indicate valid registers and allow writes to register 0. Signed-off-by: Michael Riesch Reviewed-by: Neil Armstrong --- drivers/phy/rockchip/phy-rockchip-inno-csidphy.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-inno-csidphy.c b/drivers/phy= /rockchip/phy-rockchip-inno-csidphy.c index 2ab99e1d47eb..75533d071025 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-csidphy.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-csidphy.c @@ -87,10 +87,11 @@ struct dphy_reg { u32 offset; u32 mask; u32 shift; + u8 valid; }; =20 #define PHY_REG(_offset, _width, _shift) \ - { .offset =3D _offset, .mask =3D BIT(_width) - 1, .shift =3D _shift, } + { .offset =3D _offset, .mask =3D BIT(_width) - 1, .shift =3D _shift, .val= id =3D 1, } =20 static const struct dphy_reg rk1808_grf_dphy_regs[] =3D { [GRF_DPHY_CSIPHY_FORCERXMODE] =3D PHY_REG(RK1808_GRF_PD_VI_CON_OFFSET, 4,= 0), @@ -145,7 +146,7 @@ static inline void write_grf_reg(struct rockchip_inno_c= sidphy *priv, const struct dphy_drv_data *drv_data =3D priv->drv_data; const struct dphy_reg *reg =3D &drv_data->grf_regs[index]; =20 - if (reg->offset) + if (reg->valid) regmap_write(priv->grf, reg->offset, HIWORD_UPDATE(value, reg->mask, reg->shift)); } --=20 2.39.5 From nobody Fri Oct 10 09:53:04 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D466F29552A; Tue, 17 Jun 2025 09:07:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750151247; cv=none; b=EY1YXGhE5Wpn7qkxs6LfTGNZZI0tSbyf+QszFsK3gJixh6c++ho7oxCKtdneubnzI7r/m5WAOVIayGAsLLrpLzWI2VWNpcmvp3ywBE5rNmsUuMl/SpOG2ED3SGStA5y5qnDc/dXWNCDAQalHqqzrl0WbvqzG+KuKGRN5+ZWoQzo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750151247; c=relaxed/simple; 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Tue, 17 Jun 2025 09:07:27 +0000 (UTC) From: Michael Riesch via B4 Relay Date: Tue, 17 Jun 2025 10:54:45 +0200 Subject: [PATCH 4/5] phy: rockchip: phy-rockchip-inno-csidphy: add support for rk3588 variant Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250616-rk3588-csi-dphy-v1-4-84eb3b2a736c@collabora.com> References: <20250616-rk3588-csi-dphy-v1-0-84eb3b2a736c@collabora.com> In-Reply-To: <20250616-rk3588-csi-dphy-v1-0-84eb3b2a736c@collabora.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Vinod Koul , Kishon Vijay Abraham I , Philipp Zabel , Jagan Teki , Sebastian Reichel , Collabora Kernel Team Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, Michael Riesch X-Mailer: b4 0.12.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1750150493; l=2785; i=michael.riesch@collabora.com; s=20250410; h=from:subject:message-id; bh=wIvkTfx5p7asQqRE6ZowFTwrVX3fTKBqDPaE5VUrGmU=; b=WUajPaJyRXJCRO4z/Nr5IJPT1r7i6jSpEW5MfqDZyghW5BslEBXEeXgkw8ocDJ/cjV0k5YCaF IwbJL6eadG5A9FtESWu4ZkEHmOs6FBS7pB33AHWXWk914T8WAf+PxMY X-Developer-Key: i=michael.riesch@collabora.com; a=ed25519; pk=+MWX1fffLFZtTPG/I6XdYm/+OSvpRE8D9evQaWbiN04= X-Endpoint-Received: by B4 Relay for michael.riesch@collabora.com/20250410 with auth_id=371 X-Original-From: Michael Riesch Reply-To: michael.riesch@collabora.com From: Michael Riesch The Rockchip RK3588 MIPI CSI-2 DPHY can be supported using the existing phy-rockchip-inno-csidphy driver, the notable differences being - the control bits in the GRF - the additional reset line Add support for this variant. Signed-off-by: Michael Riesch --- drivers/phy/rockchip/phy-rockchip-inno-csidphy.c | 23 ++++++++++++++++++++= ++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/drivers/phy/rockchip/phy-rockchip-inno-csidphy.c b/drivers/phy= /rockchip/phy-rockchip-inno-csidphy.c index 75533d071025..0840be668bfd 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-csidphy.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-csidphy.c @@ -30,6 +30,8 @@ #define RK3568_GRF_VI_CON0 0x0340 #define RK3568_GRF_VI_CON1 0x0344 =20 +#define RK3588_CSIDPHY_GRF_CON0 0x0000 + /* PHY */ #define CSIDPHY_CTRL_LANE_ENABLE 0x00 #define CSIDPHY_CTRL_LANE_ENABLE_CK BIT(6) @@ -115,6 +117,12 @@ static const struct dphy_reg rk3568_grf_dphy_regs[] = =3D { [GRF_DPHY_CSIPHY_CLKLANE_EN] =3D PHY_REG(RK3568_GRF_VI_CON0, 1, 8), }; =20 +static const struct dphy_reg rk3588_grf_dphy_regs[] =3D { + [GRF_DPHY_CSIPHY_FORCERXMODE] =3D PHY_REG(RK3588_CSIDPHY_GRF_CON0, 4, 0), + [GRF_DPHY_CSIPHY_DATALANE_EN] =3D PHY_REG(RK3588_CSIDPHY_GRF_CON0, 4, 4), + [GRF_DPHY_CSIPHY_CLKLANE_EN] =3D PHY_REG(RK3588_CSIDPHY_GRF_CON0, 1, 8), +}; + struct hsfreq_range { u32 range_h; u8 cfg_bit; @@ -373,6 +381,15 @@ static const struct dphy_drv_data rk3568_mipidphy_drv_= data =3D { .grf_regs =3D rk3568_grf_dphy_regs, }; =20 +static const struct dphy_drv_data rk3588_mipidphy_drv_data =3D { + .pwrctl_offset =3D -1, + .ths_settle_offset =3D RK3568_CSIDPHY_CLK_WR_THS_SETTLE, + .calib_offset =3D RK3568_CSIDPHY_CLK_CALIB_EN, + .hsfreq_ranges =3D rk1808_mipidphy_hsfreq_ranges, + .num_hsfreq_ranges =3D ARRAY_SIZE(rk1808_mipidphy_hsfreq_ranges), + .grf_regs =3D rk3588_grf_dphy_regs, +}; + static const struct of_device_id rockchip_inno_csidphy_match_id[] =3D { { .compatible =3D "rockchip,px30-csi-dphy", @@ -394,6 +411,10 @@ static const struct of_device_id rockchip_inno_csidphy= _match_id[] =3D { .compatible =3D "rockchip,rk3568-csi-dphy", .data =3D &rk3568_mipidphy_drv_data, }, + { + .compatible =3D "rockchip,rk3588-csi-dphy", + .data =3D &rk3588_mipidphy_drv_data, + }, {} }; MODULE_DEVICE_TABLE(of, rockchip_inno_csidphy_match_id); @@ -435,7 +456,7 @@ static int rockchip_inno_csidphy_probe(struct platform_= device *pdev) return PTR_ERR(priv->pclk); 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Tue, 17 Jun 2025 09:07:27 +0000 (UTC) From: Michael Riesch via B4 Relay Date: Tue, 17 Jun 2025 10:54:46 +0200 Subject: [PATCH 5/5] arm64: dts: rockchip: add mipi csi-2 dphy nodes to rk3588 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250616-rk3588-csi-dphy-v1-5-84eb3b2a736c@collabora.com> References: <20250616-rk3588-csi-dphy-v1-0-84eb3b2a736c@collabora.com> In-Reply-To: <20250616-rk3588-csi-dphy-v1-0-84eb3b2a736c@collabora.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Vinod Koul , Kishon Vijay Abraham I , Philipp Zabel , Jagan Teki , Sebastian Reichel , Collabora Kernel Team Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, Michael Riesch X-Mailer: b4 0.12.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1750150493; l=1867; i=michael.riesch@collabora.com; s=20250410; h=from:subject:message-id; bh=qrX7R9Yf+higl2wbSf3x1h05wV3AtHIap5SggDm1ypA=; b=c84nks+JEIFvKM2PQXYe5Sigfe8rKm+GsUo6dxEijt2RPl2ZO4XAEDjgHV/Lapw/2TX710uRl gb9OUZeBuxgCbK95HJRW0PI8pg2A3oRvDAL8d5h81ksM11iGvCrd4Gi X-Developer-Key: i=michael.riesch@collabora.com; a=ed25519; pk=+MWX1fffLFZtTPG/I6XdYm/+OSvpRE8D9evQaWbiN04= X-Endpoint-Received: by B4 Relay for michael.riesch@collabora.com/20250410 with auth_id=371 X-Original-From: Michael Riesch Reply-To: michael.riesch@collabora.com From: Michael Riesch The Rockchip RK3588 features two MIPI CSI-2 DPHYs. Add the device tree nodes for them. Signed-off-by: Michael Riesch --- arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 31 +++++++++++++++++++++++= ++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boo= t/dts/rockchip/rk3588-base.dtsi index 70f03e68ba55..6a4ee0247fcf 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -621,6 +621,16 @@ php_grf: syscon@fd5b0000 { reg =3D <0x0 0xfd5b0000 0x0 0x1000>; }; =20 + csidphy0_grf: syscon@fd5b4000 { + compatible =3D "rockchip,rk3588-csidphy-grf", "syscon"; + reg =3D <0x0 0xfd5b4000 0x0 0x1000>; + }; + + csidphy1_grf: syscon@fd5b5000 { + compatible =3D "rockchip,rk3588-csidphy-grf", "syscon"; + reg =3D <0x0 0xfd5b5000 0x0 0x1000>; + }; + pipe_phy0_grf: syscon@fd5bc000 { compatible =3D "rockchip,rk3588-pipe-phy-grf", "syscon"; reg =3D <0x0 0xfd5bc000 0x0 0x100>; @@ -3052,6 +3062,27 @@ mipidcphy1: phy@fedb0000 { <&cru SRST_S_MIPI_DCPHY1>; reset-names =3D "m_phy", "apb", "grf", "s_phy"; #phy-cells =3D <1>; + }; + + csi_dphy0: phy@fedc0000 { + compatible =3D "rockchip,rk3588-csi-dphy"; + reg =3D <0x0 0xfedc0000 0x0 0x8000>; + clocks =3D <&cru PCLK_CSIPHY0>; + clock-names =3D "pclk"; + #phy-cells =3D <0>; + resets =3D <&cru SRST_CSIPHY0>, <&cru SRST_P_CSIPHY0>; + rockchip,grf =3D <&csidphy0_grf>; + status =3D "disabled"; + }; + + csi_dphy1: phy@fedc8000 { + compatible =3D "rockchip,rk3588-csi-dphy"; + reg =3D <0x0 0xfedc8000 0x0 0x8000>; + clocks =3D <&cru PCLK_CSIPHY1>; + clock-names =3D "pclk"; + #phy-cells =3D <0>; + resets =3D <&cru SRST_CSIPHY1>, <&cru SRST_P_CSIPHY1>; + rockchip,grf =3D <&csidphy1_grf>; status =3D "disabled"; }; =20 --=20 2.39.5