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[175.159.121.134]) by smtp.googlemail.com with ESMTPSA id d9443c01a7336-2365deb2cedsm49932455ad.163.2025.06.15.18.32.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 15 Jun 2025 18:32:16 -0700 (PDT) From: Nick Chan Date: Mon, 16 Jun 2025 09:31:50 +0800 Subject: [PATCH RESEND v7 01/21] dt-bindings: arm: pmu: Add Apple A7-A11 SoC CPU PMU compatibles Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250616-apple-cpmu-v7-1-df2778a44d5c@gmail.com> References: <20250616-apple-cpmu-v7-0-df2778a44d5c@gmail.com> In-Reply-To: <20250616-apple-cpmu-v7-0-df2778a44d5c@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Sven Peter Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan , Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1102; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=nvc6B3SNJrX+OFSnYkWwiXKVem6neRj112hzdXP5HLQ=; b=owEBbQKS/ZANAwAKAQHKCLemxQgkAcsmYgBoT3QWWYtTwzjULiP8DN/cykkj8vIJnCQuzptdA wB0U7qCg2eJAjMEAAEKAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCaE90FgAKCRABygi3psUI JKGMD/wNuXF+G2au4+kmN+zz5CA9eusCR5mJrXaUgqBwXLIAhdK1VbIPFbzNq8aIhWZNaIR2LJ1 Cs7ZBp621+xZcQR28XuzEaKw7Ox0dGiPCJXzly8Wf2MJa8HJ3jqM6Ire1VHY9t2OZy9ABQm+v7Q 4k7lFtb08JD0zVxirPai4hCRMGNYw/xwqLaT8TOJGHty1h8Ey8pilXqZC4A4ZXT2MFSNZYETAqS 8y78dzOqZft8374UVUNYIo1goOda1I5qhMzQREEeAb1C3IcQTGc8qJ+ZL8VJZQ4L/rGXp0Y3Q0a v75LTeZwMSLRfQk+vQUZ22ZTGzplind+KoZPBLKx2G4qen8Sh0uOa5hz92Lie7jGxWMROhS5IpS kCiHsWa+OT76WPKMPNxau0di3gCWcASaLC7fp8V6m6kM+9nP3ijUs3CoKLELyWtiXMDZZR9VmpZ NNOY86Rg71RRzf6xAVzRoz1iPNu8zckEUitVsqcn1OemQrqV8NSXWtSj+h79agd4VEcBWUS5wpc m5hfFlJX08GpGy+06Gg6xiPFWEb0VRakWOfOKI+Oh6B1SfjKLxUCisRT5RwLuHbflcW6j6deRoz QguGWcRE0QqHpMhNsHo8wBbibJ/bWe+HT3vxq6nrl3LTIjeTc9d5PZmHNzV4bxy7YLuVMGGjV1w s2EAD/cmCvA5xeA== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 Document the compatibles for Apple A7-A11 SoC CPU PMU. Acked-by: Krzysztof Kozlowski Signed-off-by: Nick Chan --- Documentation/devicetree/bindings/arm/pmu.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/pmu.yaml b/Documentation= /devicetree/bindings/arm/pmu.yaml index 295963a3cae799a54560557137dd6b3cf4bd00f9..3726e1b78c42f150cf1dc68a6b3= aa3541517c311 100644 --- a/Documentation/devicetree/bindings/arm/pmu.yaml +++ b/Documentation/devicetree/bindings/arm/pmu.yaml @@ -22,8 +22,14 @@ properties: - apm,potenza-pmu - apple,avalanche-pmu - apple,blizzard-pmu + - apple,cyclone-pmu - apple,firestorm-pmu + - apple,fusion-pmu - apple,icestorm-pmu + - apple,monsoon-pmu + - apple,mistral-pmu + - apple,twister-pmu + - apple,typhoon-pmu - arm,armv8-pmuv3 # Only for s/w models - arm,arm1136-pmu - arm,arm1176-pmu --=20 2.49.0 From nobody Fri Oct 10 04:02:06 2025 Received: from mail-pl1-f175.google.com (mail-pl1-f175.google.com [209.85.214.175]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AE0811AF4C1; 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Initialization is harmless in EL1 but it is still a weird thing to do. Signed-off-by: Nick Chan --- drivers/perf/apple_m1_cpu_pmu.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pm= u.c index df9a28ba69dcfad6f33a0d18b620276b910a36ca..b800da3f7f61ffa972fcab5f24b= 42127f2c55ac6 100644 --- a/drivers/perf/apple_m1_cpu_pmu.c +++ b/drivers/perf/apple_m1_cpu_pmu.c @@ -646,8 +646,10 @@ static int m1_pmu_init(struct arm_pmu *cpu_pmu, u32 fl= ags) cpu_pmu->reset =3D m1_pmu_reset; cpu_pmu->set_event_filter =3D m1_pmu_set_event_filter; =20 - cpu_pmu->map_pmuv3_event =3D m1_pmu_map_pmuv3_event; - m1_pmu_init_pmceid(cpu_pmu); + if (is_hyp_mode_available()) { + cpu_pmu->map_pmuv3_event =3D m1_pmu_map_pmuv3_event; + m1_pmu_init_pmceid(cpu_pmu); + } =20 bitmap_set(cpu_pmu->cntr_mask, 0, M1_PMU_NR_COUNTERS); cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =3D &m1_pmu_events_attr_gr= oup; --=20 2.49.0 From nobody Fri Oct 10 04:02:06 2025 Received: from mail-pl1-f179.google.com (mail-pl1-f179.google.com [209.85.214.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0AFB61EA7E1; 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[175.159.121.134]) by smtp.googlemail.com with ESMTPSA id d9443c01a7336-2365deb2cedsm49932455ad.163.2025.06.15.18.32.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 15 Jun 2025 18:32:23 -0700 (PDT) From: Nick Chan Date: Mon, 16 Jun 2025 09:31:52 +0800 Subject: [PATCH RESEND v7 03/21] drivers/perf: apple_m1: Support per-implementation event tables Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250616-apple-cpmu-v7-3-df2778a44d5c@gmail.com> References: <20250616-apple-cpmu-v7-0-df2778a44d5c@gmail.com> In-Reply-To: <20250616-apple-cpmu-v7-0-df2778a44d5c@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Sven Peter Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=5769; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=40iBkshuT7rxTV03RILkcUaTWGCgn/IFCgnsDvO8O/4=; b=owEBbQKS/ZANAwAKAQHKCLemxQgkAcsmYgBoT3QXahV7k8F70XGC8o8Vn+M6DTHkgzxaEC38d y4qcQliEBaJAjMEAAEKAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCaE90FwAKCRABygi3psUI JNO5EACIQXBLWxc0imgRlBPChuoQQfWnIM5VL5Ufyz0y4SiKP30ZAmXJdDNOWY/QUO67J7oSfyz JwUqWPx+W/Ms5iMRJdIPs4Aws2kNauZYofpLmodL7tF67e433vcP0zNGxLByA93inHyEvrEPc8A 8owL0c+ZNPSTKSawT+g/55lBdo5KfSxxu84rwHR0EhRiAcf3OZTf8o4CVC47hFEuChiYEGkZy8z Kpd4cEpncwN1JJBdoJBaB5KgfhWjohN1h6uDpNxbK+KI35loLMV8hFT/m3p4ankqa1+8hXnopsi 46Wd6PnIbOb9K57SntS1k/I/l5OgWvnu7ZXbH8IIGWeasGOxgaclXGloGUz8FW6E2L2u02ayWk/ c8z6UchZ4dUpz8hpKnsqshsJPXYUYmNjdBOUR3hfnaOW2q8E3ZxhYtLP0fnZiRykjI+O8WeIZSR AuQdLPdFRZ0/0t++kMAfzZ6mK+ZhjJ25E8+JZtxvcH2tj4kpxVHD78D/NcAYwtFQh++uj7r5GkU c82evqiWwsJkEyNJjVE1w1huqTWTZoyhIACriNJ8nHU37wUofPkC5Vc4OmNAVuXhequ4vFx77E6 PoEUhmCittodPDHqp1ssr10D7IbJtLf9ijvS7pnOzhcKsPhk/Je3Y62beFFOEulB/NhWQEGcXjx UZlF8ntNGkrUqcw== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 Use per-implementation event tables to allow supporting implementations with a different list of events and event affinities. Signed-off-by: Nick Chan --- drivers/perf/apple_m1_cpu_pmu.c | 65 +++++++++++++++++++++++++------------= ---- 1 file changed, 40 insertions(+), 25 deletions(-) diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pm= u.c index b800da3f7f61ffa972fcab5f24b42127f2c55ac6..c19a433ee6478876e4cf6667d7a= 85a193b6cb069 100644 --- a/drivers/perf/apple_m1_cpu_pmu.c +++ b/drivers/perf/apple_m1_cpu_pmu.c @@ -43,9 +43,6 @@ * moment, we don't really need to distinguish between the two because we * know next to nothing about the events themselves, and we already have * per cpu-type PMU abstractions. - * - * If we eventually find out that the events are different across - * implementations, we'll have to introduce per cpu-type tables. */ enum m1_pmu_events { M1_PMU_PERFCTR_RETIRE_UOP =3D 0x1, @@ -494,11 +491,12 @@ static void m1_pmu_write_counter(struct perf_event *e= vent, u64 value) isb(); } =20 -static int m1_pmu_get_event_idx(struct pmu_hw_events *cpuc, - struct perf_event *event) +static int apple_pmu_get_event_idx(struct pmu_hw_events *cpuc, + struct perf_event *event, + const u16 event_affinities[]) { unsigned long evtype =3D event->hw.config_base & M1_PMU_CFG_EVENT; - unsigned long affinity =3D m1_pmu_event_affinity[evtype]; + unsigned long affinity =3D event_affinities[evtype]; int idx; =20 /* @@ -517,6 +515,12 @@ static int m1_pmu_get_event_idx(struct pmu_hw_events *= cpuc, return -EAGAIN; } =20 +static int m1_pmu_get_event_idx(struct pmu_hw_events *cpuc, + struct perf_event *event) +{ + return apple_pmu_get_event_idx(cpuc, event, m1_pmu_event_affinity); +} + static void m1_pmu_clear_event_idx(struct pmu_hw_events *cpuc, struct perf_event *event) { @@ -544,7 +548,8 @@ static void m1_pmu_stop(struct arm_pmu *cpu_pmu) __m1_pmu_set_mode(PMCR0_IMODE_OFF); } =20 -static int m1_pmu_map_event(struct perf_event *event) +static int apple_pmu_map_event_47(struct perf_event *event, + const unsigned int (*perf_map)[]) { /* * Although the counters are 48bit wide, bit 47 is what @@ -552,18 +557,29 @@ static int m1_pmu_map_event(struct perf_event *event) * being 47bit wide to mimick the behaviour of the ARM PMU. */ event->hw.flags |=3D ARMPMU_EVT_47BIT; - return armpmu_map_event(event, &m1_pmu_perf_map, NULL, M1_PMU_CFG_EVENT); + return armpmu_map_event(event, perf_map, NULL, M1_PMU_CFG_EVENT); } =20 -static int m2_pmu_map_event(struct perf_event *event) +static int apple_pmu_map_event_63(struct perf_event *event, + const unsigned int (*perf_map)[]) { /* - * Same deal as the above, except that M2 has 64bit counters. + * Same deal as the above, except with 64bit counters. * Which, as far as we're concerned, actually means 63 bits. * Yes, this is getting awkward. */ event->hw.flags |=3D ARMPMU_EVT_63BIT; - return armpmu_map_event(event, &m1_pmu_perf_map, NULL, M1_PMU_CFG_EVENT); + return armpmu_map_event(event, perf_map, NULL, M1_PMU_CFG_EVENT); +} + +static int m1_pmu_map_event(struct perf_event *event) +{ + return apple_pmu_map_event_47(event, &m1_pmu_perf_map); +} + +static int m2_pmu_map_event(struct perf_event *event) +{ + return apple_pmu_map_event_63(event, &m1_pmu_perf_map); } =20 static int m1_pmu_map_pmuv3_event(unsigned int eventsel) @@ -624,25 +640,16 @@ static int m1_pmu_set_event_filter(struct hw_perf_eve= nt *event, return 0; } =20 -static int m1_pmu_init(struct arm_pmu *cpu_pmu, u32 flags) +static int apple_pmu_init(struct arm_pmu *cpu_pmu) { cpu_pmu->handle_irq =3D m1_pmu_handle_irq; cpu_pmu->enable =3D m1_pmu_enable_event; cpu_pmu->disable =3D m1_pmu_disable_event; cpu_pmu->read_counter =3D m1_pmu_read_counter; cpu_pmu->write_counter =3D m1_pmu_write_counter; - cpu_pmu->get_event_idx =3D m1_pmu_get_event_idx; cpu_pmu->clear_event_idx =3D m1_pmu_clear_event_idx; cpu_pmu->start =3D m1_pmu_start; cpu_pmu->stop =3D m1_pmu_stop; - - if (flags & ARMPMU_EVT_47BIT) - cpu_pmu->map_event =3D m1_pmu_map_event; - else if (flags & ARMPMU_EVT_63BIT) - cpu_pmu->map_event =3D m2_pmu_map_event; - else - return WARN_ON(-EINVAL); - cpu_pmu->reset =3D m1_pmu_reset; cpu_pmu->set_event_filter =3D m1_pmu_set_event_filter; =20 @@ -661,25 +668,33 @@ static int m1_pmu_init(struct arm_pmu *cpu_pmu, u32 f= lags) static int m1_pmu_ice_init(struct arm_pmu *cpu_pmu) { cpu_pmu->name =3D "apple_icestorm_pmu"; - return m1_pmu_init(cpu_pmu, ARMPMU_EVT_47BIT); + cpu_pmu->get_event_idx =3D m1_pmu_get_event_idx; + cpu_pmu->map_event =3D m1_pmu_map_event; + return apple_pmu_init(cpu_pmu); } =20 static int m1_pmu_fire_init(struct arm_pmu *cpu_pmu) { cpu_pmu->name =3D "apple_firestorm_pmu"; - return m1_pmu_init(cpu_pmu, ARMPMU_EVT_47BIT); + cpu_pmu->get_event_idx =3D m1_pmu_get_event_idx; + cpu_pmu->map_event =3D m1_pmu_map_event; + return apple_pmu_init(cpu_pmu); } =20 static int m2_pmu_avalanche_init(struct arm_pmu *cpu_pmu) { cpu_pmu->name =3D "apple_avalanche_pmu"; - return m1_pmu_init(cpu_pmu, ARMPMU_EVT_63BIT); + cpu_pmu->get_event_idx =3D m1_pmu_get_event_idx; + cpu_pmu->map_event =3D m2_pmu_map_event; + return apple_pmu_init(cpu_pmu); } =20 static int m2_pmu_blizzard_init(struct arm_pmu *cpu_pmu) { cpu_pmu->name =3D "apple_blizzard_pmu"; - return m1_pmu_init(cpu_pmu, ARMPMU_EVT_63BIT); + cpu_pmu->get_event_idx =3D m1_pmu_get_event_idx; + cpu_pmu->map_event =3D m2_pmu_map_event; + return apple_pmu_init(cpu_pmu); } =20 static const struct of_device_id m1_pmu_of_device_ids[] =3D { --=20 2.49.0 From nobody Fri Oct 10 04:02:06 2025 Received: from mail-pl1-f169.google.com (mail-pl1-f169.google.com [209.85.214.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5F21E1FAC4B; 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[175.159.121.134]) by smtp.googlemail.com with ESMTPSA id d9443c01a7336-2365deb2cedsm49932455ad.163.2025.06.15.18.32.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 15 Jun 2025 18:32:26 -0700 (PDT) From: Nick Chan Date: Mon, 16 Jun 2025 09:31:53 +0800 Subject: [PATCH RESEND v7 04/21] drivers/perf: apple_m1: Support a per-implementation number of counters Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250616-apple-cpmu-v7-4-df2778a44d5c@gmail.com> References: <20250616-apple-cpmu-v7-0-df2778a44d5c@gmail.com> In-Reply-To: <20250616-apple-cpmu-v7-0-df2778a44d5c@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Sven Peter Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=4845; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=92neIFKGScRdX0M24usDNCsl0ZJtczDZfCVErT5yl+Y=; b=owEBbQKS/ZANAwAKAQHKCLemxQgkAcsmYgBoT3QXkcb2egfyxEIUDDhCkP08355OURKO+riCz mGVquyf1LSJAjMEAAEKAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCaE90FwAKCRABygi3psUI JIbvD/0fEGJvjk8QbPrwi7DbwIJob5LLJWbkt6axymTyd0d2U6aBs7QJbhrRLqdB+TSXLy0mUmR /cLxARZvk+HMZEWe9ErZdd1miHtKVwRyoewo+QvQhVkU8slwKf4t+jUxSZdpGTewCApvNIQFZgR qOZjvS2314iZJnJ7tL2RwgiK89XvVSRSaI5o75mVDaUEXn0CEdOlXPyXFFTWjhXCTmPfZyiZw/U VKUjD8bNgGYowCN85EK3HdGQ6jWj32rBbks99Wi4xyMFebfOKyFN5AyS0YgJ33Urg+TdbJc/LSP CWFwJZSlYzru9tipcBlOndo52Mc6K7Uo4S7EzmRKo9ta9+z0rTDBLedyvWGIjFTtHr3uo3sYcAm AJ5JAMMLijtOUBHiQ2kq/HrSkK6BkIlqZn1UVX9YzjWC/bMhTbsTmp/eFqnfzzlKLwC/3CtZ+z3 v6tDX63k+wdbpDHBVlc6Oxp1/6dnbnuCACx4DJ1ol/DWkmqR/Pca51C4eWt34bJ8EoVmYqyPzkt Rf+L9d3vXFdTwa+eG6Wo9LVL4s30s2HmOQoDHSlK0y8W/RW5xJWCZys2+cgKGzOgaI/KxFxhIj1 Iz5APgsI2KRHDO9Qs2EiNFLQ9nZKEV1091KTxrEoGnU4PpFXalhxq8E6ps1LM2BNtUY4XZQ0iiO kunnM3Dis2MDhkw== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 Support a per-implementation number of counters to allow adding support for implementations with less counters. Signed-off-by: Nick Chan --- drivers/perf/apple_m1_cpu_pmu.c | 31 ++++++++++++++++++++----------- 1 file changed, 20 insertions(+), 11 deletions(-) diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pm= u.c index c19a433ee6478876e4cf6667d7a85a193b6cb069..35a34eca403384c4908c2bba2f8= 186ea854d63bf 100644 --- a/drivers/perf/apple_m1_cpu_pmu.c +++ b/drivers/perf/apple_m1_cpu_pmu.c @@ -20,6 +20,7 @@ #include =20 #define M1_PMU_NR_COUNTERS 10 +#define APPLE_PMU_MAX_NR_COUNTERS 10 =20 #define M1_PMU_CFG_EVENT GENMASK(7, 0) =20 @@ -459,7 +460,7 @@ static irqreturn_t m1_pmu_handle_irq(struct arm_pmu *cp= u_pmu) =20 regs =3D get_irq_regs(); =20 - for_each_set_bit(idx, cpu_pmu->cntr_mask, M1_PMU_NR_COUNTERS) { + for_each_set_bit(idx, cpu_pmu->cntr_mask, APPLE_PMU_MAX_NR_COUNTERS) { struct perf_event *event =3D cpuc->events[idx]; struct perf_sample_data data; =20 @@ -507,7 +508,7 @@ static int apple_pmu_get_event_idx(struct pmu_hw_events= *cpuc, * counting on the PMU at any given time, and by placing the * most constraining events first. */ - for_each_set_bit(idx, &affinity, M1_PMU_NR_COUNTERS) { + for_each_set_bit(idx, &affinity, APPLE_PMU_MAX_NR_COUNTERS) { if (!test_and_set_bit(idx, cpuc->used_mask)) return idx; } @@ -602,13 +603,13 @@ static void m1_pmu_init_pmceid(struct arm_pmu *pmu) } } =20 -static void m1_pmu_reset(void *info) +static void apple_pmu_reset(void *info, u32 counters) { int i; =20 __m1_pmu_set_mode(PMCR0_IMODE_OFF); =20 - for (i =3D 0; i < M1_PMU_NR_COUNTERS; i++) { + for (i =3D 0; i < counters; i++) { m1_pmu_disable_counter(i); m1_pmu_disable_counter_interrupt(i); m1_pmu_write_hw_counter(0, i); @@ -617,6 +618,11 @@ static void m1_pmu_reset(void *info) isb(); } =20 +static void m1_pmu_reset(void *info) +{ + apple_pmu_reset(info, M1_PMU_NR_COUNTERS); +} + static int m1_pmu_set_event_filter(struct hw_perf_event *event, struct perf_event_attr *attr) { @@ -640,7 +646,7 @@ static int m1_pmu_set_event_filter(struct hw_perf_event= *event, return 0; } =20 -static int apple_pmu_init(struct arm_pmu *cpu_pmu) +static int apple_pmu_init(struct arm_pmu *cpu_pmu, u32 counters) { cpu_pmu->handle_irq =3D m1_pmu_handle_irq; cpu_pmu->enable =3D m1_pmu_enable_event; @@ -650,7 +656,6 @@ static int apple_pmu_init(struct arm_pmu *cpu_pmu) cpu_pmu->clear_event_idx =3D m1_pmu_clear_event_idx; cpu_pmu->start =3D m1_pmu_start; cpu_pmu->stop =3D m1_pmu_stop; - cpu_pmu->reset =3D m1_pmu_reset; cpu_pmu->set_event_filter =3D m1_pmu_set_event_filter; =20 if (is_hyp_mode_available()) { @@ -658,7 +663,7 @@ static int apple_pmu_init(struct arm_pmu *cpu_pmu) m1_pmu_init_pmceid(cpu_pmu); } =20 - bitmap_set(cpu_pmu->cntr_mask, 0, M1_PMU_NR_COUNTERS); + bitmap_set(cpu_pmu->cntr_mask, 0, counters); cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =3D &m1_pmu_events_attr_gr= oup; cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =3D &m1_pmu_format_attr_g= roup; return 0; @@ -670,7 +675,8 @@ static int m1_pmu_ice_init(struct arm_pmu *cpu_pmu) cpu_pmu->name =3D "apple_icestorm_pmu"; cpu_pmu->get_event_idx =3D m1_pmu_get_event_idx; cpu_pmu->map_event =3D m1_pmu_map_event; - return apple_pmu_init(cpu_pmu); + cpu_pmu->reset =3D m1_pmu_reset; + return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); } =20 static int m1_pmu_fire_init(struct arm_pmu *cpu_pmu) @@ -678,7 +684,8 @@ static int m1_pmu_fire_init(struct arm_pmu *cpu_pmu) cpu_pmu->name =3D "apple_firestorm_pmu"; cpu_pmu->get_event_idx =3D m1_pmu_get_event_idx; cpu_pmu->map_event =3D m1_pmu_map_event; - return apple_pmu_init(cpu_pmu); + cpu_pmu->reset =3D m1_pmu_reset; + return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); } =20 static int m2_pmu_avalanche_init(struct arm_pmu *cpu_pmu) @@ -686,7 +693,8 @@ static int m2_pmu_avalanche_init(struct arm_pmu *cpu_pm= u) cpu_pmu->name =3D "apple_avalanche_pmu"; cpu_pmu->get_event_idx =3D m1_pmu_get_event_idx; cpu_pmu->map_event =3D m2_pmu_map_event; - return apple_pmu_init(cpu_pmu); + cpu_pmu->reset =3D m1_pmu_reset; + return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); } =20 static int m2_pmu_blizzard_init(struct arm_pmu *cpu_pmu) @@ -694,7 +702,8 @@ static int m2_pmu_blizzard_init(struct arm_pmu *cpu_pmu) cpu_pmu->name =3D "apple_blizzard_pmu"; cpu_pmu->get_event_idx =3D m1_pmu_get_event_idx; cpu_pmu->map_event =3D m2_pmu_map_event; - return apple_pmu_init(cpu_pmu); + cpu_pmu->reset =3D m1_pmu_reset; + return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); 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[175.159.121.134]) by smtp.googlemail.com with ESMTPSA id d9443c01a7336-2365deb2cedsm49932455ad.163.2025.06.15.18.32.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 15 Jun 2025 18:32:30 -0700 (PDT) From: Nick Chan Date: Mon, 16 Jun 2025 09:31:54 +0800 Subject: [PATCH RESEND v7 05/21] drivers/perf: apple_m1: Support configuring counters for 32-bit EL0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250616-apple-cpmu-v7-5-df2778a44d5c@gmail.com> References: <20250616-apple-cpmu-v7-0-df2778a44d5c@gmail.com> In-Reply-To: <20250616-apple-cpmu-v7-0-df2778a44d5c@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Sven Peter Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2122; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=4vsiGjbxOOsY3kUJRZG60u58GR8XjzbCD4n5XW1wFKA=; b=owEBbQKS/ZANAwAKAQHKCLemxQgkAcsmYgBoT3QXpl0G9A8y6Clm896pAqkSYfH2CNDTrdpBa 6NDMkfcay+JAjMEAAEKAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCaE90FwAKCRABygi3psUI JFJQD/9lj2VhihWbCDTG7QEYwecH/qMCAlVbYPTHDaCCsRIM/0V2cdwEPObj9l5MTiRZEBHn3XO 8EzB0wArSxElfGNXA06UML/X48GClRu7iJ85hcHhuIx16Va8AmRiivOG2aerFJtJeEPWt2QSy8z 9qZ89fT6D9reastcBEaUAK1fhzZShJFvC14d6oXF3+6vtv42eUNO6fuXa6kqkoJ2AnV7iZANrhw TwhduTT5F+LVZ+SRUtgeh8RDt3RY07TY/z9XskHku1dQ+1d4w/+3IqtyM1LpdoodMtTy8PB+bzw JjhluCWSaCEvRT+4YOXTaTEHLmZkwWeLbgvo198EVSeg1MGCjyWuf7WcbQ7Ml4f7eUvcEcpYNt8 6QOLDFMNiYWNZUBjjneIkjovBVves5XZaJtorPv180klZaJtw1uANhAayh0ZvtZYB4alYHigNjs dhGl5mhUuUrIwt+TRsj1dxMXI4w/FunF1Cn2C3Hu93iqTVRMCOGQyDkgI3jL1BYQMaU/PFKvCsi Injkb/kfVNODwy8gAEs4Cas6gJxsTY4XPVrVQyLWO7WvDS90GkHuHRqIrF4P1xqr+LLrWaLVgIj zf2+nFLaEEcMLy1R4gIlpLEtrVEBUBNkYmhXVez8l5zL2nyeLLFMeJ994BsTfdtyW6ukC6SByjl cwB4rQU7i8OYMTw== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 Add support for configuring counters for 32-bit EL0 to allow adding support for implementations with 32-bit EL0. For documentation purposes, also add the bitmask for configuring counters for 64-bit EL3. Signed-off-by: Nick Chan --- arch/arm64/include/asm/apple_m1_pmu.h | 3 +++ drivers/perf/apple_m1_cpu_pmu.c | 6 ++++++ 2 files changed, 9 insertions(+) diff --git a/arch/arm64/include/asm/apple_m1_pmu.h b/arch/arm64/include/asm= /apple_m1_pmu.h index 02e05d05851f739b985bf416f1aa3baeafd691dc..6e238043e0dc2360c4fd507dc6a= 0eb7e055d2d6f 100644 --- a/arch/arm64/include/asm/apple_m1_pmu.h +++ b/arch/arm64/include/asm/apple_m1_pmu.h @@ -38,8 +38,11 @@ =20 #define SYS_IMP_APL_PMCR1_EL1 sys_reg(3, 1, 15, 1, 0) #define SYS_IMP_APL_PMCR1_EL12 sys_reg(3, 1, 15, 7, 2) +#define PMCR1_COUNT_A32_EL0_0_7 GENMASK(7, 0) #define PMCR1_COUNT_A64_EL0_0_7 GENMASK(15, 8) #define PMCR1_COUNT_A64_EL1_0_7 GENMASK(23, 16) +#define PMCR1_COUNT_A64_EL3_0_7 GENMASK(31, 24) +#define PMCR1_COUNT_A32_EL0_8_9 GENMASK(33, 32) #define PMCR1_COUNT_A64_EL0_8_9 GENMASK(41, 40) #define PMCR1_COUNT_A64_EL1_8_9 GENMASK(49, 48) =20 diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pm= u.c index 35a34eca403384c4908c2bba2f8186ea854d63bf..6736909a7df672a08938a392d45= 0dc9b5b7bce9e 100644 --- a/drivers/perf/apple_m1_cpu_pmu.c +++ b/drivers/perf/apple_m1_cpu_pmu.c @@ -348,10 +348,16 @@ static void __m1_pmu_configure_event_filter(unsigned = int index, bool user, case 0 ... 7: user_bit =3D BIT(get_bit_offset(index, PMCR1_COUNT_A64_EL0_0_7)); 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[175.159.121.134]) by smtp.googlemail.com with ESMTPSA id d9443c01a7336-2365deb2cedsm49932455ad.163.2025.06.15.18.32.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 15 Jun 2025 18:32:33 -0700 (PDT) From: Nick Chan Date: Mon, 16 Jun 2025 09:31:55 +0800 Subject: [PATCH RESEND v7 06/21] drivers/perf: apple_m1: Support per-implementation PMU startup Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250616-apple-cpmu-v7-6-df2778a44d5c@gmail.com> References: <20250616-apple-cpmu-v7-0-df2778a44d5c@gmail.com> In-Reply-To: <20250616-apple-cpmu-v7-0-df2778a44d5c@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Sven Peter Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2178; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=EHqn1hF+O5cx1kCcX9b9emwg/l7WZgXjC8JEUTZtaNY=; b=owEBbQKS/ZANAwAKAQHKCLemxQgkAcsmYgBoT3QXUmwc9/dCynBWE/WKymn4LvmWDoaAkcPa/ twzLeqXmI6JAjMEAAEKAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCaE90FwAKCRABygi3psUI JJt2D/96iuNKzAxGnEHVosM27pNigeAU5uos6CMZyL/eSOYYapNkzJGuEJOz+7fmbN+kamRLRxd f8iUjNFO8N9IYliG2cSGn8hV8NudpPs+0nbt0Iwz9QaZ0y+1XPMobYMvrRw/DzYj/YPJ0boaj8P ZAHPMAnw9roc9EoJzyyvj0+CwkgwVGZ7SvuYWsAJ1dMLtRTF0Uc4mtU9feG3KSn8xcODyBwcIzs eE3aNyPEtCBLqh26Eby3t7EvnNlD01HiJUIIqQAT2D8tHvqSwuHBujet9sgHIw58UjEz4h0vRWm JhsJzu1IcgoQckHppjcxvB2xZKd6+Pkoe1rmSpzRPJFu16DGsD7sCOYJu9dZipGb+RUBWmpiVIj hCy+2FSj53gJvQ1TMhO9kCi+4Dqz9O3VWV2LnC3/Sd6FaYJcy79vf8hFXy9sc/OloohbE1+7xOy unDyyWbfXnGKkOw68ocKgvFSZinOEtgnGzsw0MPrllKDoB3wmXTUcAOrjySr5NBQJrZHFjJSNfz 4OX3XhU9PKPAb4ZPix4I/LW00wGMyaJxhGsN1bkS+mFkX1tTaW9OPZYUXouet2u5E6GYn433WMb IQrseHjlezYTW2fVewcsPYXJqXORyZfrSziRAe4NE/8YvG6iUVjYdBr3LdcjVFNDD3p79jFyz+Q DTwodajb9kcd8iA== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 Support for implementations that deliver its interrupts in ways other than FIQ will be added, which requires a per-implementation startup function. Signed-off-by: Nick Chan --- drivers/perf/apple_m1_cpu_pmu.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pm= u.c index 6736909a7df672a08938a392d450dc9b5b7bce9e..f4d8da4a8aa0c197cd16af422b3= 3f4cd943d379d 100644 --- a/drivers/perf/apple_m1_cpu_pmu.c +++ b/drivers/perf/apple_m1_cpu_pmu.c @@ -660,7 +660,6 @@ static int apple_pmu_init(struct arm_pmu *cpu_pmu, u32 = counters) cpu_pmu->read_counter =3D m1_pmu_read_counter; cpu_pmu->write_counter =3D m1_pmu_write_counter; cpu_pmu->clear_event_idx =3D m1_pmu_clear_event_idx; - cpu_pmu->start =3D m1_pmu_start; cpu_pmu->stop =3D m1_pmu_stop; cpu_pmu->set_event_filter =3D m1_pmu_set_event_filter; =20 @@ -682,6 +681,7 @@ static int m1_pmu_ice_init(struct arm_pmu *cpu_pmu) cpu_pmu->get_event_idx =3D m1_pmu_get_event_idx; cpu_pmu->map_event =3D m1_pmu_map_event; cpu_pmu->reset =3D m1_pmu_reset; + cpu_pmu->start =3D m1_pmu_start; return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); } =20 @@ -691,6 +691,7 @@ static int m1_pmu_fire_init(struct arm_pmu *cpu_pmu) cpu_pmu->get_event_idx =3D m1_pmu_get_event_idx; cpu_pmu->map_event =3D m1_pmu_map_event; cpu_pmu->reset =3D m1_pmu_reset; + cpu_pmu->start =3D m1_pmu_start; return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); } =20 @@ -700,6 +701,7 @@ static int m2_pmu_avalanche_init(struct arm_pmu *cpu_pm= u) cpu_pmu->get_event_idx =3D m1_pmu_get_event_idx; cpu_pmu->map_event =3D m2_pmu_map_event; cpu_pmu->reset =3D m1_pmu_reset; + cpu_pmu->start =3D m1_pmu_start; return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); } =20 @@ -709,6 +711,7 @@ static int m2_pmu_blizzard_init(struct arm_pmu *cpu_pmu) cpu_pmu->get_event_idx =3D m1_pmu_get_event_idx; cpu_pmu->map_event =3D m2_pmu_map_event; cpu_pmu->reset =3D m1_pmu_reset; + cpu_pmu->start =3D m1_pmu_start; return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); } =20 --=20 2.49.0 From nobody Fri Oct 10 04:02:06 2025 Received: from mail-pl1-f177.google.com (mail-pl1-f177.google.com [209.85.214.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A674621ABC8; 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Signed-off-by: Nick Chan --- drivers/perf/apple_m1_cpu_pmu.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pm= u.c index f4d8da4a8aa0c197cd16af422b33f4cd943d379d..74e9e643cef7f9a3c9ed599da36= cf9b04b124810 100644 --- a/drivers/perf/apple_m1_cpu_pmu.c +++ b/drivers/perf/apple_m1_cpu_pmu.c @@ -669,7 +669,6 @@ static int apple_pmu_init(struct arm_pmu *cpu_pmu, u32 = counters) } =20 bitmap_set(cpu_pmu->cntr_mask, 0, counters); - cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =3D &m1_pmu_events_attr_gr= oup; cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =3D &m1_pmu_format_attr_g= roup; return 0; } @@ -682,6 +681,7 @@ static int m1_pmu_ice_init(struct arm_pmu *cpu_pmu) cpu_pmu->map_event =3D m1_pmu_map_event; cpu_pmu->reset =3D m1_pmu_reset; cpu_pmu->start =3D m1_pmu_start; + cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =3D &m1_pmu_events_attr_gr= oup; return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); } =20 @@ -692,6 +692,7 @@ static int m1_pmu_fire_init(struct arm_pmu *cpu_pmu) cpu_pmu->map_event =3D m1_pmu_map_event; cpu_pmu->reset =3D m1_pmu_reset; cpu_pmu->start =3D m1_pmu_start; + cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =3D &m1_pmu_events_attr_gr= oup; return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); } =20 @@ -702,6 +703,7 @@ static int m2_pmu_avalanche_init(struct arm_pmu *cpu_pm= u) cpu_pmu->map_event =3D m2_pmu_map_event; cpu_pmu->reset =3D m1_pmu_reset; cpu_pmu->start =3D m1_pmu_start; + cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =3D &m1_pmu_events_attr_gr= oup; return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); } =20 @@ -712,6 +714,7 @@ static int m2_pmu_blizzard_init(struct arm_pmu *cpu_pmu) cpu_pmu->map_event =3D m2_pmu_map_event; cpu_pmu->reset =3D m1_pmu_reset; cpu_pmu->start =3D m1_pmu_start; + cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =3D &m1_pmu_events_attr_gr= oup; return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); } =20 --=20 2.49.0 From nobody Fri Oct 10 04:02:06 2025 Received: from mail-pj1-f47.google.com (mail-pj1-f47.google.com [209.85.216.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 67DE621FF5F; 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[175.159.121.134]) by smtp.googlemail.com with ESMTPSA id d9443c01a7336-2365deb2cedsm49932455ad.163.2025.06.15.18.32.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 15 Jun 2025 18:32:39 -0700 (PDT) From: Nick Chan Date: Mon, 16 Jun 2025 09:31:57 +0800 Subject: [PATCH RESEND v7 08/21] drivers/perf: apple_m1: Add Apple A7 support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250616-apple-cpmu-v7-8-df2778a44d5c@gmail.com> References: <20250616-apple-cpmu-v7-0-df2778a44d5c@gmail.com> In-Reply-To: <20250616-apple-cpmu-v7-0-df2778a44d5c@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Sven Peter Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=11055; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=pQGdfMsvl9m9TngcNZsP+Jy/Y/QiLcqbmIk8c2DGdOI=; b=owEBbQKS/ZANAwAKAQHKCLemxQgkAcsmYgBoT3QYDSyUP/uoH7lxMdOYsX/+3iQ/VvCOvGv36 YWgn4TR5lCJAjMEAAEKAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCaE90GAAKCRABygi3psUI JNVSD/wJQpo+ejpup4lAJYWT3Fro/kdp9n1Aqf8rTxphd6X50PHijaPlK1TQu1Qx1mBZ8MN7ecS +AihBzLhPP2EdejBwOyOTCfaWLp06KgKyoZUhdJ7kCM+yyhA9E2UQahlu+RSkdDaErc1aiqtHDq iCjTRqK4DnlslLFarTb4RL10jbf/Ds87edewy62GkZGLbLsbzEjfb+fJ8BEYwnsMluFdMnrJlua 2uVmybyHopbYcBawt2AzTqphYOqwAbg0JpzVGoNj43gkRjJdnPPFCjqBYSq4YVaHimkD0vostF0 U/O4WWxUsZyBvvmlJfaLQDA5LMuDSZ3tou0Bgdrn8aP3mC2CrU5HKNNdvGzoV/DKfFZyRgz5H8y GkfF+WGGF6uiY/PqNNwN8wNB1comVbWKtbLrHmJrgwrbK9iUtNL7Yx6Mlc+CSE1A3u9iLIDcAEa wTjWLTak5mTM3GnAln2D/oFgIGln+/9HawdE80C9x0BdtCcGbziG8ihR0fLCVZc1/rGpQ2bB+Zi Z3rI6zuf91KVaMEa5mJkv8p4NGyZ4v3bh9xCfEHLp6+UWv81GC1SH3hKLZtSKWT9duvuBpJFJNp 9uBg5sLZxWXYbFKhM07hECKRtB34eZsq2Id3kQfRJvvGbXv64SGB0oPE2KK0DLDCNEoQGX29sFE wF2ZyP0P3MQkUMA== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 Add support for the CPU PMU found in the Apple A7 SoC. The PMU has 8 counters and a very different event layout compared to the M1 PMU. Interrupts are delivered as IRQs instead of FIQs like on the M1. Signed-off-by: Nick Chan --- drivers/perf/apple_m1_cpu_pmu.c | 190 ++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 190 insertions(+) diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pm= u.c index 74e9e643cef7f9a3c9ed599da36cf9b04b124810..ac9beafff3d691b226c261f222c= 2dfb057959a56 100644 --- a/drivers/perf/apple_m1_cpu_pmu.c +++ b/drivers/perf/apple_m1_cpu_pmu.c @@ -19,6 +19,7 @@ #include #include =20 +#define A7_PMU_NR_COUNTERS 8 #define M1_PMU_NR_COUNTERS 10 #define APPLE_PMU_MAX_NR_COUNTERS 10 =20 @@ -45,6 +46,143 @@ * know next to nothing about the events themselves, and we already have * per cpu-type PMU abstractions. */ + +enum a7_pmu_events { + A7_PMU_PERFCTR_INST_ALL =3D 0x0, + A7_PMU_PERFCTR_UNKNOWN_1 =3D 0x1, + A7_PMU_PERFCTR_CORE_ACTIVE_CYCLE =3D 0x2, + A7_PMU_PERFCTR_L2_TLB_MISS_INSTRUCTION =3D 0x10, + A7_PMU_PERFCTR_L2_TLB_MISS_DATA =3D 0x11, + A7_PMU_PERFCTR_BIU_UPSTREAM_CYCLE =3D 0x19, + A7_PMU_PERFCTR_BIU_DOWNSTREAM_CYCLE =3D 0x20, + A7_PMU_PERFCTR_L2C_AGENT_LD =3D 0x22, + A7_PMU_PERFCTR_L2C_AGENT_LD_MISS =3D 0x23, + A7_PMU_PERFCTR_L2C_AGENT_ST =3D 0x24, + A7_PMU_PERFCTR_L2C_AGENT_ST_MISS =3D 0x25, + A7_PMU_PERFCTR_SCHEDULE_UOP =3D 0x58, + A7_PMU_PERFCTR_MAP_REWIND =3D 0x61, + A7_PMU_PERFCTR_MAP_STALL =3D 0x62, + A7_PMU_PERFCTR_FLUSH_RESTART_OTHER_NONSPEC =3D 0x6e, + A7_PMU_PERFCTR_INST_A32 =3D 0x78, + A7_PMU_PERFCTR_INST_T32 =3D 0x79, + A7_PMU_PERFCTR_INST_A64 =3D 0x7a, + A7_PMU_PERFCTR_INST_BRANCH =3D 0x7b, + A7_PMU_PERFCTR_INST_BRANCH_CALL =3D 0x7c, + A7_PMU_PERFCTR_INST_BRANCH_RET =3D 0x7d, + A7_PMU_PERFCTR_INST_BRANCH_TAKEN =3D 0x7e, + A7_PMU_PERFCTR_INST_BRANCH_INDIR =3D 0x81, + A7_PMU_PERFCTR_INST_BRANCH_COND =3D 0x82, + A7_PMU_PERFCTR_INST_INT_LD =3D 0x83, + A7_PMU_PERFCTR_INST_INT_ST =3D 0x84, + A7_PMU_PERFCTR_INST_INT_ALU =3D 0x85, + A7_PMU_PERFCTR_INST_SIMD_LD =3D 0x86, + A7_PMU_PERFCTR_INST_SIMD_ST =3D 0x87, + A7_PMU_PERFCTR_INST_SIMD_ALU =3D 0x88, + A7_PMU_PERFCTR_INST_LDST =3D 0x89, + A7_PMU_PERFCTR_UNKNOWN_8d =3D 0x8d, + A7_PMU_PERFCTR_UNKNOWN_8e =3D 0x8e, + A7_PMU_PERFCTR_UNKNOWN_8f =3D 0x8f, + A7_PMU_PERFCTR_UNKNOWN_90 =3D 0x90, + A7_PMU_PERFCTR_UNKNOWN_93 =3D 0x93, + A7_PMU_PERFCTR_UNKNOWN_94 =3D 0x94, + A7_PMU_PERFCTR_UNKNOWN_95 =3D 0x95, + A7_PMU_PERFCTR_L1D_TLB_ACCESS =3D 0x96, + A7_PMU_PERFCTR_L1D_TLB_MISS =3D 0x97, + A7_PMU_PERFCTR_L1D_CACHE_MISS_ST =3D 0x98, + A7_PMU_PERFCTR_L1D_CACHE_MISS_LD =3D 0x99, + A7_PMU_PERFCTR_UNKNOWN_9b =3D 0x9b, + A7_PMU_PERFCTR_LD_UNIT_UOP =3D 0x9c, + A7_PMU_PERFCTR_ST_UNIT_UOP =3D 0x9d, + A7_PMU_PERFCTR_L1D_CACHE_WRITEBACK =3D 0x9e, + A7_PMU_PERFCTR_UNKNOWN_9f =3D 0x9f, + A7_PMU_PERFCTR_LDST_X64_UOP =3D 0xa7, + A7_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC =3D 0xb4, + A7_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC =3D 0xb5, + A7_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC =3D 0xb6, + A7_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC =3D 0xb9, + A7_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC =3D 0xba, + A7_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC =3D 0xbb, + A7_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC =3D 0xbd, + A7_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC =3D 0xbf, + A7_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC =3D 0xc0, + A7_PMU_PERFCTR_UNKNOWN_c1 =3D 0xc1, + A7_PMU_PERFCTR_UNKNOWN_c4 =3D 0xc4, + A7_PMU_PERFCTR_UNKNOWN_c5 =3D 0xc5, + A7_PMU_PERFCTR_UNKNOWN_c6 =3D 0xc6, + A7_PMU_PERFCTR_UNKNOWN_c8 =3D 0xc8, + A7_PMU_PERFCTR_UNKNOWN_ca =3D 0xca, + A7_PMU_PERFCTR_UNKNOWN_cb =3D 0xcb, + A7_PMU_PERFCTR_FED_IC_MISS_DEMAND =3D 0xce, + A7_PMU_PERFCTR_L1I_TLB_MISS_DEMAND =3D 0xcf, + A7_PMU_PERFCTR_UNKNOWN_f5 =3D 0xf5, + A7_PMU_PERFCTR_UNKNOWN_f6 =3D 0xf6, + A7_PMU_PERFCTR_UNKNOWN_f7 =3D 0xf7, + A7_PMU_PERFCTR_UNKNOWN_f8 =3D 0xf8, + A7_PMU_PERFCTR_UNKNOWN_fd =3D 0xfd, + A7_PMU_PERFCTR_LAST =3D M1_PMU_CFG_EVENT, + /* + * From this point onwards, these are not actual HW events, + * but attributes that get stored in hw->config_base. + */ + A7_PMU_CFG_COUNT_USER =3D BIT(8), + A7_PMU_CFG_COUNT_KERNEL =3D BIT(9), +}; + +static const u16 a7_pmu_event_affinity[A7_PMU_PERFCTR_LAST + 1] =3D { + [0 ... A7_PMU_PERFCTR_LAST] =3D ANY_BUT_0_1, + [A7_PMU_PERFCTR_INST_ALL] =3D ANY_BUT_0_1 | BIT(1), + [A7_PMU_PERFCTR_UNKNOWN_1] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_CORE_ACTIVE_CYCLE] =3D ANY_BUT_0_1 | BIT(0), + [A7_PMU_PERFCTR_INST_A32] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_T32] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_A64] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_BRANCH] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_BRANCH_CALL] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_BRANCH_RET] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_BRANCH_TAKEN] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_BRANCH_INDIR] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_BRANCH_COND] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_INT_LD] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_INT_ST] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_INT_ALU] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_SIMD_LD] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_SIMD_ST] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_SIMD_ALU] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_LDST] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_8d] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_8e] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_8f] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_90] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_93] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_94] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_95] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_L1D_CACHE_MISS_ST] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_L1D_CACHE_MISS_LD] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_9b] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_LD_UNIT_UOP] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_9f] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_c1] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_c4] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_c5] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_c6] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_c8] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_ca] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_cb] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_f5] =3D ONLY_2_4_6, + [A7_PMU_PERFCTR_UNKNOWN_f6] =3D ONLY_2_4_6, + [A7_PMU_PERFCTR_UNKNOWN_f7] =3D ONLY_2_4_6, + [A7_PMU_PERFCTR_UNKNOWN_fd] =3D ONLY_2_4_6, +}; + enum m1_pmu_events { M1_PMU_PERFCTR_RETIRE_UOP =3D 0x1, M1_PMU_PERFCTR_CORE_ACTIVE_CYCLE =3D 0x2, @@ -165,6 +303,14 @@ static const u16 m1_pmu_event_affinity[M1_PMU_PERFCTR_= LAST + 1] =3D { [M1_PMU_PERFCTR_UNKNOWN_fd] =3D ONLY_2_4_6, }; =20 +static const unsigned int a7_pmu_perf_map[PERF_COUNT_HW_MAX] =3D { + PERF_MAP_ALL_UNSUPPORTED, + [PERF_COUNT_HW_CPU_CYCLES] =3D A7_PMU_PERFCTR_CORE_ACTIVE_CYCLE, + [PERF_COUNT_HW_INSTRUCTIONS] =3D A7_PMU_PERFCTR_INST_ALL, + [PERF_COUNT_HW_BRANCH_MISSES] =3D A7_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC, + [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] =3D A7_PMU_PERFCTR_INST_BRANCH +}; + static const unsigned m1_pmu_perf_map[PERF_COUNT_HW_MAX] =3D { PERF_MAP_ALL_UNSUPPORTED, [PERF_COUNT_HW_CPU_CYCLES] =3D M1_PMU_PERFCTR_CORE_ACTIVE_CYCLE, @@ -199,6 +345,17 @@ static ssize_t m1_pmu_events_sysfs_show(struct device = *dev, #define M1_PMU_EVENT_ATTR(name, config) \ PMU_EVENT_ATTR_ID(name, m1_pmu_events_sysfs_show, config) =20 +static struct attribute *a7_pmu_event_attrs[] =3D { + M1_PMU_EVENT_ATTR(cycles, A7_PMU_PERFCTR_CORE_ACTIVE_CYCLE), + M1_PMU_EVENT_ATTR(instructions, A7_PMU_PERFCTR_INST_ALL), + NULL, +}; + +static const struct attribute_group a7_pmu_events_attr_group =3D { + .name =3D "events", + .attrs =3D a7_pmu_event_attrs, +}; + static struct attribute *m1_pmu_event_attrs[] =3D { M1_PMU_EVENT_ATTR(cycles, M1_PMU_PERFCTR_CORE_ACTIVE_CYCLE), M1_PMU_EVENT_ATTR(instructions, M1_PMU_PERFCTR_INST_ALL), @@ -522,6 +679,12 @@ static int apple_pmu_get_event_idx(struct pmu_hw_event= s *cpuc, return -EAGAIN; } =20 +static int a7_pmu_get_event_idx(struct pmu_hw_events *cpuc, + struct perf_event *event) +{ + return apple_pmu_get_event_idx(cpuc, event, a7_pmu_event_affinity); +} + static int m1_pmu_get_event_idx(struct pmu_hw_events *cpuc, struct perf_event *event) { @@ -545,6 +708,11 @@ static void __m1_pmu_set_mode(u8 mode) isb(); } =20 +static void a7_pmu_start(struct arm_pmu *cpu_pmu) +{ + __m1_pmu_set_mode(PMCR0_IMODE_AIC); +} + static void m1_pmu_start(struct arm_pmu *cpu_pmu) { __m1_pmu_set_mode(PMCR0_IMODE_FIQ); @@ -579,6 +747,11 @@ static int apple_pmu_map_event_63(struct perf_event *e= vent, return armpmu_map_event(event, perf_map, NULL, M1_PMU_CFG_EVENT); } =20 +static int a7_pmu_map_event(struct perf_event *event) +{ + return apple_pmu_map_event_47(event, &a7_pmu_perf_map); +} + static int m1_pmu_map_event(struct perf_event *event) { return apple_pmu_map_event_47(event, &m1_pmu_perf_map); @@ -624,6 +797,11 @@ static void apple_pmu_reset(void *info, u32 counters) isb(); } =20 +static void a7_pmu_reset(void *info) +{ + apple_pmu_reset(info, A7_PMU_NR_COUNTERS); +} + static void m1_pmu_reset(void *info) { apple_pmu_reset(info, M1_PMU_NR_COUNTERS); @@ -674,6 +852,17 @@ static int apple_pmu_init(struct arm_pmu *cpu_pmu, u32= counters) } =20 /* Device driver gunk */ +static int a7_pmu_cyclone_init(struct arm_pmu *cpu_pmu) +{ + cpu_pmu->name =3D "apple_cyclone_pmu"; + cpu_pmu->get_event_idx =3D a7_pmu_get_event_idx; + cpu_pmu->map_event =3D a7_pmu_map_event; + cpu_pmu->reset =3D a7_pmu_reset; + cpu_pmu->start =3D a7_pmu_start; + cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =3D &a7_pmu_events_attr_gr= oup; + return apple_pmu_init(cpu_pmu, A7_PMU_NR_COUNTERS); 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[175.159.121.134]) by smtp.googlemail.com with ESMTPSA id d9443c01a7336-2365deb2cedsm49932455ad.163.2025.06.15.18.32.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 15 Jun 2025 18:32:43 -0700 (PDT) From: Nick Chan Date: Mon, 16 Jun 2025 09:31:58 +0800 Subject: [PATCH RESEND v7 09/21] drivers/perf: apple_m1: Add Apple A8/A8X support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250616-apple-cpmu-v7-9-df2778a44d5c@gmail.com> References: <20250616-apple-cpmu-v7-0-df2778a44d5c@gmail.com> In-Reply-To: <20250616-apple-cpmu-v7-0-df2778a44d5c@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Sven Peter Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=7313; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=YYxBoRi9tg74DJBz5VJpYdMNCrAuGOPZ8JV7L/qISSk=; b=owEBbQKS/ZANAwAKAQHKCLemxQgkAcsmYgBoT3QY9jCRcgHRf+ghE+yXd7sFBwZIkZSNZjTO5 xCXvU6dMqiJAjMEAAEKAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCaE90GAAKCRABygi3psUI JKpzEACSmZ2P6P4SHeIyebwYCiQuR2tWnhDgXRgM7Dh8gbKzlv5wY5aCh6YEVGrItTQUnCPWfIa gbyURQoJZX+EJcZ90Gn0z0o6vvXcv+Tz969BMSX1NUoReGASAdiDtxJJ3YX7iZ47cKOIj+F/SS0 E1K+tEj2w6pUnFjnfxwFtjMtrv5I1ngKDAmvuzDNOEdUi1izHH9MmtFk4UJiskRrvJtm7nAVgx/ YE/UtHGil5Dff9hYUBfgR3ferCGFNQALObq6ug2oItCtZGEe60VesBF7YXmzYUFYTBAcBnriRGz 8lq8aa4oP4q4LUfXpHOW/AzN5ukO1QwnS61lIhawpdIvCEfMpM0DsqmvTXfXD60NDOsST5H2Stn 4RN8oWX3yM7BWiCSCdGnytng/dcJvaRs4NIToseN/emn56CEYFj4OIpQMrpzfulCGGEHgtIx7bw kQtRfQIWiJuhp1/zEjHU1SwKqk12FrNHMWVgZWMiNXIqfi6nBxxzl3sIj6uqyCxcCpIGhDPOWHP wHhEaFhXXCigvzlJlU+Z76nnmLQNwXXfr2Q4gui6RIe34eqtX8TOgw3yR7uyNGWi9FEji3GQZ4s EaWi6eEex2b602HkjF+umdbPRi6nfrVxS4C/1blIXGCe8G5xBff/F4V30XdS69PU7oKkri16A07 nnlSdjOVo8oIYKg== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 Add support for the CPU PMU found on the Apple A8, A8X SoCs. Signed-off-by: Nick Chan --- drivers/perf/apple_m1_cpu_pmu.c | 124 ++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 124 insertions(+) diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pm= u.c index ac9beafff3d691b226c261f222c2dfb057959a56..e56f7fa9829da9e9444c6834b03= e4a79dbc02c22 100644 --- a/drivers/perf/apple_m1_cpu_pmu.c +++ b/drivers/perf/apple_m1_cpu_pmu.c @@ -28,6 +28,7 @@ #define ANY_BUT_0_1 GENMASK(9, 2) #define ONLY_2_TO_7 GENMASK(7, 2) #define ONLY_2_4_6 (BIT(2) | BIT(4) | BIT(6)) +#define ONLY_3_5_7 (BIT(3) | BIT(5) | BIT(7)) #define ONLY_5_6_7 (BIT(5) | BIT(6) | BIT(7)) =20 /* @@ -183,6 +184,111 @@ static const u16 a7_pmu_event_affinity[A7_PMU_PERFCTR= _LAST + 1] =3D { [A7_PMU_PERFCTR_UNKNOWN_fd] =3D ONLY_2_4_6, }; =20 +enum a8_pmu_events { + A8_PMU_PERFCTR_UNKNOWN_1 =3D 0x1, + A8_PMU_PERFCTR_CORE_ACTIVE_CYCLE =3D 0x2, + A8_PMU_PERFCTR_L2_TLB_MISS_INSTRUCTION =3D 0xa, + A8_PMU_PERFCTR_L2_TLB_MISS_DATA =3D 0xb, + A8_PMU_PERFCTR_BIU_UPSTREAM_CYCLE =3D 0x13, + A8_PMU_PERFCTR_BIU_DOWNSTREAM_CYCLE =3D 0x14, + A8_PMU_PERFCTR_L2C_AGENT_LD =3D 0x1a, + A8_PMU_PERFCTR_L2C_AGENT_LD_MISS =3D 0x1b, + A8_PMU_PERFCTR_L2C_AGENT_ST =3D 0x1c, + A8_PMU_PERFCTR_L2C_AGENT_ST_MISS =3D 0x1d, + A8_PMU_PERFCTR_SCHEDULE_UOP =3D 0x52, + A8_PMU_PERFCTR_MAP_REWIND =3D 0x75, + A8_PMU_PERFCTR_MAP_STALL =3D 0x76, + A8_PMU_PERFCTR_MAP_INT_UOP =3D 0x7b, + A8_PMU_PERFCTR_MAP_LDST_UOP =3D 0x7c, + A8_PMU_PERFCTR_MAP_SIMD_UOP =3D 0x7d, + A8_PMU_PERFCTR_FLUSH_RESTART_OTHER_NONSPEC =3D 0x84, + A8_PMU_PERFCTR_INST_A32 =3D 0x8a, + A8_PMU_PERFCTR_INST_T32 =3D 0x8b, + A8_PMU_PERFCTR_INST_ALL =3D 0x8c, + A8_PMU_PERFCTR_INST_BRANCH =3D 0x8d, + A8_PMU_PERFCTR_INST_BRANCH_CALL =3D 0x8e, + A8_PMU_PERFCTR_INST_BRANCH_RET =3D 0x8f, + A8_PMU_PERFCTR_INST_BRANCH_TAKEN =3D 0x90, + A8_PMU_PERFCTR_INST_BRANCH_INDIR =3D 0x93, + A8_PMU_PERFCTR_INST_BRANCH_COND =3D 0x94, + A8_PMU_PERFCTR_INST_INT_LD =3D 0x95, + A8_PMU_PERFCTR_INST_INT_ST =3D 0x96, + A8_PMU_PERFCTR_INST_INT_ALU =3D 0x97, + A8_PMU_PERFCTR_INST_SIMD_LD =3D 0x98, + A8_PMU_PERFCTR_INST_SIMD_ST =3D 0x99, + A8_PMU_PERFCTR_INST_SIMD_ALU =3D 0x9a, + A8_PMU_PERFCTR_INST_LDST =3D 0x9b, + A8_PMU_PERFCTR_UNKNOWN_9c =3D 0x9c, + A8_PMU_PERFCTR_UNKNOWN_9f =3D 0x9f, + A8_PMU_PERFCTR_L1D_TLB_ACCESS =3D 0xa0, + A8_PMU_PERFCTR_L1D_TLB_MISS =3D 0xa1, + A8_PMU_PERFCTR_L1D_CACHE_MISS_ST =3D 0xa2, + A8_PMU_PERFCTR_L1D_CACHE_MISS_LD =3D 0xa3, + A8_PMU_PERFCTR_LD_UNIT_UOP =3D 0xa6, + A8_PMU_PERFCTR_ST_UNIT_UOP =3D 0xa7, + A8_PMU_PERFCTR_L1D_CACHE_WRITEBACK =3D 0xa8, + A8_PMU_PERFCTR_LDST_X64_UOP =3D 0xb1, + A8_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC =3D 0xbf, + A8_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC =3D 0xc0, + A8_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC =3D 0xc1, + A8_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC =3D 0xc4, + A8_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC =3D 0xc5, + A8_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC =3D 0xc6, + A8_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC =3D 0xc8, + A8_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC =3D 0xca, + A8_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC =3D 0xcb, + A8_PMU_PERFCTR_FED_IC_MISS_DEMAND =3D 0xd3, + A8_PMU_PERFCTR_L1I_TLB_MISS_DEMAND =3D 0xd4, + A8_PMU_PERFCTR_FETCH_RESTART =3D 0xde, + A8_PMU_PERFCTR_UNKNOWN_f5 =3D 0xf5, + A8_PMU_PERFCTR_UNKNOWN_f6 =3D 0xf6, + A8_PMU_PERFCTR_UNKNOWN_f7 =3D 0xf7, + A8_PMU_PERFCTR_LAST =3D M1_PMU_CFG_EVENT, + + /* + * From this point onwards, these are not actual HW events, + * but attributes that get stored in hw->config_base. + */ + A8_PMU_CFG_COUNT_USER =3D BIT(8), + A8_PMU_CFG_COUNT_KERNEL =3D BIT(9), +}; + +static const u16 a8_pmu_event_affinity[A8_PMU_PERFCTR_LAST + 1] =3D { + [0 ... A8_PMU_PERFCTR_LAST] =3D ANY_BUT_0_1, + [A8_PMU_PERFCTR_UNKNOWN_1] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_CORE_ACTIVE_CYCLE] =3D ANY_BUT_0_1 | BIT(0), + [A8_PMU_PERFCTR_INST_A32] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_T32] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_ALL] =3D BIT(7) | BIT(1), + [A8_PMU_PERFCTR_INST_BRANCH] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_BRANCH_CALL] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_BRANCH_RET] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_BRANCH_TAKEN] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_BRANCH_INDIR] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_BRANCH_COND] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_INT_LD] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_INT_ST] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_INT_ALU] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_SIMD_LD] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_SIMD_ST] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_SIMD_ALU] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_LDST] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_UNKNOWN_9c] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_UNKNOWN_9f] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_UNKNOWN_f5] =3D ANY_BUT_0_1, + [A8_PMU_PERFCTR_UNKNOWN_f6] =3D ONLY_3_5_7, + [A8_PMU_PERFCTR_UNKNOWN_f7] =3D ONLY_3_5_7, +}; + enum m1_pmu_events { M1_PMU_PERFCTR_RETIRE_UOP =3D 0x1, M1_PMU_PERFCTR_CORE_ACTIVE_CYCLE =3D 0x2, @@ -685,6 +791,12 @@ static int a7_pmu_get_event_idx(struct pmu_hw_events *= cpuc, return apple_pmu_get_event_idx(cpuc, event, a7_pmu_event_affinity); } =20 +static int a8_pmu_get_event_idx(struct pmu_hw_events *cpuc, + struct perf_event *event) +{ + return apple_pmu_get_event_idx(cpuc, event, a8_pmu_event_affinity); +} + static int m1_pmu_get_event_idx(struct pmu_hw_events *cpuc, struct perf_event *event) { @@ -863,6 +975,17 @@ static int a7_pmu_cyclone_init(struct arm_pmu *cpu_pmu) return apple_pmu_init(cpu_pmu, A7_PMU_NR_COUNTERS); } =20 +static int a8_pmu_typhoon_init(struct arm_pmu *cpu_pmu) +{ + cpu_pmu->name =3D "apple_typhoon_pmu"; + cpu_pmu->get_event_idx =3D a8_pmu_get_event_idx; + cpu_pmu->map_event =3D m1_pmu_map_event; + cpu_pmu->reset =3D a7_pmu_reset; + cpu_pmu->start =3D a7_pmu_start; + cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =3D &m1_pmu_events_attr_gr= oup; + return apple_pmu_init(cpu_pmu, A7_PMU_NR_COUNTERS); +} + static int m1_pmu_ice_init(struct arm_pmu *cpu_pmu) { cpu_pmu->name =3D "apple_icestorm_pmu"; @@ -912,6 +1035,7 @@ static const struct of_device_id m1_pmu_of_device_ids[= ] =3D { { .compatible =3D "apple,blizzard-pmu", .data =3D m2_pmu_blizzard_init, }, { .compatible =3D "apple,icestorm-pmu", .data =3D m1_pmu_ice_init, }, { .compatible =3D "apple,firestorm-pmu", .data =3D m1_pmu_fire_init, }, + { .compatible =3D "apple,typhoon-pmu", .data =3D a8_pmu_typhoon_init, }, { .compatible =3D "apple,cyclone-pmu", .data =3D a7_pmu_cyclone_init, }, { }, }; --=20 2.49.0 From nobody Fri Oct 10 04:02:06 2025 Received: from mail-pg1-f174.google.com (mail-pg1-f174.google.com [209.85.215.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 684F2262FF1; Mon, 16 Jun 2025 01:32:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.174 ARC-Seal: i=1; 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[175.159.121.134]) by smtp.googlemail.com with ESMTPSA id d9443c01a7336-2365deb2cedsm49932455ad.163.2025.06.15.18.32.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 15 Jun 2025 18:32:46 -0700 (PDT) From: Nick Chan Date: Mon, 16 Jun 2025 09:31:59 +0800 Subject: [PATCH RESEND v7 10/21] drivers/perf: apple_m1: Add A9/A9X support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250616-apple-cpmu-v7-10-df2778a44d5c@gmail.com> References: <20250616-apple-cpmu-v7-0-df2778a44d5c@gmail.com> In-Reply-To: <20250616-apple-cpmu-v7-0-df2778a44d5c@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Sven Peter Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=6996; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=wl40dMXc8W0PdUzpNjblXnUW0iWApVwrvUwg8aXHqWM=; b=owEBbQKS/ZANAwAKAQHKCLemxQgkAcsmYgBoT3QYzkM6OtNggSbVQTTUUqoHAtJZO/AYTiMwH uvS2ucgsjiJAjMEAAEKAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCaE90GAAKCRABygi3psUI JK+6D/0SosreD+Kv8mIQ7V0lkT+Zllm0HHJbCHRg0H+BhFH5YzW53HGyHd3bvPbqQSGc/CfZzQz XPc3NfB516oIUV/fXfS3HUEWuQUdOZNk/3HzrcOG54dunp0dJn4gW/avVXAyAoRrDyYPlmdmbxS 9cljwk1oxmBba9X35ludf4hwAltUvK9D3t4U51UtU8+6RZdL7wwhptCjO6jkpjhhAdHx6qBfCuz NNSzQtBnc7FuZtEjDrlkg+BZFFMK6C+LPdz7rYIhk/hVIVlZzGZcJCoKgecPMTn+zdQc+OZTEIn oHf/eVQubM334p1Jhl2Oc5dQQqrnq8l1+oUOw0rAG4XBWgSdElGICdvU4tO350jfVKexgyOtPe6 7F7MOk47o+FykXcrcZeNSaW/GoQEo8V7BwgEHeqX+/ZSytG62fFitO9QUeW3useEWw6l2K07m4K uM1CzU+0PmdeeSmH5cm5GSL8OniZLmCbDvDub8U3qXFz5UvItDt+zqH7Jzo6xX4efGfJAnr1k+M JTbf80AqHeFETLST0pHt1ktMf2NXChOLk7QkTYzKzlfqrGji+rScfHWPe3gm3LV62XO75hPp/uT BNNO7dIN49VVbu0eRxqZBkZTDdH1abbJ3hgB7EOv0MexbxU6kkrtJEzJzYZrDAMIOTfb+2S/JA8 5K0kXLdQeJoq5PA== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 Add support for CPU PMU found in the Apple A9 and A9X SoCs. Signed-off-by: Nick Chan --- drivers/perf/apple_m1_cpu_pmu.c | 121 ++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 121 insertions(+) diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pm= u.c index e56f7fa9829da9e9444c6834b03e4a79dbc02c22..e89fe646a849f50615a3dc809e5= 1a6cd95dd9a1b 100644 --- a/drivers/perf/apple_m1_cpu_pmu.c +++ b/drivers/perf/apple_m1_cpu_pmu.c @@ -289,6 +289,109 @@ static const u16 a8_pmu_event_affinity[A8_PMU_PERFCTR= _LAST + 1] =3D { [A8_PMU_PERFCTR_UNKNOWN_f7] =3D ONLY_3_5_7, }; =20 + +enum a9_pmu_events { + A9_PMU_PERFCTR_UNKNOWN_1 =3D 0x1, + A9_PMU_PERFCTR_CORE_ACTIVE_CYCLE =3D 0x2, + A9_PMU_PERFCTR_L2_TLB_MISS_INSTRUCTION =3D 0xa, + A9_PMU_PERFCTR_L2_TLB_MISS_DATA =3D 0xb, + A9_PMU_PERFCTR_L2C_AGENT_LD =3D 0x1a, + A9_PMU_PERFCTR_L2C_AGENT_LD_MISS =3D 0x1b, + A9_PMU_PERFCTR_L2C_AGENT_ST =3D 0x1c, + A9_PMU_PERFCTR_L2C_AGENT_ST_MISS =3D 0x1d, + A9_PMU_PERFCTR_SCHEDULE_UOP =3D 0x52, + A9_PMU_PERFCTR_MAP_REWIND =3D 0x75, + A9_PMU_PERFCTR_MAP_STALL =3D 0x76, + A9_PMU_PERFCTR_MAP_INT_UOP =3D 0x7c, + A9_PMU_PERFCTR_MAP_LDST_UOP =3D 0x7d, + A9_PMU_PERFCTR_MAP_SIMD_UOP =3D 0x7e, + A9_PMU_PERFCTR_FLUSH_RESTART_OTHER_NONSPEC =3D 0x84, + A9_PMU_PERFCTR_INST_ALL =3D 0x8c, + A9_PMU_PERFCTR_INST_BRANCH =3D 0x8d, + A9_PMU_PERFCTR_INST_BRANCH_CALL =3D 0x8e, + A9_PMU_PERFCTR_INST_BRANCH_RET =3D 0x8f, + A9_PMU_PERFCTR_INST_BRANCH_TAKEN =3D 0x90, + A9_PMU_PERFCTR_INST_BRANCH_INDIR =3D 0x93, + A9_PMU_PERFCTR_INST_BRANCH_COND =3D 0x94, + A9_PMU_PERFCTR_INST_INT_LD =3D 0x95, + A9_PMU_PERFCTR_INST_INT_ST =3D 0x96, + A9_PMU_PERFCTR_INST_INT_ALU =3D 0x97, + A9_PMU_PERFCTR_INST_SIMD_LD =3D 0x98, + A9_PMU_PERFCTR_INST_SIMD_ST =3D 0x99, + A9_PMU_PERFCTR_INST_SIMD_ALU =3D 0x9a, + A9_PMU_PERFCTR_INST_LDST =3D 0x9b, + A9_PMU_PERFCTR_INST_BARRIER =3D 0x9c, + A9_PMU_PERFCTR_UNKNOWN_9f =3D 0x9f, + A9_PMU_PERFCTR_L1D_TLB_ACCESS =3D 0xa0, + A9_PMU_PERFCTR_L1D_TLB_MISS =3D 0xa1, + A9_PMU_PERFCTR_L1D_CACHE_MISS_ST =3D 0xa2, + A9_PMU_PERFCTR_L1D_CACHE_MISS_LD =3D 0xa3, + A9_PMU_PERFCTR_LD_UNIT_UOP =3D 0xa6, + A9_PMU_PERFCTR_ST_UNIT_UOP =3D 0xa7, + A9_PMU_PERFCTR_L1D_CACHE_WRITEBACK =3D 0xa8, + A9_PMU_PERFCTR_LDST_X64_UOP =3D 0xb1, + A9_PMU_PERFCTR_ATOMIC_OR_EXCLUSIVE_SUCC =3D 0xb3, + A9_PMU_PERFCTR_ATOMIC_OR_EXCLUSIVE_FAIL =3D 0xb4, + A9_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC =3D 0xbf, + A9_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC =3D 0xc0, + A9_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC =3D 0xc1, + A9_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC =3D 0xc4, + A9_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC =3D 0xc5, + A9_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC =3D 0xc6, + A9_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC =3D 0xc8, + A9_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC =3D 0xca, + A9_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC =3D 0xcb, + A9_PMU_PERFCTR_FED_IC_MISS_DEMAND =3D 0xd3, + A9_PMU_PERFCTR_L1I_TLB_MISS_DEMAND =3D 0xd4, + A9_PMU_PERFCTR_MAP_DISPATCH_BUBBLE =3D 0xd6, + A9_PMU_PERFCTR_FETCH_RESTART =3D 0xde, + A9_PMU_PERFCTR_ST_NT_UOP =3D 0xe5, + A9_PMU_PERFCTR_LD_NT_UOP =3D 0xe6, + A9_PMU_PERFCTR_UNKNOWN_f6 =3D 0xf6, + A9_PMU_PERFCTR_UNKNOWN_f7 =3D 0xf7, + A9_PMU_PERFCTR_LAST =3D M1_PMU_CFG_EVENT, + + /* + * From this point onwards, these are not actual HW events, + * but attributes that get stored in hw->config_base. + */ + A9_PMU_CFG_COUNT_USER =3D BIT(8), + A9_PMU_CFG_COUNT_KERNEL =3D BIT(9), +}; + +static const u16 a9_pmu_event_affinity[A9_PMU_PERFCTR_LAST + 1] =3D { + [0 ... A9_PMU_PERFCTR_LAST] =3D ANY_BUT_0_1, + [A9_PMU_PERFCTR_UNKNOWN_1] =3D BIT(7), + [A9_PMU_PERFCTR_CORE_ACTIVE_CYCLE] =3D ANY_BUT_0_1 | BIT(0), + [A9_PMU_PERFCTR_INST_ALL] =3D BIT(7) | BIT(1), + [A9_PMU_PERFCTR_INST_BRANCH] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_INST_BRANCH_CALL] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_INST_BRANCH_RET] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_INST_BRANCH_TAKEN] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_INST_BRANCH_INDIR] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_INST_BRANCH_COND] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_INST_INT_LD] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_INST_INT_ST] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_INST_INT_ALU] =3D BIT(7), + [A9_PMU_PERFCTR_INST_SIMD_LD] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_INST_SIMD_ST] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_INST_SIMD_ALU] =3D BIT(7), + [A9_PMU_PERFCTR_INST_LDST] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_INST_BARRIER] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_UNKNOWN_9f] =3D BIT(7), + [A9_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_UNKNOWN_f6] =3D ONLY_3_5_7, + [A9_PMU_PERFCTR_UNKNOWN_f7] =3D ONLY_3_5_7, +}; + enum m1_pmu_events { M1_PMU_PERFCTR_RETIRE_UOP =3D 0x1, M1_PMU_PERFCTR_CORE_ACTIVE_CYCLE =3D 0x2, @@ -797,6 +900,12 @@ static int a8_pmu_get_event_idx(struct pmu_hw_events *= cpuc, return apple_pmu_get_event_idx(cpuc, event, a8_pmu_event_affinity); } =20 +static int a9_pmu_get_event_idx(struct pmu_hw_events *cpuc, + struct perf_event *event) +{ + return apple_pmu_get_event_idx(cpuc, event, a9_pmu_event_affinity); +} + static int m1_pmu_get_event_idx(struct pmu_hw_events *cpuc, struct perf_event *event) { @@ -986,6 +1095,17 @@ static int a8_pmu_typhoon_init(struct arm_pmu *cpu_pm= u) return apple_pmu_init(cpu_pmu, A7_PMU_NR_COUNTERS); } =20 +static int a9_pmu_twister_init(struct arm_pmu *cpu_pmu) +{ + cpu_pmu->name =3D "apple_twister_pmu"; + cpu_pmu->get_event_idx =3D a9_pmu_get_event_idx; + cpu_pmu->map_event =3D m1_pmu_map_event; + cpu_pmu->reset =3D a7_pmu_reset; + cpu_pmu->start =3D a7_pmu_start; + cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =3D &m1_pmu_events_attr_gr= oup; + return apple_pmu_init(cpu_pmu, A7_PMU_NR_COUNTERS); +} + static int m1_pmu_ice_init(struct arm_pmu *cpu_pmu) { cpu_pmu->name =3D "apple_icestorm_pmu"; @@ -1035,6 +1155,7 @@ static const struct of_device_id m1_pmu_of_device_ids= [] =3D { { .compatible =3D "apple,blizzard-pmu", .data =3D m2_pmu_blizzard_init, }, { .compatible =3D "apple,icestorm-pmu", .data =3D m1_pmu_ice_init, }, { .compatible =3D "apple,firestorm-pmu", .data =3D m1_pmu_fire_init, }, + { .compatible =3D "apple,twister-pmu", .data =3D a9_pmu_twister_init, }, { .compatible =3D "apple,typhoon-pmu", .data =3D a8_pmu_typhoon_init, }, { .compatible =3D "apple,cyclone-pmu", .data =3D a7_pmu_cyclone_init, }, { }, --=20 2.49.0 From nobody Fri Oct 10 04:02:06 2025 Received: from mail-pj1-f52.google.com (mail-pj1-f52.google.com [209.85.216.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C54921DB924; Mon, 16 Jun 2025 01:32:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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[175.159.121.134]) by smtp.googlemail.com with ESMTPSA id d9443c01a7336-2365deb2cedsm49932455ad.163.2025.06.15.18.32.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 15 Jun 2025 18:32:49 -0700 (PDT) From: Nick Chan Date: Mon, 16 Jun 2025 09:32:00 +0800 Subject: [PATCH RESEND v7 11/21] drivers/perf: apple_m1: Add Apple A10/A10X/T2 Support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250616-apple-cpmu-v7-11-df2778a44d5c@gmail.com> References: <20250616-apple-cpmu-v7-0-df2778a44d5c@gmail.com> In-Reply-To: <20250616-apple-cpmu-v7-0-df2778a44d5c@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Sven Peter Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=7477; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=7wE0yzPS1UdR3HX1uhwHr/0JyraXWlDKVwdFlazVm24=; b=owEBbQKS/ZANAwAKAQHKCLemxQgkAcsmYgBoT3QYHzvOmIXt/ETLm/Q9roRZgvm9PbkIKeHbv HB3p5LXB0aJAjMEAAEKAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCaE90GAAKCRABygi3psUI JEykD/4pzILrEIjw4/iHHC6xnFkJyCQ0WfJxC+rxLzn7mc4FR29Sp7kqC7zW7UIl8iFKATdPaw2 KOepVUyQhy6SA4Q2qxBUL7qBF0ascoWLbjMNbfwtqvnzKQW13WYvzgAdMbdfGX+P098Q+s6CKZo rcot5T0/pstG2xSBmy23qoxi813dxQdg3PkUGv9JPPPnPNxTZtca5jctzq5+B4XaoL4i9ipNUKD qDmHZiJjNjTqTGmEFMW7sLQ3N43Z6mAn9FUM3ToQLTQn3Gf4K0T4NNE1ae/66lvajbMkHf7SiGF vzib+/QjcxY2Dn7g4u2P0lIv1cnei33rHNjjtNHRl4tpwFvnqXiios13hWJNojitcexpVMyPnZL OjGatCJBUZ8yJAoBQE9RL4HDMfHMN7QY8Q3a8hZii/GhDp/cw+z++2615iQUCfLx/vHfziUVfLA TBVWqCnfxd3reot5MRV9wfK9+vzoQ9hXqeTP59cCTnl4pHOlXK+QONy5ZcwVZIkj7iL5U/q68Xd aU4BfjCg9bNJ6nfbd74Kooz8Ga3PFQHd/RpDtnBTpnCmWOY+4H6AjZkv187/qfGTCC8yKc7BmtH Bn/bjtHs8tT6FxQ9HlpriJS/FVh3/IsL5UD5YRJKE9I6CPFcd8Q66mXI0LD24WhWO+GvI9P5TrE qiU0WneH/pZmibQ== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 Add support for the CPU PMU found in the Apple A10, A10X, T2 SoCs. Signed-off-by: Nick Chan --- drivers/perf/apple_m1_cpu_pmu.c | 127 ++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 127 insertions(+) diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pm= u.c index e89fe646a849f50615a3dc809e51a6cd95dd9a1b..02abad2239340e75719e989c434= 5d411d55de89a 100644 --- a/drivers/perf/apple_m1_cpu_pmu.c +++ b/drivers/perf/apple_m1_cpu_pmu.c @@ -392,6 +392,115 @@ static const u16 a9_pmu_event_affinity[A9_PMU_PERFCTR= _LAST + 1] =3D { [A9_PMU_PERFCTR_UNKNOWN_f7] =3D ONLY_3_5_7, }; =20 +enum a10_pmu_events { + A10_PMU_PERFCTR_RETIRE_UOP =3D 0x1, + A10_PMU_PERFCTR_CORE_ACTIVE_CYCLE =3D 0x2, + A10_PMU_PERFCTR_L2_TLB_MISS_INSTRUCTION =3D 0xa, + A10_PMU_PERFCTR_L2_TLB_MISS_DATA =3D 0xb, + A10_PMU_PERFCTR_L2C_AGENT_LD =3D 0x1a, + A10_PMU_PERFCTR_L2C_AGENT_LD_MISS =3D 0x1b, + A10_PMU_PERFCTR_L2C_AGENT_ST =3D 0x1c, + A10_PMU_PERFCTR_L2C_AGENT_ST_MISS =3D 0x1d, + A10_PMU_PERFCTR_SCHEDULE_UOP =3D 0x52, + A10_PMU_PERFCTR_MAP_REWIND =3D 0x75, + A10_PMU_PERFCTR_MAP_STALL =3D 0x76, + A10_PMU_PERFCTR_MAP_INT_UOP =3D 0x7c, + A10_PMU_PERFCTR_MAP_LDST_UOP =3D 0x7d, + A10_PMU_PERFCTR_MAP_SIMD_UOP =3D 0x7e, + A10_PMU_PERFCTR_FLUSH_RESTART_OTHER_NONSPEC =3D 0x84, + A10_PMU_PERFCTR_INST_ALL =3D 0x8c, + A10_PMU_PERFCTR_INST_BRANCH =3D 0x8d, + A10_PMU_PERFCTR_INST_BRANCH_CALL =3D 0x8e, + A10_PMU_PERFCTR_INST_BRANCH_RET =3D 0x8f, + A10_PMU_PERFCTR_INST_BRANCH_TAKEN =3D 0x90, + A10_PMU_PERFCTR_INST_BRANCH_INDIR =3D 0x93, + A10_PMU_PERFCTR_INST_BRANCH_COND =3D 0x94, + A10_PMU_PERFCTR_INST_INT_LD =3D 0x95, + A10_PMU_PERFCTR_INST_INT_ST =3D 0x96, + A10_PMU_PERFCTR_INST_INT_ALU =3D 0x97, + A10_PMU_PERFCTR_INST_SIMD_LD =3D 0x98, + A10_PMU_PERFCTR_INST_SIMD_ST =3D 0x99, + A10_PMU_PERFCTR_INST_SIMD_ALU =3D 0x9a, + A10_PMU_PERFCTR_INST_LDST =3D 0x9b, + A10_PMU_PERFCTR_INST_BARRIER =3D 0x9c, + A10_PMU_PERFCTR_UNKNOWN_9f =3D 0x9f, + A10_PMU_PERFCTR_L1D_TLB_ACCESS =3D 0xa0, + A10_PMU_PERFCTR_L1D_TLB_MISS =3D 0xa1, + A10_PMU_PERFCTR_L1D_CACHE_MISS_ST =3D 0xa2, + A10_PMU_PERFCTR_L1D_CACHE_MISS_LD =3D 0xa3, + A10_PMU_PERFCTR_LD_UNIT_UOP =3D 0xa6, + A10_PMU_PERFCTR_ST_UNIT_UOP =3D 0xa7, + A10_PMU_PERFCTR_L1D_CACHE_WRITEBACK =3D 0xa8, + A10_PMU_PERFCTR_LDST_X64_UOP =3D 0xb1, + A10_PMU_PERFCTR_ATOMIC_OR_EXCLUSIVE_SUCC =3D 0xb3, + A10_PMU_PERFCTR_ATOMIC_OR_EXCLUSIVE_FAIL =3D 0xb4, + A10_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC =3D 0xbf, + A10_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC =3D 0xc0, + A10_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC =3D 0xc1, + A10_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC =3D 0xc4, + A10_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC =3D 0xc5, + A10_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC =3D 0xc6, + A10_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC =3D 0xc8, + A10_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC =3D 0xca, + A10_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC =3D 0xcb, + A10_PMU_PERFCTR_FED_IC_MISS_DEMAND =3D 0xd3, + A10_PMU_PERFCTR_L1I_TLB_MISS_DEMAND =3D 0xd4, + A10_PMU_PERFCTR_MAP_DISPATCH_BUBBLE =3D 0xd6, + A10_PMU_PERFCTR_L1I_CACHE_MISS_DEMAND =3D 0xdb, + A10_PMU_PERFCTR_FETCH_RESTART =3D 0xde, + A10_PMU_PERFCTR_ST_NT_UOP =3D 0xe5, + A10_PMU_PERFCTR_LD_NT_UOP =3D 0xe6, + A10_PMU_PERFCTR_UNKNOWN_f5 =3D 0xf5, + A10_PMU_PERFCTR_UNKNOWN_f6 =3D 0xf6, + A10_PMU_PERFCTR_UNKNOWN_f7 =3D 0xf7, + A10_PMU_PERFCTR_UNKNOWN_f8 =3D 0xf8, + A10_PMU_PERFCTR_UNKNOWN_fd =3D 0xfd, + A10_PMU_PERFCTR_LAST =3D M1_PMU_CFG_EVENT, + + /* + * From this point onwards, these are not actual HW events, + * but attributes that get stored in hw->config_base. + */ + A10_PMU_CFG_COUNT_USER =3D BIT(8), + A10_PMU_CFG_COUNT_KERNEL =3D BIT(9), +}; + +static const u16 a10_pmu_event_affinity[A10_PMU_PERFCTR_LAST + 1] =3D { + [0 ... A10_PMU_PERFCTR_LAST] =3D ANY_BUT_0_1, + [A10_PMU_PERFCTR_RETIRE_UOP] =3D BIT(7), + [A10_PMU_PERFCTR_CORE_ACTIVE_CYCLE] =3D ANY_BUT_0_1 | BIT(0), + [A10_PMU_PERFCTR_INST_ALL] =3D BIT(7) | BIT(1), + [A10_PMU_PERFCTR_INST_BRANCH] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_INST_BRANCH_CALL] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_INST_BRANCH_RET] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_INST_BRANCH_TAKEN] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_INST_BRANCH_INDIR] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_INST_BRANCH_COND] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_INST_INT_LD] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_INST_INT_ST] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_INST_INT_ALU] =3D BIT(7), + [A10_PMU_PERFCTR_INST_SIMD_LD] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_INST_SIMD_ST] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_INST_SIMD_ALU] =3D BIT(7), + [A10_PMU_PERFCTR_INST_LDST] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_INST_BARRIER] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_UNKNOWN_9f] =3D BIT(7), + [A10_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_UNKNOWN_f5] =3D ONLY_2_4_6, + [A10_PMU_PERFCTR_UNKNOWN_f6] =3D ONLY_2_4_6, + [A10_PMU_PERFCTR_UNKNOWN_f7] =3D ONLY_2_4_6, + [A10_PMU_PERFCTR_UNKNOWN_f8] =3D ONLY_2_TO_7, + [A10_PMU_PERFCTR_UNKNOWN_fd] =3D ONLY_2_4_6, +}; + enum m1_pmu_events { M1_PMU_PERFCTR_RETIRE_UOP =3D 0x1, M1_PMU_PERFCTR_CORE_ACTIVE_CYCLE =3D 0x2, @@ -906,6 +1015,12 @@ static int a9_pmu_get_event_idx(struct pmu_hw_events = *cpuc, return apple_pmu_get_event_idx(cpuc, event, a9_pmu_event_affinity); } =20 +static int a10_pmu_get_event_idx(struct pmu_hw_events *cpuc, + struct perf_event *event) +{ + return apple_pmu_get_event_idx(cpuc, event, a10_pmu_event_affinity); +} + static int m1_pmu_get_event_idx(struct pmu_hw_events *cpuc, struct perf_event *event) { @@ -1106,6 +1221,17 @@ static int a9_pmu_twister_init(struct arm_pmu *cpu_p= mu) return apple_pmu_init(cpu_pmu, A7_PMU_NR_COUNTERS); } =20 +static int a10_pmu_fusion_init(struct arm_pmu *cpu_pmu) +{ + cpu_pmu->name =3D "apple_fusion_pmu"; + cpu_pmu->get_event_idx =3D a10_pmu_get_event_idx; + cpu_pmu->map_event =3D m1_pmu_map_event; + cpu_pmu->reset =3D m1_pmu_reset; + cpu_pmu->start =3D a7_pmu_start; + cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =3D &m1_pmu_events_attr_gr= oup; + return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); +} + static int m1_pmu_ice_init(struct arm_pmu *cpu_pmu) { cpu_pmu->name =3D "apple_icestorm_pmu"; @@ -1155,6 +1281,7 @@ static const struct of_device_id m1_pmu_of_device_ids= [] =3D { { .compatible =3D "apple,blizzard-pmu", .data =3D m2_pmu_blizzard_init, }, { .compatible =3D "apple,icestorm-pmu", .data =3D m1_pmu_ice_init, }, { .compatible =3D "apple,firestorm-pmu", .data =3D m1_pmu_fire_init, }, + { .compatible =3D "apple,fusion-pmu", .data =3D a10_pmu_fusion_init, }, { .compatible =3D "apple,twister-pmu", .data =3D a9_pmu_twister_init, }, { .compatible =3D "apple,typhoon-pmu", .data =3D a8_pmu_typhoon_init, }, { .compatible =3D "apple,cyclone-pmu", .data =3D a7_pmu_cyclone_init, }, --=20 2.49.0 From nobody Fri Oct 10 04:02:06 2025 Received: from mail-pl1-f176.google.com (mail-pl1-f176.google.com [209.85.214.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A39A627E7DB; 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[175.159.121.134]) by smtp.googlemail.com with ESMTPSA id d9443c01a7336-2365deb2cedsm49932455ad.163.2025.06.15.18.32.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 15 Jun 2025 18:32:53 -0700 (PDT) From: Nick Chan Date: Mon, 16 Jun 2025 09:32:01 +0800 Subject: [PATCH RESEND v7 12/21] drivers/perf: apple_m1: Add Apple A11 Support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250616-apple-cpmu-v7-12-df2778a44d5c@gmail.com> References: <20250616-apple-cpmu-v7-0-df2778a44d5c@gmail.com> In-Reply-To: <20250616-apple-cpmu-v7-0-df2778a44d5c@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Sven Peter Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=7991; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=Raj3dM6TrZPNDRlEodrAbzttSnwOw6xo+GsUbrfYvRs=; b=owEBbQKS/ZANAwAKAQHKCLemxQgkAcsmYgBoT3QYmb10V25U0s8mQYIoJ/IGo47JpveNptEQ6 sDXoKqby+qJAjMEAAEKAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCaE90GAAKCRABygi3psUI JEi/D/9XL4oC5yFae4biH5yUmBpbZmmFE5iHNM7DJAapGzjPWAD3sRL79JH9uhNjfAcZqOpVl0G HBA68dhOFpGPZCyC4v1QNycBnVHrlX8zhzqQRo7CODrfQZhARa3LhS49tSZ9I3RigRh0BWYqNLW O/yHjgROQ3tGyfTXe8A52HgIlxb/CCjwwIi6cJ1khowOUi1PpVnLG2hlXeWH3XgURN0wln20BWI N/8zF/lDWefVNoSDwLEyMI2uomaZtxy6FSa5SEaD3QNtrkFXPoefkrbC6sVEWSXmpNkr3f3KCUC oF69PhRbWTV5S8xD2MYHbY35GUBiQKcvFx1xohyNagXZa0Eh0k/b4OssDmYTMAXPDfYBbdTO08v YTvGw5n+lbsW/t0zDwEuoQ5oRlCoIsnxiE7m7QWvcllR1T6wohmgWEVONpCUC5uX5Cd2IYLRyvA ntgjvFjR3mv3MszTPrbA6eeebXdMiMoDIVnVkYLod0v2mQiFGdiJGOcty69azCQbgcznITVdMi/ 5N4ikAosWkgib/U+0pMPiY6hin/AUbgZNQ9U0xMQl1tJYm9tGA+zkzoGbZU9OAczP6RkXuQSjxm 2YMkOpesNY7eU+Yr63VKRyDksEFpwSu7v4jwFkoGLKCjCKUZf6DLq3RPWIQUPzZcnFrugui1v/y 7hhuvnJlJU95f8Q== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 Add support for the CPU PMU found attached to the performance and efficiency cores of the Apple A11 SoCs. This PMU can deliver its interrupt via IRQ or FIQ. Use FIQ as that is faster. Signed-off-by: Nick Chan --- drivers/perf/apple_m1_cpu_pmu.c | 137 ++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 137 insertions(+) diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pm= u.c index 02abad2239340e75719e989c4345d411d55de89a..81443e5158b25e753b836ae83f4= 2820d8d072418 100644 --- a/drivers/perf/apple_m1_cpu_pmu.c +++ b/drivers/perf/apple_m1_cpu_pmu.c @@ -501,6 +501,113 @@ static const u16 a10_pmu_event_affinity[A10_PMU_PERFC= TR_LAST + 1] =3D { [A10_PMU_PERFCTR_UNKNOWN_fd] =3D ONLY_2_4_6, }; =20 +enum a11_pmu_events { + A11_PMU_PERFCTR_RETIRE_UOP =3D 0x1, + A11_PMU_PERFCTR_CORE_ACTIVE_CYCLE =3D 0x2, + A11_PMU_PERFCTR_L2_TLB_MISS_INSTRUCTION =3D 0xa, + A11_PMU_PERFCTR_L2_TLB_MISS_DATA =3D 0xb, + A11_PMU_PERFCTR_SCHEDULE_UOP =3D 0x52, + A11_PMU_PERFCTR_MAP_REWIND =3D 0x75, + A11_PMU_PERFCTR_MAP_STALL =3D 0x76, + A11_PMU_PERFCTR_MAP_INT_UOP =3D 0x7c, + A11_PMU_PERFCTR_MAP_LDST_UOP =3D 0x7d, + A11_PMU_PERFCTR_MAP_SIMD_UOP =3D 0x7e, + A11_PMU_PERFCTR_FLUSH_RESTART_OTHER_NONSPEC =3D 0x84, + A11_PMU_PERFCTR_INST_A32 =3D 0x8a, + A11_PMU_PERFCTR_INST_T32 =3D 0x8b, + A11_PMU_PERFCTR_INST_ALL =3D 0x8c, + A11_PMU_PERFCTR_INST_BRANCH =3D 0x8d, + A11_PMU_PERFCTR_INST_BRANCH_CALL =3D 0x8e, + A11_PMU_PERFCTR_INST_BRANCH_RET =3D 0x8f, + A11_PMU_PERFCTR_INST_BRANCH_TAKEN =3D 0x90, + A11_PMU_PERFCTR_INST_BRANCH_INDIR =3D 0x93, + A11_PMU_PERFCTR_INST_BRANCH_COND =3D 0x94, + A11_PMU_PERFCTR_INST_INT_LD =3D 0x95, + A11_PMU_PERFCTR_INST_INT_ST =3D 0x96, + A11_PMU_PERFCTR_INST_INT_ALU =3D 0x97, + A11_PMU_PERFCTR_INST_SIMD_LD =3D 0x98, + A11_PMU_PERFCTR_INST_SIMD_ST =3D 0x99, + A11_PMU_PERFCTR_INST_SIMD_ALU =3D 0x9a, + A11_PMU_PERFCTR_INST_LDST =3D 0x9b, + A11_PMU_PERFCTR_INST_BARRIER =3D 0x9c, + A11_PMU_PERFCTR_UNKNOWN_9f =3D 0x9f, + A11_PMU_PERFCTR_L1D_TLB_ACCESS =3D 0xa0, + A11_PMU_PERFCTR_L1D_TLB_MISS =3D 0xa1, + A11_PMU_PERFCTR_L1D_CACHE_MISS_ST =3D 0xa2, + A11_PMU_PERFCTR_L1D_CACHE_MISS_LD =3D 0xa3, + A11_PMU_PERFCTR_LD_UNIT_UOP =3D 0xa6, + A11_PMU_PERFCTR_ST_UNIT_UOP =3D 0xa7, + A11_PMU_PERFCTR_L1D_CACHE_WRITEBACK =3D 0xa8, + A11_PMU_PERFCTR_LDST_X64_UOP =3D 0xb1, + A11_PMU_PERFCTR_ATOMIC_OR_EXCLUSIVE_SUCC =3D 0xb3, + A11_PMU_PERFCTR_ATOMIC_OR_EXCLUSIVE_FAIL =3D 0xb4, + A11_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC =3D 0xbf, + A11_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC =3D 0xc0, + A11_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC =3D 0xc1, + A11_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC =3D 0xc4, + A11_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC =3D 0xc5, + A11_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC =3D 0xc6, + A11_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC =3D 0xc8, + A11_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC =3D 0xca, + A11_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC =3D 0xcb, + A11_PMU_PERFCTR_FED_IC_MISS_DEMAND =3D 0xd3, + A11_PMU_PERFCTR_L1I_TLB_MISS_DEMAND =3D 0xd4, + A11_PMU_PERFCTR_MAP_DISPATCH_BUBBLE =3D 0xd6, + A11_PMU_PERFCTR_L1I_CACHE_MISS_DEMAND =3D 0xdb, + A11_PMU_PERFCTR_FETCH_RESTART =3D 0xde, + A11_PMU_PERFCTR_ST_NT_UOP =3D 0xe5, + A11_PMU_PERFCTR_LD_NT_UOP =3D 0xe6, + A11_PMU_PERFCTR_UNKNOWN_f5 =3D 0xf5, + A11_PMU_PERFCTR_UNKNOWN_f6 =3D 0xf6, + A11_PMU_PERFCTR_UNKNOWN_f7 =3D 0xf7, + A11_PMU_PERFCTR_UNKNOWN_f8 =3D 0xf8, + A11_PMU_PERFCTR_UNKNOWN_fd =3D 0xfd, + A11_PMU_PERFCTR_LAST =3D M1_PMU_CFG_EVENT, + + /* + * From this point onwards, these are not actual HW events, + * but attributes that get stored in hw->config_base. + */ + A11_PMU_CFG_COUNT_USER =3D BIT(8), + A11_PMU_CFG_COUNT_KERNEL =3D BIT(9), +}; + +static const u16 a11_pmu_event_affinity[A11_PMU_PERFCTR_LAST + 1] =3D { + [0 ... A11_PMU_PERFCTR_LAST] =3D ANY_BUT_0_1, + [A11_PMU_PERFCTR_RETIRE_UOP] =3D BIT(7), + [A11_PMU_PERFCTR_CORE_ACTIVE_CYCLE] =3D ANY_BUT_0_1 | BIT(0), + [A11_PMU_PERFCTR_INST_ALL] =3D BIT(7) | BIT(1), + [A11_PMU_PERFCTR_INST_BRANCH] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_BRANCH_CALL] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_BRANCH_RET] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_BRANCH_TAKEN] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_BRANCH_INDIR] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_BRANCH_COND] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_INT_LD] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_INT_ST] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_INT_ALU] =3D BIT(7), + [A11_PMU_PERFCTR_INST_SIMD_LD] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_SIMD_ST] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_SIMD_ALU] =3D BIT(7), + [A11_PMU_PERFCTR_INST_LDST] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_BARRIER] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_UNKNOWN_9f] =3D BIT(7), + [A11_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_UNKNOWN_f5] =3D ONLY_2_4_6, + [A11_PMU_PERFCTR_UNKNOWN_f6] =3D ONLY_2_4_6, + [A11_PMU_PERFCTR_UNKNOWN_f7] =3D ONLY_2_4_6, + [A11_PMU_PERFCTR_UNKNOWN_f8] =3D ONLY_2_TO_7, + [A11_PMU_PERFCTR_UNKNOWN_fd] =3D ONLY_2_4_6, +}; + enum m1_pmu_events { M1_PMU_PERFCTR_RETIRE_UOP =3D 0x1, M1_PMU_PERFCTR_CORE_ACTIVE_CYCLE =3D 0x2, @@ -1021,6 +1128,12 @@ static int a10_pmu_get_event_idx(struct pmu_hw_event= s *cpuc, return apple_pmu_get_event_idx(cpuc, event, a10_pmu_event_affinity); } =20 +static int a11_pmu_get_event_idx(struct pmu_hw_events *cpuc, + struct perf_event *event) +{ + return apple_pmu_get_event_idx(cpuc, event, a11_pmu_event_affinity); +} + static int m1_pmu_get_event_idx(struct pmu_hw_events *cpuc, struct perf_event *event) { @@ -1232,6 +1345,28 @@ static int a10_pmu_fusion_init(struct arm_pmu *cpu_p= mu) return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); } =20 +static int a11_pmu_monsoon_init(struct arm_pmu *cpu_pmu) +{ + cpu_pmu->name =3D "apple_monsoon_pmu"; + cpu_pmu->get_event_idx =3D a11_pmu_get_event_idx; + cpu_pmu->map_event =3D m1_pmu_map_event; + cpu_pmu->reset =3D m1_pmu_reset; + cpu_pmu->start =3D m1_pmu_start; + cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =3D &m1_pmu_events_attr_gr= oup; + return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); +} + +static int a11_pmu_mistral_init(struct arm_pmu *cpu_pmu) +{ + cpu_pmu->name =3D "apple_mistral_pmu"; + cpu_pmu->get_event_idx =3D a11_pmu_get_event_idx; + cpu_pmu->map_event =3D m1_pmu_map_event; + cpu_pmu->reset =3D m1_pmu_reset; + cpu_pmu->start =3D m1_pmu_start; + cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =3D &m1_pmu_events_attr_gr= oup; + return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); +} + static int m1_pmu_ice_init(struct arm_pmu *cpu_pmu) { cpu_pmu->name =3D "apple_icestorm_pmu"; @@ -1281,6 +1416,8 @@ static const struct of_device_id m1_pmu_of_device_ids= [] =3D { { .compatible =3D "apple,blizzard-pmu", .data =3D m2_pmu_blizzard_init, }, { .compatible =3D "apple,icestorm-pmu", .data =3D m1_pmu_ice_init, }, { .compatible =3D "apple,firestorm-pmu", .data =3D m1_pmu_fire_init, }, + { .compatible =3D "apple,monsoon-pmu", .data =3D a11_pmu_monsoon_init, }, + { .compatible =3D "apple,mistral-pmu", .data =3D a11_pmu_mistral_init, }, { .compatible =3D "apple,fusion-pmu", .data =3D a10_pmu_fusion_init, }, { .compatible =3D "apple,twister-pmu", .data =3D a9_pmu_twister_init, }, { .compatible =3D "apple,typhoon-pmu", .data =3D a8_pmu_typhoon_init, }, --=20 2.49.0 From nobody Fri Oct 10 04:02:06 2025 Received: from mail-pl1-f174.google.com (mail-pl1-f174.google.com [209.85.214.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 96D8828151E; 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[175.159.121.134]) by smtp.googlemail.com with ESMTPSA id d9443c01a7336-2365deb2cedsm49932455ad.163.2025.06.15.18.32.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 15 Jun 2025 18:32:56 -0700 (PDT) From: Nick Chan Date: Mon, 16 Jun 2025 09:32:02 +0800 Subject: [PATCH RESEND v7 13/21] arm64: dts: apple: s5l8960x: Add CPU PMU nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250616-apple-cpmu-v7-13-df2778a44d5c@gmail.com> References: <20250616-apple-cpmu-v7-0-df2778a44d5c@gmail.com> In-Reply-To: <20250616-apple-cpmu-v7-0-df2778a44d5c@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Sven Peter Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=914; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=LZ5pN5iqWz3OCuzIiw27nZWBzYhm/oPtBhWwt5qbJRc=; b=owEBbQKS/ZANAwAKAQHKCLemxQgkAcsmYgBoT3QYaNhoHNVpoP2f2HSS8k4EzqiYo9wg7u9tE CJZOqsVlqCJAjMEAAEKAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCaE90GAAKCRABygi3psUI JLN4D/0XYiURgf560pd5iqzLJHOqI/H1/M8LUyqN0RZfrm2CAKpRHah6xfBnNtOQbAo0ZJARO9w 2jdbUvU1Aj9DWOjiRLM5AwS1l6C5n4kyAcn2OtRFgQlAhjgwpw9Mhy7TGwhpfSA+QWZvg62Qc7A VA3wbGfk/pgaOdbrEZ13wxie4Ats7ZOPyJck6YRGeHChb8onEOsPQoBprEt5byAGO7z89zaBOa+ 028KIs6+OZOhmv6I2FvvjhLluiLjphCs8QM89gJuL704Gt1UqcstaMqfRyWflt2UdyKNZHCDA/O suhAfiU+MpVBgXC1I7GSFiR7oHSc7jl02GIN2tD/QqUBlMuHCBBG4XZbF6R5T0rAa/8yGscCgC5 vqFAPyWGOgjsp/8l8iHhMKTOI/bW8L/ZP3vOB8kbdPDaCbZ+yqVT6hgM8BKUbG6U1MKxkj4qz5i jnhF0MxPUcOHcmP9xF0mCK2CM17obf3mBHACb+87D3v1zEXkbEn10913GE72DAGkxiWbfHvkq1/ 0GdlXm6h3aejsyTiVEIaJFiIjMIxbmZ+67QWNRqERjUsfbLrHK7ak+lmhNFzJ8kz/QNcnf1pTcs 20aj7HHtsBXThGqOfGfLYXwU+vJqP2KZSaqcaCbnr/jvuZAjCxoNclniNzNtrCf8fs+6tGnIkiH r/dvfmOymQjqd6Q== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 Add CPU PMU nodes for Apple A7 SoC. Signed-off-by: Nick Chan --- arch/arm64/boot/dts/apple/s5l8960x.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/apple/s5l8960x.dtsi b/arch/arm64/boot/dts/= apple/s5l8960x.dtsi index d820b0e430507f681a5f2aa13a498be98080e1db..62d528d4b7204af28b66a90d68e= 27e1c78e2df26 100644 --- a/arch/arm64/boot/dts/apple/s5l8960x.dtsi +++ b/arch/arm64/boot/dts/apple/s5l8960x.dtsi @@ -138,6 +138,14 @@ timer { interrupts =3D , ; }; + + pmu { + compatible =3D "apple,cyclone-pmu"; + interrupt-parent =3D <&aic>; + interrupts =3D , + ; + interrupt-affinity =3D <&cpu0 &cpu1>; + }; }; =20 #include "s5l8960x-pmgr.dtsi" --=20 2.49.0 From nobody Fri Oct 10 04:02:06 2025 Received: from mail-pl1-f178.google.com (mail-pl1-f178.google.com [209.85.214.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 823BD283FD3; Mon, 16 Jun 2025 01:33:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Signed-off-by: Nick Chan --- arch/arm64/boot/dts/apple/t7000.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t7000.dtsi b/arch/arm64/boot/dts/app= le/t7000.dtsi index 85a34dc7bc01088167d33d7b7e1cdb78161c46d8..f1415f50cb150ce1d33999c8172= 43c3dc9184199 100644 --- a/arch/arm64/boot/dts/apple/t7000.dtsi +++ b/arch/arm64/boot/dts/apple/t7000.dtsi @@ -193,6 +193,14 @@ timer { interrupts =3D , ; }; + + pmu { + compatible =3D "apple,typhoon-pmu"; + interrupt-parent =3D <&aic>; + interrupts =3D , + ; + interrupt-affinity =3D <&cpu0 &cpu1>; + }; }; =20 #include "t7000-pmgr.dtsi" --=20 2.49.0 From nobody Fri Oct 10 04:02:06 2025 Received: from mail-pl1-f176.google.com (mail-pl1-f176.google.com [209.85.214.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 79235283FFC; Mon, 16 Jun 2025 01:33:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.176 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750037585; cv=none; b=ZlzuIE9rXFPpTL3NLbi4UQiI3nThpp48Pmb6b3yuG9oTE1fLw4GLRuNolhqLLNM/XOJRomCBtcHt+l5a+8HV7xoBAIHCrU8QEyfa00unOj6MCJDV4uoXijSLsaqthCBR2S/6z4TbEAs3c3K0AgKBcx7pMN6bQugGW2TMsPb/5YM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750037585; c=relaxed/simple; bh=/9xxkCL20iFcrQUCvIdlPD0ncxR9ZewCh+wmud58YcU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=mOFw5WqniG3bbSez7lhPSgJ9hBWsvuReH8coQaZu5iZ+mDYapMaBTlh3rlhOuV4RubtSAm5IzQ9wWrW7nRH4usDkFZPdqNwTy0TXw63LQt+HEA93EB9QxTuAJIn0szgkvd/xX/GGvA83U12jTRwQGNQ81JKZTBgr3S1imNGxccs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=M9JyCQMx; arc=none smtp.client-ip=209.85.214.176 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="M9JyCQMx" Received: by mail-pl1-f176.google.com with SMTP id d9443c01a7336-234fcadde3eso49214985ad.0; Sun, 15 Jun 2025 18:33:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1750037583; x=1750642383; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=t22CBONJmB65GQP7nsD4ofUIJ4+sf0vAxHh7+1UHNU4=; b=M9JyCQMxY+rPvZw1+wgzxnSlw836TrD/Us3B9ZCe9dtV//ySciNT4cDaJCLY0Zp0CM 08a6V+ZdPZCuGZozllphDpd03i3rQEPx4k/NlMa3sfKBvUBtgKGxjM2vDr013sJ2DwMh 1jloarQcz/115vxCVbDjIJwiXfNRUFsNJ/DWFs0CLefY0ZdM3eg6hIIaH7kEhJBvUXyO 9CrT92fLXbvW1OuajMf0VN2Eopq6va7bgTjcu8dPD55ghcjnCBxW87DqymqoXViuOKVC 9fk2w3qNqR7i8GnVKUOcQDWNQ6qlQL0JM8FAnOnxF2l8jASiRsHtbAUW3wNWSLsTgJHo Mu8g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1750037583; x=1750642383; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=t22CBONJmB65GQP7nsD4ofUIJ4+sf0vAxHh7+1UHNU4=; b=Vk4TJrQKNpu/gyCSDaj+yix3oRFa9doADwgXMzpQUg8LOo/CLyvqr1ZmtAoPA3VRQN 1ejwxcDyooi/bQBFcfnTC+uV+oieCLiDy/lsBQWAsQ7rg06TpxICW7SfjIfTCub+rVG0 XfwClWNkvGI6caNtoISZ+E8s8HaER+FWlf4duqLJuJjBEznNs4oJaEFqMDIjAQODjg73 /J35shOsJgtU7xxL5MiWH68t+H84AtngrH6DgrT/L6up1PWONM1plPYpmAKHLNjxJrhl v/+y6osvSife3C7JHFMhnHh6tT2EWD4ssnWE9/K3VKyUk09tIusm/1Qazxy5FPQihJ1k HXOg== X-Forwarded-Encrypted: i=1; AJvYcCUT8POVHQTQmUR/I4OLKU3ZNP0K8dmWx5D+4btVyX6nIkXH0Vw5GYeksTU9+3cv59Tfx1eUfh1XAxgb@vger.kernel.org, AJvYcCV94jvTAXTYsHOiJLgQHeSMjjuxyYwhFyk2nRAXNnKBnzY6BsCvANKiz+nMWR06igMIRj/S69yiwPIiUMo8x/l9uQ==@vger.kernel.org, AJvYcCXVwyhvYQVVF06Iyn3ouBbtu5nqnpYMvxlz3NFc5OGemQ33wBoz8RoFNtuLZeUshRLjfIHwEJkHPf3IagnC@vger.kernel.org X-Gm-Message-State: AOJu0YzPMTgVsawTaEvd03nvTSPC6lCVi8KIK88UL3nvyh+m/6HuplzL 2aNTdAQT84kIthl5Eq1Cy2xn6GH1FkJ/0jP9xyf0gorO+gAMhdBAmL9hUXZ4pA== X-Gm-Gg: ASbGncu7568rT0XLAVS85xC+sUAUsxlSzCjiuEh4JrrK1co4hVgkUSzeI5Mr9+fdmaW Nz1UlKpdU2BgRUUK20qsnWgzSZpVHI8s5HLEb9rovp834R8UYGj36d24ztwUexJ4nSlaRsRc7mZ vO/kFzT6xOuYfohw0tbnO3tVOa0rcHAZYoSonA4J7Hkh5POnB0RvL/y6miGcnrCCVZ9lWE9czcg QdJiJz6Vh1KH/70A1RK5QFXg9TpwTrf2Por7kdIk4gD/pF4fovyTpFs26SaSjKhBtetVEt3kdaD QouGsOeYtf16uVrQltrosjSGu9kbrzvEc+/oK7Zh57BTRM9HLHqutHfCBcItN4Z4LsBUQ6z6KV9 Y8W0= X-Google-Smtp-Source: AGHT+IHy5nCDE1jMX7dMgjCgj5ZwKnKsJR/VWO4k4I2j18iZ2axryYBEpSYK4EN4u1t6tFlZ5HxWEQ== X-Received: by 2002:a17:902:d4d0:b0:234:db06:ac0 with SMTP id d9443c01a7336-2366b3c3cdfmr109470005ad.45.1750037583466; Sun, 15 Jun 2025 18:33:03 -0700 (PDT) Received: from [127.0.1.1] (wf121-134.ust.hk. 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Signed-off-by: Nick Chan --- arch/arm64/boot/dts/apple/t7001.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t7001.dtsi b/arch/arm64/boot/dts/app= le/t7001.dtsi index 8e2c67e19c4167fc6639458ce79588e153336603..fca0a100dfd7b29086735d36fec= 0db51144da456 100644 --- a/arch/arm64/boot/dts/apple/t7001.dtsi +++ b/arch/arm64/boot/dts/apple/t7001.dtsi @@ -183,6 +183,15 @@ timer { interrupts =3D , ; }; + + pmu { + compatible =3D "apple,typhoon-pmu"; + interrupt-parent =3D <&aic>; + interrupts =3D , + , + ; + interrupt-affinity =3D <&cpu0 &cpu1 &cpu2>; + }; }; =20 #include "t7001-pmgr.dtsi" --=20 2.49.0 From nobody Fri Oct 10 04:02:06 2025 Received: from mail-pl1-f170.google.com (mail-pl1-f170.google.com [209.85.214.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4535C284B41; Mon, 16 Jun 2025 01:33:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Signed-off-by: Nick Chan --- arch/arm64/boot/dts/apple/s800-0-3.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/apple/s800-0-3.dtsi b/arch/arm64/boot/dts/= apple/s800-0-3.dtsi index c0e9ae45627c8150bc0ddcdc1e6ab65d52fa7219..56ac6e7f3803a16beacc7476426= 2b02c75a96fce 100644 --- a/arch/arm64/boot/dts/apple/s800-0-3.dtsi +++ b/arch/arm64/boot/dts/apple/s800-0-3.dtsi @@ -167,6 +167,14 @@ timer { interrupts =3D , ; }; + + pmu { + compatible =3D "apple,twister-pmu"; + interrupt-parent =3D <&aic>; + interrupts =3D , + ; + interrupt-affinity =3D <&cpu0 &cpu1>; + }; }; =20 #include "s800-0-3-pmgr.dtsi" --=20 2.49.0 From nobody Fri Oct 10 04:02:06 2025 Received: from mail-pl1-f177.google.com (mail-pl1-f177.google.com [209.85.214.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 244E828541B; Mon, 16 Jun 2025 01:33:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Signed-off-by: Nick Chan --- arch/arm64/boot/dts/apple/s8001.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/apple/s8001.dtsi b/arch/arm64/boot/dts/app= le/s8001.dtsi index d56d49c048bbf55e5f2edf40f6fd1fcff6342a9f..33760c60a9189df5491256f81db= 7f413cada27a7 100644 --- a/arch/arm64/boot/dts/apple/s8001.dtsi +++ b/arch/arm64/boot/dts/apple/s8001.dtsi @@ -209,6 +209,14 @@ timer { interrupts =3D , ; }; + + pmu { + compatible =3D "apple,twister-pmu"; + interrupt-parent =3D <&aic>; + interrupts =3D , + ; + interrupt-affinity =3D <&cpu0 &cpu1>; + }; }; =20 #include "s8001-pmgr.dtsi" --=20 2.49.0 From nobody Fri Oct 10 04:02:06 2025 Received: from mail-pl1-f180.google.com (mail-pl1-f180.google.com [209.85.214.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 719492857DD; Mon, 16 Jun 2025 01:33:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.180 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750037595; cv=none; b=BSB3aDDq6yxCRtjySTtBHY8Ay8/g7yurEf0iLD/0I+ReenFGOPFIGxGcCArCEvB25hPUt8yPL/jO230txhoC3h6glt3SzmRPml3sIlghoW8sxpxlP27SQzfIZkzvM/EuaJnAOnWze+zmjU/qFVNv9jpd+xOXZigPr/txG0GnILU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750037595; c=relaxed/simple; bh=kZviMfYtRCR7gR5VoFkDRwcKeTgAqfWp35C3egDQLf8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=gi8rstE2A0yGOa4TvYqLQ6Ci3/F58ot7zrNJVH2KWVWLjRvHPxUAIwmiRa8/9GXfdpDy1TpigBhyjxJmnfZ27h7yAWMxHh0EgmQieYMWGohBytVx7v4P4ABkk4UWPGP6Xz19y62hD7tBlta3mT8DxNb8Vj552gkqkGWehfYAnm8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=NkRVjGcn; arc=none smtp.client-ip=209.85.214.180 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="NkRVjGcn" Received: by mail-pl1-f180.google.com with SMTP id d9443c01a7336-236192f8770so26410415ad.0; Sun, 15 Jun 2025 18:33:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1750037593; x=1750642393; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=65yvptSdo6oSSwoGRF8EUfcgAwuQwDq5kFTQAdR/3Jo=; b=NkRVjGcn1Q76zCvBdfTnIWS3F1oDHMmajzQ7gg14i/JziwNrFaLEBM9CDBFBkMgApf Uhn9qVAAm64Nmsfrx+WzwTOelvNQJ1ArOzdU9PpVz+H+RJ2s8xvl3kd+v/5AWqPyPv6u 15QM9l2wjYeuX5ZMyqpXP4HA5k6POrEQ36rM65gq1fJCKMGg/RDk/uwjtwSPGLu9Uz7K +cI8ciPWS1FukSArRNMABf0p1qctb8LjsQnSGfEz7rX9SuKZFJ/3D0hOaGEqYgiY7ePh ZqtK13BGqVNsBWV0G1Tcxm1L0HHZ0VgjFZzsCeRnT1+HhEY+wpESHgE/zUuNSM45mVaY 2Lhw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1750037593; x=1750642393; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=65yvptSdo6oSSwoGRF8EUfcgAwuQwDq5kFTQAdR/3Jo=; b=SDDn75PHcJ8GbS4l8V8L4+LaW/XPxrnsJ0DUEJ3gLIBTa/6cNs3LKjsYDY7P5ftPc1 3pAoB6teFSQQ8KEXpQqpXsAVdsChXgGn4320wAxw9xbu1+oOja3KUIl5mzpri8WANBhH UeLQcEYmG36L05XX0B5yTyAkU3W9UOSYLoAQyostsueRWFB2Ngf6thXMDChIndk99pvR zKUjkOMyjxwDcsvMG0eCRmNz99vpcxxpsOGHQHvITX8BgW97yVVaLDOqtOKX0jrEkLTD JpkPUpzmBhuPCOrEjwfRlCj4g/5cR5oakOhu3tpB+0DHejJF9Quh84Avy4fLN51HvMNF WjhA== X-Forwarded-Encrypted: i=1; AJvYcCVvPr8VgulrWu/uIZ29UlGMpSZYrMeog2kYCHh7A5pJIo4bw4paPMnI++eaLemooEXwzoc4xQM8pJfESUMc2PXvGg==@vger.kernel.org, AJvYcCW+vybSgjOZ8t+0HulpJqLmYuZ7WTJEjCHk8lquc+78bhzFzqNzVWWEDQKMnxfTpPLklG4ZfVoThbDfsNKO@vger.kernel.org, AJvYcCWGxSQmv3TtSXxh9C03qCcO3lZ4PA61Wb8PcHvLVvv1dL5ZNcO/j4zR3z7f+TeZcQLb7p/YAWWEC5MP@vger.kernel.org X-Gm-Message-State: AOJu0Yw6j14IiNmMsb+u7eGPy4SS/L7nDDQSRHeGBJCC+3pt0a9Zobhw GVWeGRaSiUBFMIQ9+KRMF6sjbmCjeNoA9yVoeSZyv4MTB8O032vWA3OMJqFdAQ== X-Gm-Gg: ASbGnct37elTYkAJQBEX7pIv6NVaLBv6j7LpRJZ9BYKaSVLqeKujVGfGjlYtyBJTzJf MJQqIV+23hpqsVsh9UvxAAK/8xAwuvJEfPMRnWdvAFSRu66NNXM3Vc/Mvc296nehw77Hr2jYRjF jjOf1L1WUuh4DjkV5/BI5reInF69LlV3GkwAkDtBpfpT+eDaO6Cym2zTDKTD0zU/zDrFkod2C9E Canp9KWMKX1tDKGYMvZfIuk0DvIlqtJP9/Z5lxQq0VuXeOFJE2EpN+4OAVM9fMsx37KH14GI7nd KbTZV3jkfPv2Krk3Tc2Q/oM+VrZxqfPwxCk0RR709J4xhYoxb2Z5Dh2zsPO7LzSwdxz2UjBqozo Rbbw= X-Google-Smtp-Source: AGHT+IH8RHIqmgqFH9/PYcKJWUdxyaFMM6Kq/4bBmlVBjq5NMwMgObIJXACByRuQ2ziPGn9ASPeGPg== X-Received: by 2002:a17:903:2ac7:b0:235:278c:7d06 with SMTP id d9443c01a7336-2366ae00e80mr122624655ad.8.1750037593408; Sun, 15 Jun 2025 18:33:13 -0700 (PDT) Received: from [127.0.1.1] (wf121-134.ust.hk. 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Signed-off-by: Nick Chan --- arch/arm64/boot/dts/apple/t8010.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8010.dtsi b/arch/arm64/boot/dts/app= le/t8010.dtsi index 17e294bd7c44c7961cc3ba0ec5f4178840d5b9c6..cbffc84480379cb476d5caaecce= 91f746e862354 100644 --- a/arch/arm64/boot/dts/apple/t8010.dtsi +++ b/arch/arm64/boot/dts/apple/t8010.dtsi @@ -243,6 +243,14 @@ timer { interrupts =3D , ; }; + + pmu { + compatible =3D "apple,fusion-pmu"; + interrupt-parent =3D <&aic>; + interrupts =3D , + ; + interrupt-affinity =3D <&cpu0 &cpu1>; + }; }; =20 #include "t8010-pmgr.dtsi" --=20 2.49.0 From nobody Fri Oct 10 04:02:06 2025 Received: from mail-pl1-f170.google.com (mail-pl1-f170.google.com [209.85.214.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C2BFD28642A; Mon, 16 Jun 2025 01:33:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Signed-off-by: Nick Chan --- arch/arm64/boot/dts/apple/t8011.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8011.dtsi b/arch/arm64/boot/dts/app= le/t8011.dtsi index 5b280c896b760dc8b759bf38dae79060e34dfc19..7fb3ab738f67583d9a19a542bf3= 6ab2806268d55 100644 --- a/arch/arm64/boot/dts/apple/t8011.dtsi +++ b/arch/arm64/boot/dts/apple/t8011.dtsi @@ -237,6 +237,15 @@ timer { interrupts =3D , ; }; + + pmu { + compatible =3D "apple,fusion-pmu"; + interrupt-parent =3D <&aic>; + interrupts =3D , + , + ; + interrupt-affinity =3D <&cpu0 &cpu1 &cpu2>; + }; }; =20 #include "t8011-pmgr.dtsi" --=20 2.49.0 From nobody Fri Oct 10 04:02:06 2025 Received: from mail-pl1-f175.google.com (mail-pl1-f175.google.com [209.85.214.175]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 11FF01F0994; Mon, 16 Jun 2025 01:33:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Signed-off-by: Nick Chan --- arch/arm64/boot/dts/apple/t8012.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8012.dtsi b/arch/arm64/boot/dts/app= le/t8012.dtsi index 42df2f51ad7be4c4533e76d18e49a9a747b6b7a8..d79ed754c68dd89fc8c52887e6d= cbbce04fe126b 100644 --- a/arch/arm64/boot/dts/apple/t8012.dtsi +++ b/arch/arm64/boot/dts/apple/t8012.dtsi @@ -276,6 +276,14 @@ timer { interrupts =3D , ; }; + + pmu { + compatible =3D "apple,fusion-pmu"; + interrupt-parent =3D <&aic>; + interrupts =3D , + ; + interrupt-affinity =3D <&cpu0 &cpu1>; + }; }; =20 #include "t8012-pmgr.dtsi" --=20 2.49.0 From nobody Fri Oct 10 04:02:06 2025 Received: from mail-pl1-f179.google.com (mail-pl1-f179.google.com [209.85.214.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E537A286D4D; Mon, 16 Jun 2025 01:33:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.179 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750037606; cv=none; b=QRsyysMtEmqReYPiYfQ5YkV7B78bDxSb4CG0GKxfeRzbRyTqlch7zu0pxwsCgaAWMGgPBZxEPBPr+yU8ybMyeITABT5QZUAe0ptm3ofuE4eFB0M8dq5KXYSiUKu70SCPkxFGd81guguHQAZfdAXMDFkRg0u5x6tCrbDr9AmRH0g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750037606; c=relaxed/simple; bh=ZHoXysjC3tKjwBhupXya9t0tvevKJFeLclU2Q2P4acg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Uuxi57DgibEzsKJtjMXHXn/Dhz0BZrAwjWgPt7xj4xrlhsrhgaExgF5Q/cR0vU4QT8jqDBHbxsGbncl1cU/n7ljrHtBiiYBhe/bdcckcKZN8IWnCKTxHrI+J4OOjZlepBdGRjgzrGY+wAWqy0E++DZdtcr4pYdsSoS5LRzrnNBg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=Edz4Zy2y; arc=none smtp.client-ip=209.85.214.179 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Edz4Zy2y" Received: by mail-pl1-f179.google.com with SMTP id d9443c01a7336-2350fc2591dso35520875ad.1; Sun, 15 Jun 2025 18:33:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1750037603; x=1750642403; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=YgYxG+vTxBAlApfr9OfPBfVTpSGem7njEO/S/STMqlg=; b=Edz4Zy2yEYL21vk1ZbO6Jcs4wPg9w7iC0mv81RL3Cw7iwRjt/54kdt6YM2WD7yaOFy dQpH9xoAglBfJTfbHT8NgcbjuG/SWa6yN4y2O/Qgcso1gVsoCXwx5HYDgduQZ8abamAj Ori9EGSWZQf2ELLjm3l7jjcRcJxN0+7UcDiGPZUqnegE0IgHqL3borqnsTAR/SmdoftW LrVi6IghcGgsf2jl9KVZYHhpCsSjqFjLRhX03xZ6WD8e9HNw9ljxVjEUWABzcpOlO9x3 guIhZrHYvSRVqGbUvZmEJI/ao7GKFfJjDF/HErATEauUsmUk9ZrtccCvYvkMvAt9TwNC T3Zg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1750037603; x=1750642403; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YgYxG+vTxBAlApfr9OfPBfVTpSGem7njEO/S/STMqlg=; b=MQMZDtuZA/YZRJoWKhOE49nL2WX4XoI0KLOQaTDla9VjD8ddkkfan2Emdzs+hgK3If capTVlr9nluT0Z9YB+g24wCkyCj+Arh9OT0eCMo/iGwhhGJxJoCTZAa5rqrhHKW8jYU8 RAm7s0hCrfmlzbgt05grHAFbQVk6Vo77Ncwa8Xef2z0b6Xphbsq6fotufqQfaEPKr/i0 2z+3yp21xvxtdEKYXrJPp83CUqAUEz4wmW9fJnV3BuGIYSo0QNp93+ILvP+cNyi/zmIT /4uZ6tXTR+9m+0EG/ayq4jhVa21WiT/Z8cpWhW6aKqzj/r98VZQ479mSKf8y0j62GSAA BGqw== X-Forwarded-Encrypted: i=1; AJvYcCUW/28eOu+s/yi4T083H2WSe2llbX61HwpdJXIR31Lmx2MkDe6uqz2Yw9xrcK8+iEJp9N2+mTL29Bf9@vger.kernel.org, AJvYcCWP8CHmItJ7KThpugL4Lh7rQnAyeWTkP/vfXOX5jXWqlwTyAYmCtCbEIjqU9xOgb4ngOROBlz7TdtwNPvF6tvvfnA==@vger.kernel.org, AJvYcCXp7rWekdjtssc2AtMsCwKgZ4dSSG+JHRXYQhbPI34FGjrknn+2vcxX4Gex9cOymTGy3Ba2rHP1HwaVkWok@vger.kernel.org X-Gm-Message-State: AOJu0YxioWVvSpJxokcMhjk9dPURPcqAr5hTqgTyVeKWXukmkON2fqUm ZloO9M52uCAsQnkGzlTf/Pbns+B+c3RrZinRimbU+4Y/aKT6gq/njKAtCOQUbA== X-Gm-Gg: ASbGncvlrYd+wv0tdDtCcKaNWjpgGuSbx9mNnfsD6E00ivMKw4LdoeXTmKsOs7+N3sr HcElv+ylfDBcOxDLbMJT1KTPJBiKz5tWfJzUYsUOzgqAmg/RA3AJSp0eFLPFdF89y9CtSAbsrjN F9Y9eSYTBCJTl3juuU22Suc1HBvPj9hy7BpSwPiTr6PjyPz8Kr7NAz7owhRGtm0N6oi8RyZJsCH 14SwR+4tl3r/YYQTAPAJk6HX4NwT1NrLTi+e4hLCQAONYdFOw24vPzWfzoLSTru5VexcIT7pB/I UZfdBAnjyucIXyIwZliQ0RP2AlHt9duU6txuuua0HNnsGrdM0InNru2RLSlJCE1oH+6SUWNl1uU CpS4= X-Google-Smtp-Source: AGHT+IGUNE394ORxjIh9GhaDQ4I3KqTxb9FUPwuTUfcms2kv5CaO57PXeF2Ec3A96Ssb2JDXBhtDnA== X-Received: by 2002:a17:902:ec8b:b0:215:b1e3:c051 with SMTP id d9443c01a7336-2366ae0ddedmr101009925ad.11.1750037603347; Sun, 15 Jun 2025 18:33:23 -0700 (PDT) Received: from [127.0.1.1] (wf121-134.ust.hk. [175.159.121.134]) by smtp.googlemail.com with ESMTPSA id d9443c01a7336-2365deb2cedsm49932455ad.163.2025.06.15.18.33.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 15 Jun 2025 18:33:23 -0700 (PDT) From: Nick Chan Date: Mon, 16 Jun 2025 09:32:10 +0800 Subject: [PATCH RESEND v7 21/21] arm64: dts: apple: t8015: Add CPU PMU nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250616-apple-cpmu-v7-21-df2778a44d5c@gmail.com> References: <20250616-apple-cpmu-v7-0-df2778a44d5c@gmail.com> In-Reply-To: <20250616-apple-cpmu-v7-0-df2778a44d5c@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Sven Peter Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1462; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=ZHoXysjC3tKjwBhupXya9t0tvevKJFeLclU2Q2P4acg=; b=owEBbQKS/ZANAwAKAQHKCLemxQgkAcsmYgBoT3QaSXqCudX2xRA+ssME3ry+rfSTxP+sC1MrC ixnxG3HfLWJAjMEAAEKAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCaE90GgAKCRABygi3psUI JADEEAC3bkcdx2hB1A0jAuE+jQT0MTVLry1QJzypyt7uDz/cbauH5T0Flh6NufBZjPuPF/Sv2Mb rD4RMil6Ax3YXWBc1aL+j8zwQdq8wRFn1XvphQyCVzPcG7GEckhipulqj7Okfn9ORpTNI9VZNY/ geWfae2fnK0yc5UUtGz50C6/QAysifrAjrAefbV9XGSW6b7sYyXXlISwB6nqfCt8A/c5y9Kpk6Y BXEgeqiP1Sb4UYQXBBIxj2ycsYYbRr7pWWsmqVrk9CGOEmYKZ79qQG4uYjzZNI2/GPFkMTzaeSF GWbX51uX2Y8WGyzuqHJrUGRMHx0cvSK/YUUuNW1RppphZPWHTYGOEDFfw1gPod3NPjMueLg739Y 6rXnPWEEXwdfMluXd/qpa/ZS5pDnDnMNnjqZep2Ya3LNOyvnhBCBqIoL4mOF1NAQiAhtTrOvVtf Z1TgtrYc8zZoa+1NgT21fugtO25LVSxXRbtPBP3E6hGz2BhG1AtqgpFfAsm/ZapQhomR+vxAkcx mhk50zGnK45EUy5twAajaN1i9FyMw91eWP/zsdue2J9ILg4FYTZ90km9mi5Ln7268c0vR2fThMU L5ayeXeJbFaFMHgMkyBWIdNe5fJDPc8e12T+KwnErz7hevAZknTP+1m2G0FYXTVn5z4M0RmiaB0 BbO6+1HlUNipYpg== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 Add CPU PMU nodes for Apple A11 SoC. Signed-off-by: Nick Chan --- arch/arm64/boot/dts/apple/t8015.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8015.dtsi b/arch/arm64/boot/dts/app= le/t8015.dtsi index 4d54afcecd50b50ed1fd386ccfc46c373e190e6b..e838b65ea63eef9c198032ee87e= 63dae282141dc 100644 --- a/arch/arm64/boot/dts/apple/t8015.dtsi +++ b/arch/arm64/boot/dts/apple/t8015.dtsi @@ -252,6 +252,18 @@ aic: interrupt-controller@232100000 { #interrupt-cells =3D <3>; interrupt-controller; power-domains =3D <&ps_aic>; + + affinities { + e-core-pmu-affinity { + apple,fiq-index =3D ; + cpus =3D <&cpu_e0 &cpu_e1 &cpu_e2 &cpu_e3>; + }; + + p-core-pmu-affinity { + apple,fiq-index =3D ; + cpus =3D <&cpu_p0 &cpu_p1>; + }; + }; }; =20 pmgr: power-management@232000000 { @@ -380,6 +392,18 @@ timer { interrupts =3D , ; }; + + pmu-e { + compatible =3D "apple,mistral-pmu"; + interrupt-parent =3D <&aic>; + interrupts =3D ; + }; + + pmu-p { + compatible =3D "apple,monsoon-pmu"; + interrupt-parent =3D <&aic>; + interrupts =3D ; + }; }; =20 #include "t8015-pmgr.dtsi" --=20 2.49.0