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[84.72.156.211]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-adf8b393ea8sm412692766b.159.2025.06.15.15.23.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 15 Jun 2025 15:23:08 -0700 (PDT) From: Lothar Rubusch To: jic23@kernel.org, dlechner@baylibre.com, nuno.sa@analog.com, andy@kernel.org, corbet@lwn.net, lucas.p.stankus@gmail.com, lars@metafoo.de, Michael.Hennerich@analog.com, bagasdotme@gmail.com Cc: l.rubusch@gmail.com, linux-iio@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 3/8] iio: accel: adxl313: add buffered FIFO watermark with interrupt handling Date: Sun, 15 Jun 2025 22:22:53 +0000 Message-Id: <20250615222258.117771-4-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250615222258.117771-1-l.rubusch@gmail.com> References: <20250615222258.117771-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Cover the following tasks: =E2=80=93 Add scan_mask and scan_index to the IIO channel configuration. The scan_index sets up buffer usage. According to the datasheet, the ADXL313 uses a 13-bit wide data field in full-resolution mode. Set the signedness, number of storage bits, and endianness accordingly. =E2=80=93 Parse the devicetree for an optional interrupt line and configure= the interrupt mapping based on its presence. If no interrupt line is specified, keep the FIFO in bypass mode as currently implemented. =E2=80=93 Set up the interrupt handler. Add register access to detect and evaluate interrupts. Implement functions to clear status registers and reset the FIFO. =E2=80=93 Implement FIFO watermark configuration and handling. Allow the watermark level to be set, evaluate the corresponding interrupt, read the FIFO contents, and push the data to the IIO channel. Signed-off-by: Lothar Rubusch --- drivers/iio/accel/adxl313.h | 22 +++ drivers/iio/accel/adxl313_core.c | 259 ++++++++++++++++++++++++++++++- 2 files changed, 275 insertions(+), 6 deletions(-) diff --git a/drivers/iio/accel/adxl313.h b/drivers/iio/accel/adxl313.h index 6958a00f5e8f..4f4a9fd39f6d 100644 --- a/drivers/iio/accel/adxl313.h +++ b/drivers/iio/accel/adxl313.h @@ -21,6 +21,7 @@ #define ADXL313_REG_ACT_INACT_CTL 0x27 #define ADXL313_REG_BW_RATE 0x2C #define ADXL313_REG_POWER_CTL 0x2D +#define ADXL313_REG_INT_ENABLE 0x2E #define ADXL313_REG_INT_MAP 0x2F #define ADXL313_REG_INT_SOURCE 0x30 #define ADXL313_REG_DATA_FORMAT 0x31 @@ -46,6 +47,25 @@ #define ADXL313_SPI_3WIRE BIT(6) #define ADXL313_I2C_DISABLE BIT(6) =20 +#define ADXL313_INT_OVERRUN BIT(0) +#define ADXL313_INT_WATERMARK BIT(1) +#define ADXL313_INT_INACTIVITY BIT(3) +#define ADXL313_INT_ACTIVITY BIT(4) +#define ADXL313_INT_DREADY BIT(7) + +/* FIFO entries: how many values are stored in the FIFO */ +#define ADXL313_REG_FIFO_STATUS_ENTRIES_MSK GENMASK(5, 0) +/* FIFO samples: number of samples needed for watermark (FIFO mode) */ +#define ADXL313_REG_FIFO_CTL_SAMPLES_MSK GENMASK(4, 0) +#define ADXL313_REG_FIFO_CTL_MODE_MSK GENMASK(7, 6) + +#define ADXL313_FIFO_BYPASS 0 +#define ADXL313_FIFO_STREAM 2 + +#define ADXL313_FIFO_SIZE 32 + +#define ADXL313_NUM_AXIS 3 + extern const struct regmap_access_table adxl312_readable_regs_table; extern const struct regmap_access_table adxl313_readable_regs_table; extern const struct regmap_access_table adxl314_readable_regs_table; @@ -66,7 +86,9 @@ struct adxl313_data { struct regmap *regmap; const struct adxl313_chip_info *chip_info; struct mutex lock; /* lock to protect transf_buf */ + u8 watermark; __le16 transf_buf __aligned(IIO_DMA_MINALIGN); + __le16 fifo_buf[ADXL313_NUM_AXIS * ADXL313_FIFO_SIZE + 1]; }; =20 struct adxl313_chip_info { diff --git a/drivers/iio/accel/adxl313_core.c b/drivers/iio/accel/adxl313_c= ore.c index 99a7f3755031..488680807a8f 100644 --- a/drivers/iio/accel/adxl313_core.c +++ b/drivers/iio/accel/adxl313_core.c @@ -8,11 +8,23 @@ */ =20 #include +#include #include +#include +#include #include =20 +#include +#include + #include "adxl313.h" =20 +#define ADXL313_INT_NONE U8_MAX +#define ADXL313_INT1 1 +#define ADXL313_INT2 2 + +#define ADXL313_REG_XYZ_BASE ADXL313_REG_DATA_AXIS(0) + static const struct regmap_range adxl312_readable_reg_range[] =3D { regmap_reg_range(ADXL313_REG_DEVID0, ADXL313_REG_DEVID0), regmap_reg_range(ADXL313_REG_OFS_AXIS(0), ADXL313_REG_OFS_AXIS(2)), @@ -195,9 +207,10 @@ static const int adxl313_odr_freqs[][2] =3D { [9] =3D { 3200, 0 }, }; =20 -#define ADXL313_ACCEL_CHANNEL(index, axis) { \ +#define ADXL313_ACCEL_CHANNEL(index, reg, axis) { \ .type =3D IIO_ACCEL, \ - .address =3D index, \ + .scan_index =3D (index), \ + .address =3D (reg), \ .modified =3D 1, \ .channel2 =3D IIO_MOD_##axis, \ .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW) | \ @@ -207,14 +220,26 @@ static const int adxl313_odr_freqs[][2] =3D { .info_mask_shared_by_type_available =3D \ BIT(IIO_CHAN_INFO_SAMP_FREQ), \ .scan_type =3D { \ + .sign =3D 's', \ .realbits =3D 13, \ + .storagebits =3D 16, \ + .endianness =3D IIO_BE, \ }, \ } =20 +enum adxl313_chans { + chan_x, chan_y, chan_z, +}; + static const struct iio_chan_spec adxl313_channels[] =3D { - ADXL313_ACCEL_CHANNEL(0, X), - ADXL313_ACCEL_CHANNEL(1, Y), - ADXL313_ACCEL_CHANNEL(2, Z), + ADXL313_ACCEL_CHANNEL(0, chan_x, X), + ADXL313_ACCEL_CHANNEL(1, chan_y, Y), + ADXL313_ACCEL_CHANNEL(2, chan_z, Z), +}; + +static const unsigned long adxl313_scan_masks[] =3D { + BIT(chan_x) | BIT(chan_y) | BIT(chan_z), + 0 }; =20 static int adxl313_set_odr(struct adxl313_data *data, @@ -345,6 +370,173 @@ static int adxl313_write_raw(struct iio_dev *indio_de= v, } } =20 +static int adxl313_set_watermark(struct iio_dev *indio_dev, unsigned int v= alue) +{ + struct adxl313_data *data =3D iio_priv(indio_dev); + int ret; + + value =3D min(value, ADXL313_FIFO_SIZE - 1); + + ret =3D adxl313_set_measure_en(data, false); + if (ret) + return ret; + + ret =3D regmap_update_bits(data->regmap, ADXL313_REG_FIFO_CTL, + ADXL313_REG_FIFO_CTL_MODE_MSK, value); + if (ret) + return ret; + + data->watermark =3D value; + + ret =3D regmap_set_bits(data->regmap, ADXL313_REG_INT_ENABLE, + ADXL313_INT_WATERMARK); + if (ret) + return ret; + + return adxl313_set_measure_en(data, true); +} + +static int adxl313_get_samples(struct adxl313_data *data) +{ + unsigned int regval; + int ret; + + ret =3D regmap_read(data->regmap, ADXL313_REG_FIFO_STATUS, ®val); + if (ret) + return ret; + + return FIELD_GET(ADXL313_REG_FIFO_STATUS_ENTRIES_MSK, regval); +} + +static int adxl313_fifo_transfer(struct adxl313_data *data, int samples) +{ + unsigned int i; + int ret; + + for (i =3D 0; i < samples; i++) { + ret =3D regmap_bulk_read(data->regmap, ADXL313_REG_XYZ_BASE, + data->fifo_buf + (i * ADXL313_NUM_AXIS), + 2 * ADXL313_NUM_AXIS); + if (ret) + return ret; + } + + return 0; +} + +/** + * adxl313_fifo_reset() - Reset the FIFO and interrupt status registers. + * @data: The device data. + * + * Reset the FIFO status registers. Reading out status registers clears the + * FIFO and interrupt configuration. Thus do not evaluate regmap return va= lues. + * Ignore particular read register content. Register content is not proces= sed + * any further. Therefore the function returns void. + */ +static void adxl313_fifo_reset(struct adxl313_data *data) +{ + unsigned int regval; + int samples; + + adxl313_set_measure_en(data, false); + + samples =3D adxl313_get_samples(data); + if (samples > 0) + adxl313_fifo_transfer(data, samples); + + regmap_read(data->regmap, ADXL313_REG_INT_SOURCE, ®val); + + adxl313_set_measure_en(data, true); +} + +static int adxl313_buffer_postenable(struct iio_dev *indio_dev) +{ + struct adxl313_data *data =3D iio_priv(indio_dev); + int ret; + + /* Set FIFO modes with measurement turned off, according to datasheet */ + ret =3D adxl313_set_measure_en(data, false); + if (ret) + return ret; + + ret =3D regmap_write(data->regmap, ADXL313_REG_FIFO_CTL, + FIELD_PREP(ADXL313_REG_FIFO_CTL_SAMPLES_MSK, data->watermark) | + FIELD_PREP(ADXL313_REG_FIFO_CTL_MODE_MSK, ADXL313_FIFO_STREAM)); + if (ret) + return ret; + + return adxl313_set_measure_en(data, true); +} + +static int adxl313_buffer_predisable(struct iio_dev *indio_dev) +{ + struct adxl313_data *data =3D iio_priv(indio_dev); + int ret; + + ret =3D adxl313_set_measure_en(data, false); + if (ret) + return ret; + + ret =3D regmap_write(data->regmap, ADXL313_REG_FIFO_CTL, + FIELD_PREP(ADXL313_REG_FIFO_CTL_MODE_MSK, ADXL313_FIFO_BYPASS)); + + ret =3D regmap_write(data->regmap, ADXL313_REG_INT_ENABLE, 0); + if (ret) + return ret; + + return adxl313_set_measure_en(data, true); +} + +static const struct iio_buffer_setup_ops adxl313_buffer_ops =3D { + .postenable =3D adxl313_buffer_postenable, + .predisable =3D adxl313_buffer_predisable, +}; + +static int adxl313_fifo_push(struct iio_dev *indio_dev, int samples) +{ + struct adxl313_data *data =3D iio_priv(indio_dev); + unsigned int i; + int ret; + + ret =3D adxl313_fifo_transfer(data, samples); + if (ret) + return ret; + + for (i =3D 0; i < ADXL313_NUM_AXIS * samples; i +=3D ADXL313_NUM_AXIS) + iio_push_to_buffers(indio_dev, &data->fifo_buf[i]); + + return 0; +} + +static irqreturn_t adxl313_irq_handler(int irq, void *p) +{ + struct iio_dev *indio_dev =3D p; + struct adxl313_data *data =3D iio_priv(indio_dev); + int samples, int_stat; + + if (regmap_read(data->regmap, ADXL313_REG_INT_SOURCE, &int_stat)) + return IRQ_NONE; + + if (FIELD_GET(ADXL313_INT_WATERMARK, int_stat)) { + samples =3D adxl313_get_samples(data); + if (samples < 0) + goto err; + + if (adxl313_fifo_push(indio_dev, samples)) + goto err; + } + + if (FIELD_GET(ADXL313_INT_OVERRUN, int_stat)) + goto err; + + return IRQ_HANDLED; + +err: + adxl313_fifo_reset(data); + + return IRQ_HANDLED; +} + static int adxl313_reg_access(struct iio_dev *indio_dev, unsigned int reg, unsigned int writeval, unsigned int *readval) { @@ -359,6 +551,7 @@ static const struct iio_info adxl313_info =3D { .read_raw =3D adxl313_read_raw, .write_raw =3D adxl313_write_raw, .read_avail =3D adxl313_read_freq_avail, + .hwfifo_set_watermark =3D adxl313_set_watermark, .debugfs_reg_access =3D &adxl313_reg_access, }; =20 @@ -424,7 +617,9 @@ int adxl313_core_probe(struct device *dev, { struct adxl313_data *data; struct iio_dev *indio_dev; - int ret; + u8 int_line; + u8 int_map_msk; + int irq, ret; =20 indio_dev =3D devm_iio_device_alloc(dev, sizeof(*data)); if (!indio_dev) @@ -441,6 +636,7 @@ int adxl313_core_probe(struct device *dev, indio_dev->modes =3D INDIO_DIRECT_MODE; indio_dev->channels =3D adxl313_channels; indio_dev->num_channels =3D ARRAY_SIZE(adxl313_channels); + indio_dev->available_scan_masks =3D adxl313_scan_masks; =20 ret =3D adxl313_setup(dev, data, setup); if (ret) { @@ -448,6 +644,57 @@ int adxl313_core_probe(struct device *dev, return ret; } =20 + int_line =3D ADXL313_INT1; + irq =3D fwnode_irq_get_byname(dev_fwnode(dev), "INT1"); + if (irq < 0) { + int_line =3D ADXL313_INT2; + irq =3D fwnode_irq_get_byname(dev_fwnode(dev), "INT2"); + if (irq < 0) + int_line =3D ADXL313_INT_NONE; + } + + if (int_line !=3D ADXL313_INT_NONE) { + /* FIFO_STREAM mode */ + int_map_msk =3D ADXL313_INT_DREADY | ADXL313_INT_ACTIVITY | + ADXL313_INT_INACTIVITY | ADXL313_INT_WATERMARK | + ADXL313_INT_OVERRUN; + ret =3D regmap_assign_bits(data->regmap, ADXL313_REG_INT_MAP, + int_map_msk, int_line =3D=3D ADXL313_INT2); + if (ret) + return ret; + + ret =3D devm_iio_kfifo_buffer_setup(dev, indio_dev, + &adxl313_buffer_ops); + if (ret) + return ret; + + ret =3D devm_request_threaded_irq(dev, irq, NULL, + &adxl313_irq_handler, + IRQF_SHARED | IRQF_ONESHOT, + indio_dev->name, indio_dev); + if (ret) + return ret; + } else { + /* + * FIFO_BYPASSED mode + * + * When no interrupt lines are specified, the driver falls back + * to use the sensor in FIFO_BYPASS mode. This means turning off + * internal FIFO and interrupt generation (since there is no + * line specified). Unmaskable interrupts such as overrun or + * data ready won't interfere. Even that a FIFO_STREAM mode w/o + * connected interrupt line might allow for obtaining raw + * measurements, a fallback to disable interrupts when no + * interrupt lines are connected seems to be the cleaner + * solution. + */ + ret =3D regmap_write(data->regmap, ADXL313_REG_FIFO_CTL, + FIELD_PREP(ADXL313_REG_FIFO_CTL_MODE_MSK, + ADXL313_FIFO_BYPASS)); + if (ret) + return ret; + } + return devm_iio_device_register(dev, indio_dev); } EXPORT_SYMBOL_NS_GPL(adxl313_core_probe, IIO_ADXL313); --=20 2.39.5