From nobody Fri Oct 10 09:21:29 2025 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4397B2609D9; Sun, 15 Jun 2025 03:58:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749959902; cv=none; b=qR0ikfKqDVWwUP//mX9GB37tPbya5TYZY5DTaKH706rFBfOn1/RxtzvdUU1obloMgrzUaMC8zAmNwOzArBQNG+0Ij0/Yvc2ATVyd88P1WvC+Dn3Yu7He+i/NIkw+lKq/BvJB52X+/RWNpMVx0CK7uLkcmrm/qKchfo0GjX44m2E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749959902; c=relaxed/simple; bh=hhg3MOUlGRm1vzPyc/vs5RdgGUj6mrA4VG+758wdgLc=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=dWaZ7XCxjlSMRLu51aBFerqI6VqDWgdsuZCmqh/pHXws5+m5gaYnOVqHlBmNHbLXAF413a41UmMpNrCGPWh037cD4PeNDoS8udv07ETCKjJBsHOoDme6AdcvDa0LGjr6Ll4FVXAAyHCSJJOmOVTtIBV+6SMbSq8zSomAIMNzkHQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Sun, 15 Jun 2025 11:58:03 +0800 Received: from mail.aspeedtech.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Sun, 15 Jun 2025 11:58:03 +0800 From: Cool Lee To: , , , , , , , , , Subject: [PATCH 1/8] mmc: sdhci-of-aspeed: Fix sdhci software reset can't be cleared issue. Date: Sun, 15 Jun 2025 11:57:56 +0800 Message-ID: <20250615035803.3752235-2-cool_lee@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250615035803.3752235-1-cool_lee@aspeedtech.com> References: <20250615035803.3752235-1-cool_lee@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Replace sdhci software reset by scu reset from top. Signed-off-by: Cool Lee --- drivers/mmc/host/sdhci-of-aspeed.c | 55 +++++++++++++++++++++++++++++- 1 file changed, 54 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-of-aspeed.c b/drivers/mmc/host/sdhci-of= -aspeed.c index d6de010551b9..01bc574272eb 100644 --- a/drivers/mmc/host/sdhci-of-aspeed.c +++ b/drivers/mmc/host/sdhci-of-aspeed.c @@ -13,6 +13,7 @@ #include #include #include +#include #include =20 #include "sdhci-pltfm.h" @@ -39,6 +40,7 @@ struct aspeed_sdc { struct clk *clk; struct resource *res; + struct reset_control *rst; =20 spinlock_t lock; void __iomem *regs; @@ -328,13 +330,58 @@ static u32 aspeed_sdhci_readl(struct sdhci_host *host= , int reg) return val; } =20 +static void aspeed_sdhci_reset(struct sdhci_host *host, u8 mask) +{ + struct sdhci_pltfm_host *pltfm_priv; + struct aspeed_sdhci *aspeed_sdhci; + struct aspeed_sdc *aspeed_sdc; + u32 save_array[7]; + u32 reg_array[] =3D {SDHCI_DMA_ADDRESS, + SDHCI_BLOCK_SIZE, + SDHCI_ARGUMENT, + SDHCI_HOST_CONTROL, + SDHCI_CLOCK_CONTROL, + SDHCI_INT_ENABLE, + SDHCI_SIGNAL_ENABLE}; + int i; + u16 tran_mode; + u32 mmc8_mode; + + pltfm_priv =3D sdhci_priv(host); + aspeed_sdhci =3D sdhci_pltfm_priv(pltfm_priv); + aspeed_sdc =3D aspeed_sdhci->parent; + + if (!IS_ERR(aspeed_sdc->rst)) { + for (i =3D 0; i < ARRAY_SIZE(reg_array); i++) + save_array[i] =3D sdhci_readl(host, reg_array[i]); + + tran_mode =3D sdhci_readw(host, SDHCI_TRANSFER_MODE); + mmc8_mode =3D readl(aspeed_sdc->regs); + + reset_control_assert(aspeed_sdc->rst); + mdelay(1); + reset_control_deassert(aspeed_sdc->rst); + mdelay(1); + + for (i =3D 0; i < ARRAY_SIZE(reg_array); i++) + sdhci_writel(host, save_array[i], reg_array[i]); + + sdhci_writew(host, tran_mode, SDHCI_TRANSFER_MODE); + writel(mmc8_mode, aspeed_sdc->regs); + + aspeed_sdhci_set_clock(host, host->clock); + } + + sdhci_reset(host, mask); +} + static const struct sdhci_ops aspeed_sdhci_ops =3D { .read_l =3D aspeed_sdhci_readl, .set_clock =3D aspeed_sdhci_set_clock, .get_max_clock =3D aspeed_sdhci_get_max_clock, .set_bus_width =3D aspeed_sdhci_set_bus_width, .get_timeout_clock =3D sdhci_pltfm_clk_get_max_clock, - .reset =3D sdhci_reset, + .reset =3D aspeed_sdhci_reset, .set_uhs_signaling =3D sdhci_set_uhs_signaling, }; =20 @@ -535,6 +582,12 @@ static int aspeed_sdc_probe(struct platform_device *pd= ev) =20 spin_lock_init(&sdc->lock); =20 + sdc->rst =3D devm_reset_control_get(&pdev->dev, NULL); + if (!IS_ERR(sdc->rst)) { + reset_control_assert(sdc->rst); + reset_control_deassert(sdc->rst); + } + sdc->clk =3D devm_clk_get(&pdev->dev, NULL); if (IS_ERR(sdc->clk)) return PTR_ERR(sdc->clk); --=20 2.34.1 From nobody Fri Oct 10 09:21:29 2025 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F264D261594; Sun, 15 Jun 2025 03:58:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749959905; cv=none; b=HqEERH9OATCq7thQyUpf8gdgkmP+vJTec3kK+PFpV+44CWneLC8d/CUKBIwP4p0I6g1IZ4Z3MX8XHDIxmz5JUW4EO7rfiHBLCKjS+ylmtzD4rpxuFJdCrqbpG4zCc2arsCWGJHlgcjZmMXmC6ysOD3IfyQeKyqwXxNEtilTP3gY= ARC-Message-Signature: i=1; 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Sun, 15 Jun 2025 11:58:03 +0800 From: Cool Lee To: , , , , , , , , , Subject: [PATCH 2/8] mmc: sdhci-of-aspeed: Add runtime tuning Date: Sun, 15 Jun 2025 11:57:57 +0800 Message-ID: <20250615035803.3752235-3-cool_lee@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250615035803.3752235-1-cool_lee@aspeedtech.com> References: <20250615035803.3752235-1-cool_lee@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for runtime tuning in the Aspeed SDHCI driver. Using the timing phase register to adjust the clock phase with mmc tuning command to find the left and right boundary. Signed-off-by: Cool Lee --- drivers/mmc/host/sdhci-of-aspeed.c | 68 ++++++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/drivers/mmc/host/sdhci-of-aspeed.c b/drivers/mmc/host/sdhci-of= -aspeed.c index 01bc574272eb..5e5ae1894456 100644 --- a/drivers/mmc/host/sdhci-of-aspeed.c +++ b/drivers/mmc/host/sdhci-of-aspeed.c @@ -24,6 +24,7 @@ #define ASPEED_SDC_PHASE 0xf4 #define ASPEED_SDC_S1_PHASE_IN GENMASK(25, 21) #define ASPEED_SDC_S0_PHASE_IN GENMASK(20, 16) +#define ASPEED_SDC_S0_PHASE_IN_SHIFT 16 #define ASPEED_SDC_S1_PHASE_OUT GENMASK(15, 11) #define ASPEED_SDC_S1_PHASE_IN_EN BIT(10) #define ASPEED_SDC_S1_PHASE_OUT_EN GENMASK(9, 8) @@ -375,6 +376,72 @@ static void aspeed_sdhci_reset(struct sdhci_host *host= , u8 mask) sdhci_reset(host, mask); } =20 +static int aspeed_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) +{ + struct sdhci_pltfm_host *pltfm_priv; + struct aspeed_sdhci *sdhci; + struct aspeed_sdc *sdc; + struct device *dev; + + u32 val, left, right, edge; + u32 window, oldwindow =3D 0, center; + u32 in_phase, out_phase, enable_mask, inverted =3D 0; + + dev =3D mmc_dev(host->mmc); + pltfm_priv =3D sdhci_priv(host); + sdhci =3D sdhci_pltfm_priv(pltfm_priv); + sdc =3D sdhci->parent; + + out_phase =3D readl(sdc->regs + ASPEED_SDC_PHASE) & ASPEED_SDC_S0_PHASE_O= UT; + + enable_mask =3D ASPEED_SDC_S0_PHASE_OUT_EN | ASPEED_SDC_S0_PHASE_IN_EN; + + /* + * There are two window upon clock rising and falling edge. + * Iterate each tap delay to find the valid window and choose the + * bigger one, set the tap delay at the middle of window. + */ + for (edge =3D 0; edge < 2; edge++) { + if (edge =3D=3D 1) + inverted =3D ASPEED_SDHCI_TAP_PARAM_INVERT_CLK; + + val =3D (out_phase | enable_mask | (inverted << ASPEED_SDC_S0_PHASE_IN_S= HIFT)); + + /* find the left boundary */ + for (left =3D 0; left < ASPEED_SDHCI_NR_TAPS + 1; left++) { + in_phase =3D val | (left << ASPEED_SDC_S0_PHASE_IN_SHIFT); + writel(in_phase, sdc->regs + ASPEED_SDC_PHASE); + + if (!mmc_send_tuning(host->mmc, opcode, NULL)) + break; + } + + /* find the right boundary */ + for (right =3D left + 1; right < ASPEED_SDHCI_NR_TAPS + 1; right++) { + in_phase =3D val | (right << ASPEED_SDC_S0_PHASE_IN_SHIFT); + writel(in_phase, sdc->regs + ASPEED_SDC_PHASE); + + if (mmc_send_tuning(host->mmc, opcode, NULL)) + break; + } + + window =3D right - left; + dev_info(dev, "tuning window =3D %d\n", window); + + if (window > oldwindow) { + oldwindow =3D window; + center =3D (((right - 1) + left) / 2) | inverted; + } + } + + val =3D (out_phase | enable_mask | (center << ASPEED_SDC_S0_PHASE_IN_SHIF= T)); + writel(val, sdc->regs + ASPEED_SDC_PHASE); + + dev_info(dev, "tuning result=3D%x\n", val); + + return mmc_send_tuning(host->mmc, opcode, NULL); +} + static const struct sdhci_ops aspeed_sdhci_ops =3D { .read_l =3D aspeed_sdhci_readl, .set_clock =3D aspeed_sdhci_set_clock, @@ -383,6 +450,7 @@ static const struct sdhci_ops aspeed_sdhci_ops =3D { .get_timeout_clock =3D sdhci_pltfm_clk_get_max_clock, .reset =3D aspeed_sdhci_reset, .set_uhs_signaling =3D sdhci_set_uhs_signaling, + .platform_execute_tuning =3D aspeed_sdhci_execute_tuning, }; =20 static const struct sdhci_pltfm_data aspeed_sdhci_pdata =3D { --=20 2.34.1 From nobody Fri Oct 10 09:21:29 2025 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 76ED926280C; Sun, 15 Jun 2025 03:58:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749959907; cv=none; b=gG2DCbtMz4WtoiPHHbpT6YIE8PC0II71fSTtbsY64r6bYMIMtoRYVQSM2OUJh4k9KNyHOkWB1r/zerHWHklRmqnoA1bC6QCPDf9Wzj804vePxeQxjZhtzW7GlkafhXwdJXzBS8GhJmjeaz993LaeSfBMsmf/gQ9t2/RMweH4YbI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749959907; c=relaxed/simple; bh=YjPzTdmH7xkSjl38iTCRT6bZwtjPhBKYF1MCvlsqp+M=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=PThY4Eg2+xBMuoXsE+CCPuLcK7b2pB20y75JOtFLNx85v2u38g9IkHzkzewTGcqt+2KkqMMtMpGzAUz/hS5DdVp5eQsOmo8mtC0qqFjD7fhLrE0jmXoGte802KumO8FnGbeDYOgZA0gxrpcbGbqXgFRNeHGs/GxR/Y8r1Ar+kIU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Sun, 15 Jun 2025 11:58:03 +0800 Received: from mail.aspeedtech.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Sun, 15 Jun 2025 11:58:03 +0800 From: Cool Lee To: , , , , , , , , , Subject: [PATCH 3/8] mmc: sdhci-of-aspeed: Patch HOST_CONTROL2 register missing after top reset Date: Sun, 15 Jun 2025 11:57:58 +0800 Message-ID: <20250615035803.3752235-4-cool_lee@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250615035803.3752235-1-cool_lee@aspeedtech.com> References: <20250615035803.3752235-1-cool_lee@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" HOST_CONTROL2 register will be cleared after top reset, it needs to be saved/resotred while reset. Signed-off-by: Cool Lee --- drivers/mmc/host/sdhci-of-aspeed.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/host/sdhci-of-aspeed.c b/drivers/mmc/host/sdhci-of= -aspeed.c index 5e5ae1894456..10160a706334 100644 --- a/drivers/mmc/host/sdhci-of-aspeed.c +++ b/drivers/mmc/host/sdhci-of-aspeed.c @@ -336,14 +336,15 @@ static void aspeed_sdhci_reset(struct sdhci_host *hos= t, u8 mask) struct sdhci_pltfm_host *pltfm_priv; struct aspeed_sdhci *aspeed_sdhci; struct aspeed_sdc *aspeed_sdc; - u32 save_array[7]; + u32 save_array[8]; u32 reg_array[] =3D {SDHCI_DMA_ADDRESS, SDHCI_BLOCK_SIZE, SDHCI_ARGUMENT, SDHCI_HOST_CONTROL, SDHCI_CLOCK_CONTROL, SDHCI_INT_ENABLE, - SDHCI_SIGNAL_ENABLE}; + SDHCI_SIGNAL_ENABLE, + SDHCI_AUTO_CMD_STATUS}; int i; u16 tran_mode; u32 mmc8_mode; --=20 2.34.1 From nobody Fri Oct 10 09:21:29 2025 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CEDA0262FE9; Sun, 15 Jun 2025 03:58:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749959909; cv=none; b=HJY4M11qVYWyAoVS56NgEDYEsjg3kz5fq5RwxnHqx0+BMk0NJfG/wbaQ8AHMWwUf4YLJdjP+XbQk0GXn4G1bKNCW1OIk1SFUSZ5U/mzhkrkxgkevyTCgKzSemooVHEUm/yAI3cV4d0aply51caQlK6ksuoO02pKuibp92J3nAhI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749959909; c=relaxed/simple; bh=kj0fa6FUnZIfFY0VTTCuMa2DO67jndNJVpVLb3+Bfbk=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=kfJo63cDZAeVK8vKT8UeMAwebm6IkUX5qIfdWgT/d2xkxbflyhl+DLRyCE9C/iicgVY1rDP5aOmwfmffqCHG+I1BQa0DfAI13IF7dlFT+E85eAfE5+kZHuNnx5CKNXRaIaHgqcaOSP6evTNEgcrTZ6S9vy1rykL4+s44vhEsR6c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Sun, 15 Jun 2025 11:58:04 +0800 Received: from mail.aspeedtech.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Sun, 15 Jun 2025 11:58:04 +0800 From: Cool Lee To: , , , , , , , , , Subject: [PATCH 4/8] mmc: sdhci-of-aspeed: Get max clockk by using default api Date: Sun, 15 Jun 2025 11:57:59 +0800 Message-ID: <20250615035803.3752235-5-cool_lee@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250615035803.3752235-1-cool_lee@aspeedtech.com> References: <20250615035803.3752235-1-cool_lee@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Don't limit clock frequency by f_max. Signed-off-by: Cool Lee --- drivers/mmc/host/sdhci-of-aspeed.c | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-) diff --git a/drivers/mmc/host/sdhci-of-aspeed.c b/drivers/mmc/host/sdhci-of= -aspeed.c index 10160a706334..2bdd93a3f91f 100644 --- a/drivers/mmc/host/sdhci-of-aspeed.c +++ b/drivers/mmc/host/sdhci-of-aspeed.c @@ -288,14 +288,6 @@ static void aspeed_sdhci_set_clock(struct sdhci_host *= host, unsigned int clock) sdhci_enable_clk(host, clk); } =20 -static unsigned int aspeed_sdhci_get_max_clock(struct sdhci_host *host) -{ - if (host->mmc->f_max) - return host->mmc->f_max; - - return sdhci_pltfm_clk_get_max_clock(host); -} - static void aspeed_sdhci_set_bus_width(struct sdhci_host *host, int width) { struct sdhci_pltfm_host *pltfm_priv; @@ -446,7 +438,7 @@ static int aspeed_sdhci_execute_tuning(struct sdhci_hos= t *host, u32 opcode) static const struct sdhci_ops aspeed_sdhci_ops =3D { .read_l =3D aspeed_sdhci_readl, .set_clock =3D aspeed_sdhci_set_clock, - .get_max_clock =3D aspeed_sdhci_get_max_clock, + .get_max_clock =3D sdhci_pltfm_clk_get_max_clock, .set_bus_width =3D aspeed_sdhci_set_bus_width, .get_timeout_clock =3D sdhci_pltfm_clk_get_max_clock, .reset =3D aspeed_sdhci_reset, --=20 2.34.1 From nobody Fri Oct 10 09:21:29 2025 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E442E263C9B; Sun, 15 Jun 2025 03:58:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749959911; cv=none; b=mJZFWwzYJp8XE9NEUXENTAK+cb5QntFxSnVefJnEMWrlww5culfytg2LD+zh/oCmI2+EQUWoofQ4qfBXyAsxxJqESqU4Kp9upjlxYzuFRVwKN4tjY4GdBhOb3wRa5Z5x7Ujfh6Fx0PesUkN8/WCP+ekZInXiS3R14h2Y9POom/o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749959911; c=relaxed/simple; bh=HarTzHrwSyFQg+FX83UEhgHlcVli7cTOblv9vvMb3ZM=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=PLbRPNcEb3vI78okDfWiTUGTwim4zoW5WLwpPZ+QojVF0lxo/+GH2YdwMeiIQLvXh84QpJUy/u8uH9RyFh4P+nvG3NyZ5TYAGKDNAPsZ+a0xBb8WelhBAhhDmiazgS7aZS+ggSDfjCPxHYguDeNczyaQlVaYCJVmEp/vwtygL/8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Sun, 15 Jun 2025 11:58:04 +0800 Received: from mail.aspeedtech.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Sun, 15 Jun 2025 11:58:04 +0800 From: Cool Lee To: , , , , , , , , , Subject: [PATCH 5/8] mmc: sdhci-of-aspeed: Fix null pointer Date: Sun, 15 Jun 2025 11:58:00 +0800 Message-ID: <20250615035803.3752235-6-cool_lee@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250615035803.3752235-1-cool_lee@aspeedtech.com> References: <20250615035803.3752235-1-cool_lee@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Platform data might be null. Signed-off-by: Cool Lee --- drivers/mmc/host/sdhci-of-aspeed.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/host/sdhci-of-aspeed.c b/drivers/mmc/host/sdhci-of= -aspeed.c index 2bdd93a3f91f..22dde915e51b 100644 --- a/drivers/mmc/host/sdhci-of-aspeed.c +++ b/drivers/mmc/host/sdhci-of-aspeed.c @@ -241,7 +241,7 @@ static void aspeed_sdhci_set_clock(struct sdhci_host *h= ost, unsigned int clock) struct sdhci_pltfm_host *pltfm_host; unsigned long parent, bus; struct aspeed_sdhci *sdhci; - int div; + int div =3D 1; u16 clk; =20 pltfm_host =3D sdhci_priv(host); @@ -257,6 +257,9 @@ static void aspeed_sdhci_set_clock(struct sdhci_host *h= ost, unsigned int clock) if (WARN_ON(clock > host->max_clk)) clock =3D host->max_clk; =20 + if (sdhci->pdata) + div =3D sdhci->pdata->clk_div_start; + /* * Regarding the AST2600: * @@ -273,7 +276,7 @@ static void aspeed_sdhci_set_clock(struct sdhci_host *h= ost, unsigned int clock) * supporting the value 0 in (EMMC12C[7:6], EMMC12C[15:8]), and capture * the 0-value capability in clk_div_start. */ - for (div =3D sdhci->pdata->clk_div_start; div < 256; div *=3D 2) { + for (; div < 256; div *=3D 2) { bus =3D parent / div; if (bus <=3D clock) break; --=20 2.34.1 From nobody Fri Oct 10 09:21:29 2025 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DF3DE264608; Sun, 15 Jun 2025 03:58:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749959913; cv=none; b=e3vj0luoGXvReqYKlk9fq/eGI2VHnNNa+qbHckdykp5oDH3tCwUsS601YqoSxrRDXJifwXcvhIy8m8hu64spS7L47oln3Sfc5yOanHeXcIcwRlGky63KSj5tSXSSaqDfyqfPcDX+ourdeWpHJqJVnuspFARDpLStSXuIra1mPMY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749959913; c=relaxed/simple; bh=bHUS/Tk9LMBg9lQIuPHoyB6SeTAcyZ0KY8ozl+YM+RE=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Eo+8XUk3vvwwKnOft3OdPE98YIq0UjBMPLLpXpvldzmtCTrV7njTWerEbNijRWMvKAgFjHOZoZE4HDnqaGfXw3wqcn9hCvLSyCSKcCpRc03vKKk2DHaGK6EoIVS5ofMNci/Ba1t8r+w8lnQebaPsnEjJFl6bzVT+MTt7tfiBQu8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Sun, 15 Jun 2025 11:58:04 +0800 Received: from mail.aspeedtech.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Sun, 15 Jun 2025 11:58:04 +0800 From: Cool Lee To: , , , , , , , , , Subject: [PATCH 6/8] mmc: sdhci-of-aspeed: Add output timing phase tuning Date: Sun, 15 Jun 2025 11:58:01 +0800 Message-ID: <20250615035803.3752235-7-cool_lee@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250615035803.3752235-1-cool_lee@aspeedtech.com> References: <20250615035803.3752235-1-cool_lee@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enhance auto tuning with input and output calibration. Signed-off-by: Cool Lee --- drivers/mmc/host/sdhci-of-aspeed.c | 48 ++++++++++++++++++++++++++++-- 1 file changed, 46 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/host/sdhci-of-aspeed.c b/drivers/mmc/host/sdhci-of= -aspeed.c index 22dde915e51b..92687fc30d1d 100644 --- a/drivers/mmc/host/sdhci-of-aspeed.c +++ b/drivers/mmc/host/sdhci-of-aspeed.c @@ -25,6 +25,7 @@ #define ASPEED_SDC_S1_PHASE_IN GENMASK(25, 21) #define ASPEED_SDC_S0_PHASE_IN GENMASK(20, 16) #define ASPEED_SDC_S0_PHASE_IN_SHIFT 16 +#define ASPEED_SDC_S0_PHASE_OUT_SHIFT 3 #define ASPEED_SDC_S1_PHASE_OUT GENMASK(15, 11) #define ASPEED_SDC_S1_PHASE_IN_EN BIT(10) #define ASPEED_SDC_S1_PHASE_OUT_EN GENMASK(9, 8) @@ -422,7 +423,7 @@ static int aspeed_sdhci_execute_tuning(struct sdhci_hos= t *host, u32 opcode) } =20 window =3D right - left; - dev_info(dev, "tuning window =3D %d\n", window); + dev_dbg(dev, "tuning window[%d][%d~%d] =3D %d\n", edge, left, right, win= dow); =20 if (window > oldwindow) { oldwindow =3D window; @@ -433,7 +434,50 @@ static int aspeed_sdhci_execute_tuning(struct sdhci_ho= st *host, u32 opcode) val =3D (out_phase | enable_mask | (center << ASPEED_SDC_S0_PHASE_IN_SHIF= T)); writel(val, sdc->regs + ASPEED_SDC_PHASE); =20 - dev_info(dev, "tuning result=3D%x\n", val); + dev_dbg(dev, "input tuning result=3D%x\n", val); + + inverted =3D 0; + out_phase =3D val & ~ASPEED_SDC_S0_PHASE_OUT; + in_phase =3D out_phase; + oldwindow =3D 0; + + for (edge =3D 0; edge < 2; edge++) { + if (edge =3D=3D 1) + inverted =3D ASPEED_SDHCI_TAP_PARAM_INVERT_CLK; + + val =3D (in_phase | enable_mask | (inverted << ASPEED_SDC_S0_PHASE_OUT_S= HIFT)); + + /* find the left boundary */ + for (left =3D 0; left < ASPEED_SDHCI_NR_TAPS + 1; left++) { + out_phase =3D val | (left << ASPEED_SDC_S0_PHASE_OUT_SHIFT); + writel(out_phase, sdc->regs + ASPEED_SDC_PHASE); + + if (!mmc_send_tuning(host->mmc, opcode, NULL)) + break; + } + + /* find the right boundary */ + for (right =3D left + 1; right < ASPEED_SDHCI_NR_TAPS + 1; right++) { + out_phase =3D val | (right << ASPEED_SDC_S0_PHASE_OUT_SHIFT); + writel(out_phase, sdc->regs + ASPEED_SDC_PHASE); + + if (mmc_send_tuning(host->mmc, opcode, NULL)) + break; + } + + window =3D right - left; + dev_info(dev, "tuning window[%d][%d~%d] =3D %d\n", edge, left, right, wi= ndow); + + if (window > oldwindow) { + oldwindow =3D window; + center =3D (((right - 1) + left) / 2) | inverted; + } + } + + val =3D (in_phase | enable_mask | (center << ASPEED_SDC_S0_PHASE_OUT_SHIF= T)); + writel(val, sdc->regs + ASPEED_SDC_PHASE); + + dev_dbg(dev, "output tuning result=3D%x\n", val); =20 return mmc_send_tuning(host->mmc, opcode, NULL); } --=20 2.34.1 From nobody Fri Oct 10 09:21:29 2025 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DFA2E264A90; Sun, 15 Jun 2025 03:58:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Sun, 15 Jun 2025 11:58:04 +0800 Received: from mail.aspeedtech.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Sun, 15 Jun 2025 11:58:04 +0800 From: Cool Lee To: , , , , , , , , , Subject: [PATCH 7/8] mmc: sdhci-of-aspeed: Remove timing phase Date: Sun, 15 Jun 2025 11:58:02 +0800 Message-ID: <20250615035803.3752235-8-cool_lee@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250615035803.3752235-1-cool_lee@aspeedtech.com> References: <20250615035803.3752235-1-cool_lee@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The timing phase is no more needed since the auto tuning is applied. Signed-off-by: Cool Lee --- drivers/mmc/host/sdhci-of-aspeed.c | 178 +---------------------------- 1 file changed, 3 insertions(+), 175 deletions(-) diff --git a/drivers/mmc/host/sdhci-of-aspeed.c b/drivers/mmc/host/sdhci-of= -aspeed.c index 92687fc30d1d..365c02215273 100644 --- a/drivers/mmc/host/sdhci-of-aspeed.c +++ b/drivers/mmc/host/sdhci-of-aspeed.c @@ -34,6 +34,9 @@ #define ASPEED_SDC_S0_PHASE_OUT_EN GENMASK(1, 0) #define ASPEED_SDC_PHASE_MAX 31 =20 +#define ASPEED_SDHCI_TAP_PARAM_INVERT_CLK BIT(4) +#define ASPEED_SDHCI_NR_TAPS 15 + /* SDIO{10,20} */ #define ASPEED_SDC_CAP1_1_8V (0 * 32 + 26) /* SDIO{14,24} */ @@ -48,37 +51,14 @@ struct aspeed_sdc { void __iomem *regs; }; =20 -struct aspeed_sdhci_tap_param { - bool valid; - -#define ASPEED_SDHCI_TAP_PARAM_INVERT_CLK BIT(4) - u8 in; - u8 out; -}; - -struct aspeed_sdhci_tap_desc { - u32 tap_mask; - u32 enable_mask; - u8 enable_value; -}; - -struct aspeed_sdhci_phase_desc { - struct aspeed_sdhci_tap_desc in; - struct aspeed_sdhci_tap_desc out; -}; - struct aspeed_sdhci_pdata { unsigned int clk_div_start; - const struct aspeed_sdhci_phase_desc *phase_desc; - size_t nr_phase_descs; }; =20 struct aspeed_sdhci { const struct aspeed_sdhci_pdata *pdata; struct aspeed_sdc *parent; u32 width_mask; - struct mmc_clk_phase_map phase_map; - const struct aspeed_sdhci_phase_desc *phase_desc; }; =20 /* @@ -129,114 +109,6 @@ static void aspeed_sdc_configure_8bit_mode(struct asp= eed_sdc *sdc, spin_unlock(&sdc->lock); } =20 -static u32 -aspeed_sdc_set_phase_tap(const struct aspeed_sdhci_tap_desc *desc, - u8 tap, bool enable, u32 reg) -{ - reg &=3D ~(desc->enable_mask | desc->tap_mask); - if (enable) { - reg |=3D tap << __ffs(desc->tap_mask); - reg |=3D desc->enable_value << __ffs(desc->enable_mask); - } - - return reg; -} - -static void -aspeed_sdc_set_phase_taps(struct aspeed_sdc *sdc, - const struct aspeed_sdhci_phase_desc *desc, - const struct aspeed_sdhci_tap_param *taps) -{ - u32 reg; - - spin_lock(&sdc->lock); - reg =3D readl(sdc->regs + ASPEED_SDC_PHASE); - - reg =3D aspeed_sdc_set_phase_tap(&desc->in, taps->in, taps->valid, reg); - reg =3D aspeed_sdc_set_phase_tap(&desc->out, taps->out, taps->valid, reg); - - writel(reg, sdc->regs + ASPEED_SDC_PHASE); - spin_unlock(&sdc->lock); -} - -#define PICOSECONDS_PER_SECOND 1000000000000ULL -#define ASPEED_SDHCI_NR_TAPS 15 -/* Measured value with *handwave* environmentals and static loading */ -#define ASPEED_SDHCI_MAX_TAP_DELAY_PS 1253 -static int aspeed_sdhci_phase_to_tap(struct device *dev, unsigned long rat= e_hz, - int phase_deg) -{ - u64 phase_period_ps; - u64 prop_delay_ps; - u64 clk_period_ps; - unsigned int tap; - u8 inverted; - - phase_deg %=3D 360; - - if (phase_deg >=3D 180) { - inverted =3D ASPEED_SDHCI_TAP_PARAM_INVERT_CLK; - phase_deg -=3D 180; - dev_dbg(dev, - "Inverting clock to reduce phase correction from %d to %d degrees\n", - phase_deg + 180, phase_deg); - } else { - inverted =3D 0; - } - - prop_delay_ps =3D ASPEED_SDHCI_MAX_TAP_DELAY_PS / ASPEED_SDHCI_NR_TAPS; - clk_period_ps =3D div_u64(PICOSECONDS_PER_SECOND, (u64)rate_hz); - phase_period_ps =3D div_u64((u64)phase_deg * clk_period_ps, 360ULL); - - tap =3D div_u64(phase_period_ps, prop_delay_ps); - if (tap > ASPEED_SDHCI_NR_TAPS) { - dev_dbg(dev, - "Requested out of range phase tap %d for %d degrees of phase compensat= ion at %luHz, clamping to tap %d\n", - tap, phase_deg, rate_hz, ASPEED_SDHCI_NR_TAPS); - tap =3D ASPEED_SDHCI_NR_TAPS; - } - - return inverted | tap; -} - -static void -aspeed_sdhci_phases_to_taps(struct device *dev, unsigned long rate, - const struct mmc_clk_phase *phases, - struct aspeed_sdhci_tap_param *taps) -{ - taps->valid =3D phases->valid; - - if (!phases->valid) - return; - - taps->in =3D aspeed_sdhci_phase_to_tap(dev, rate, phases->in_deg); - taps->out =3D aspeed_sdhci_phase_to_tap(dev, rate, phases->out_deg); -} - -static void -aspeed_sdhci_configure_phase(struct sdhci_host *host, unsigned long rate) -{ - struct aspeed_sdhci_tap_param _taps =3D {0}, *taps =3D &_taps; - struct mmc_clk_phase *params; - struct aspeed_sdhci *sdhci; - struct device *dev; - - dev =3D mmc_dev(host->mmc); - sdhci =3D sdhci_pltfm_priv(sdhci_priv(host)); - - if (!sdhci->phase_desc) - return; - - params =3D &sdhci->phase_map.phase[host->timing]; - aspeed_sdhci_phases_to_taps(dev, rate, params, taps); - aspeed_sdc_set_phase_taps(sdhci->parent, sdhci->phase_desc, taps); - dev_dbg(dev, - "Using taps [%d, %d] for [%d, %d] degrees of phase correction at %luHz (= %d)\n", - taps->in & ASPEED_SDHCI_NR_TAPS, - taps->out & ASPEED_SDHCI_NR_TAPS, - params->in_deg, params->out_deg, rate, host->timing); -} - static void aspeed_sdhci_set_clock(struct sdhci_host *host, unsigned int c= lock) { struct sdhci_pltfm_host *pltfm_host; @@ -287,8 +159,6 @@ static void aspeed_sdhci_set_clock(struct sdhci_host *h= ost, unsigned int clock) =20 clk =3D div << SDHCI_DIVIDER_SHIFT; =20 - aspeed_sdhci_configure_phase(host, bus); - sdhci_enable_clk(host, clk); } =20 @@ -550,14 +420,6 @@ static int aspeed_sdhci_probe(struct platform_device *= pdev) else if (slot >=3D 2) return -EINVAL; =20 - if (slot < dev->pdata->nr_phase_descs) { - dev->phase_desc =3D &dev->pdata->phase_desc[slot]; - } else { - dev_info(&pdev->dev, - "Phase control not supported for slot %d\n", slot); - dev->phase_desc =3D NULL; - } - dev->width_mask =3D !slot ? ASPEED_SDC_S0_MMC8 : ASPEED_SDC_S1_MMC8; =20 dev_info(&pdev->dev, "Configured for slot %d\n", slot); @@ -589,9 +451,6 @@ static int aspeed_sdhci_probe(struct platform_device *p= dev) if (ret) goto err_sdhci_add; =20 - if (dev->phase_desc) - mmc_of_parse_clk_phase(&pdev->dev, &dev->phase_map); - ret =3D sdhci_add_host(host); if (ret) goto err_sdhci_add; @@ -624,39 +483,8 @@ static const struct aspeed_sdhci_pdata ast2400_sdhci_p= data =3D { .clk_div_start =3D 2, }; =20 -static const struct aspeed_sdhci_phase_desc ast2600_sdhci_phase[] =3D { - /* SDHCI/Slot 0 */ - [0] =3D { - .in =3D { - .tap_mask =3D ASPEED_SDC_S0_PHASE_IN, - .enable_mask =3D ASPEED_SDC_S0_PHASE_IN_EN, - .enable_value =3D 1, - }, - .out =3D { - .tap_mask =3D ASPEED_SDC_S0_PHASE_OUT, - .enable_mask =3D ASPEED_SDC_S0_PHASE_OUT_EN, - .enable_value =3D 3, - }, - }, - /* SDHCI/Slot 1 */ - [1] =3D { - .in =3D { - .tap_mask =3D ASPEED_SDC_S1_PHASE_IN, - .enable_mask =3D ASPEED_SDC_S1_PHASE_IN_EN, - .enable_value =3D 1, - }, - .out =3D { - .tap_mask =3D ASPEED_SDC_S1_PHASE_OUT, - .enable_mask =3D ASPEED_SDC_S1_PHASE_OUT_EN, - .enable_value =3D 3, - }, - }, -}; - static const struct aspeed_sdhci_pdata ast2600_sdhci_pdata =3D { .clk_div_start =3D 1, - .phase_desc =3D ast2600_sdhci_phase, - .nr_phase_descs =3D ARRAY_SIZE(ast2600_sdhci_phase), }; =20 static const struct of_device_id aspeed_sdhci_of_match[] =3D { --=20 2.34.1 From nobody Fri Oct 10 09:21:29 2025 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E468F26528E; Sun, 15 Jun 2025 03:58:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749959919; cv=none; b=r+a5cElkhvl+YcfpYs/1cIrD8Vh2Yjmj3Oa4doyOQKNKcl8/Q13Xwl0a/w+JOmaZD73j70HdQ/Yx9BQcIhCncelLbqiG7suk3N+Z51BqAqH3zf07hfsReN3+Fkvl+AvDsildlKYDZiwq8x8dW8merZBEQfUyGnZVc71yt6Dk7q4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749959919; c=relaxed/simple; bh=lSminI9thQ4D1Cmx3meEA7cWQlap1VEYZBL1D6u9zH0=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=MVwSi+vihrnq4ToRMynWKvNTgy5yGeyVunGL2buxRjfJyzWir8WzQSnWnFbnnWrbevURfABgQQ7xYhXWDzdr61Makf/BixLB4zF4EtV/Tz5qFs6b0ZZLsBGEqlvds0m1ezylhCXcU8qSRoJl0W6QQBDA9WpGB1yDcnGt+2IUwZE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Sun, 15 Jun 2025 11:58:04 +0800 Received: from mail.aspeedtech.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Sun, 15 Jun 2025 11:58:04 +0800 From: Cool Lee To: , , , , , , , , , Subject: [PATCH 8/8] mmc: sdhci-of-aspeed: Add sdr50 support Date: Sun, 15 Jun 2025 11:58:03 +0800 Message-ID: <20250615035803.3752235-9-cool_lee@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250615035803.3752235-1-cool_lee@aspeedtech.com> References: <20250615035803.3752235-1-cool_lee@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for SDR50 mode in the Aspeed SDHCI driver by setting capability shadow register. Signed-off-by: Cool Lee Reviewed-by: Andrew Jeffery --- drivers/mmc/host/sdhci-of-aspeed.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/mmc/host/sdhci-of-aspeed.c b/drivers/mmc/host/sdhci-of= -aspeed.c index 365c02215273..ec6833295b6a 100644 --- a/drivers/mmc/host/sdhci-of-aspeed.c +++ b/drivers/mmc/host/sdhci-of-aspeed.c @@ -41,6 +41,7 @@ #define ASPEED_SDC_CAP1_1_8V (0 * 32 + 26) /* SDIO{14,24} */ #define ASPEED_SDC_CAP2_SDR104 (1 * 32 + 1) +#define ASPEED_SDC_CAP2_SDR50 (1 * 32 + 0) =20 struct aspeed_sdc { struct clk *clk; @@ -427,11 +428,17 @@ static int aspeed_sdhci_probe(struct platform_device = *pdev) sdhci_get_of_property(pdev); =20 if (of_property_read_bool(np, "mmc-hs200-1_8v") || + of_property_read_bool(np, "sd-uhs-sdr50") || of_property_read_bool(np, "sd-uhs-sdr104")) { aspeed_sdc_set_slot_capability(host, dev->parent, ASPEED_SDC_CAP1_1_8V, true, slot); } =20 + if (of_property_read_bool(np, "sd-uhs-sdr50")) { + aspeed_sdc_set_slot_capability(host, dev->parent, ASPEED_SDC_CAP2_SDR50, + true, slot); + } + if (of_property_read_bool(np, "sd-uhs-sdr104")) { aspeed_sdc_set_slot_capability(host, dev->parent, ASPEED_SDC_CAP2_SDR104, true, slot); --=20 2.34.1