From nobody Fri Oct 10 02:44:40 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E4BD426AA91; Sun, 15 Jun 2025 20:35:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750019750; cv=none; b=SH5wP/vvxSKEomSFzdHRSxi0k/k/YD+zWhDWlkTSO6z4wJHhnaLnbwEMi5HQ5UNnUsd2IGxN9RVrUcf33lTgLqSiaUHKDJtZewYwlVQ/oP14OZJN7WQOSmMBXUEwc7u2tXpaC7lLbHu+vCthCv99A27/2iG9VjkLhQvD8s7cpCY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750019750; c=relaxed/simple; bh=egU0n+65roSHxWhTVtVk29C1nXnroRGzUZWjFXyLw1s=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=uwAnUvG+vpb9UtM4qf+4aXNXmgXtxWRehHsANTj4+8FNYk15xwGC4t2hJCw7ewI3Cosz9+hklqpQFGomRWQRXK8dCwgrre3DqQnI40h40NuNFuXQGGj5KMdfh1YN69/23CxNkj6EHOJmc4N5922W53I5yW6ATBxa2dUlYrG/1QA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=O/NUABMp; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="O/NUABMp" Received: by smtp.kernel.org (Postfix) with ESMTPS id 681ECC4CEEE; Sun, 15 Jun 2025 20:35:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1750019749; bh=egU0n+65roSHxWhTVtVk29C1nXnroRGzUZWjFXyLw1s=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=O/NUABMpeNrOXSBVVP0pcrWe+9NTGnuiKsvmb+NgdkGl1CTXBCoNA4OQGOk4YDPW6 jAmjJeihcVeYFIFHY/ES+whREJPmXKiYXNeOcUTZkzJA8+ASY1LIWkaQD6n+xXNC4A Nfru2TcMaPTtR8Ziix/RfQwjdtp7S8YvgPLSKxp1tQbsUJ69tsQ5C7EpBteIC75a+h vhsAU3b0TJWPsAp6qFLrHIKCSkQWB2c4QCtMdEVVuAntwB+ueI0RYvT4qXwXxjy1xq YSqtagETZ0j0oJOTuN6lFzFQfuhj9lfOMl4KaZPkHyM9mfvXLz5aabMGZk/hhfOmTK l9v6r8sl3wMqw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4986AC71150; Sun, 15 Jun 2025 20:35:49 +0000 (UTC) From: =?utf-8?q?Andr=C3=A9_Apitzsch_via_B4_Relay?= Date: Sun, 15 Jun 2025 22:35:03 +0200 Subject: [PATCH v2 1/4] arm64: dts: qcom: msm8976: Make blsp_dma controlled-remotely Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250615-bqx5plus-v2-1-72b45c84237d@apitzsch.eu> References: <20250615-bqx5plus-v2-0-72b45c84237d@apitzsch.eu> In-Reply-To: <20250615-bqx5plus-v2-0-72b45c84237d@apitzsch.eu> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , AngeloGioacchino Del Regno , Marijn Suijten Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , =?utf-8?q?Andr=C3=A9_Apitzsch?= , Konrad Dybcio X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1750019747; l=1769; i=git@apitzsch.eu; s=20240325; h=from:subject:message-id; bh=tou8+NFaKkVAfh9dyXrj9kZqM4iUPndfWaC+WwSYyHc=; b=4Xmoe6/myYB3cYhDeLzNJWgowocjQ8LtNC6kZwXhFxmvB1UuR2G5bjZxqiy+Z3DEC2Xbfb00A TAvF9S8o3inBADxfUyOLYNniIVRlim3HbM2AMDILVpiMAmZuCTFZnLF X-Developer-Key: i=git@apitzsch.eu; a=ed25519; pk=wxovcZRfvNYBMcTw4QFFtNEP4qv39gnBfnfyImXZxiU= X-Endpoint-Received: by B4 Relay for git@apitzsch.eu/20240325 with auth_id=142 X-Original-From: =?utf-8?q?Andr=C3=A9_Apitzsch?= Reply-To: git@apitzsch.eu From: Andr=C3=A9 Apitzsch The blsp_dma controller is shared between the different subsystems, which is why it is already initialized by the firmware. We should not reinitialize it from Linux to avoid potential other users of the DMA engine to misbehave. In mainline this can be described using the "qcom,controlled-remotely" property. In the downstream/vendor kernel from Qualcomm there is an opposite "qcom,managed-locally" property. This property is *not* set for the qcom,sps-dma@7884000 and qcom,sps-dma@7ac4000 [1] so adding "qcom,controlled-remotely" upstream matches the behavior of the downstream/vendor kernel. Adding this fixes booting Longcheer L9360. [1]: https://git.codelinaro.org/clo/la/kernel/msm-3.10/-/blob/LA.BR.1.3.7.c= 26/arch/arm/boot/dts/qcom/msm8976.dtsi#L1149-1163 Fixes: 0484d3ce0902 ("arm64: dts: qcom: Add DTS for MSM8976 and MSM8956 SoC= s") Reviewed-by: Konrad Dybcio Signed-off-by: Andr=C3=A9 Apitzsch --- arch/arm64/boot/dts/qcom/msm8976.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8976.dtsi b/arch/arm64/boot/dts/qc= om/msm8976.dtsi index e2ac2fd6882fcf47e846a92d45e0fcb9beba633a..2a30246384700dac2ec868c6f37= 1248cfcc643fc 100644 --- a/arch/arm64/boot/dts/qcom/msm8976.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8976.dtsi @@ -1331,6 +1331,7 @@ blsp1_dma: dma-controller@7884000 { clock-names =3D "bam_clk"; #dma-cells =3D <1>; qcom,ee =3D <0>; + qcom,controlled-remotely; }; =20 blsp1_uart1: serial@78af000 { @@ -1451,6 +1452,7 @@ blsp2_dma: dma-controller@7ac4000 { clock-names =3D "bam_clk"; #dma-cells =3D <1>; qcom,ee =3D <0>; + qcom,controlled-remotely; }; =20 blsp2_uart2: serial@7af0000 { --=20 2.49.0 From nobody Fri Oct 10 02:44:40 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2774127FB31; Sun, 15 Jun 2025 20:35:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750019750; cv=none; b=vDs/s2B+FDnCIhK+U5CzLqwgZ16Q8DFJhOWROD54ownvDcmh5qRLlpE/NCTVFyHAAY3sRJRPJlp9auJgAcKyAaC9XscwqTskt/dCP7ESsodD8F3qVbfVKbhaXvynS/IgO/4bew8dURLUSso7v8FZBcWVUFiEidJIneiCS+Z1OS0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750019750; c=relaxed/simple; bh=BuGkE3E1AEr1z3MC3ft91Kq0SflMY1/y45MNOn4L5EE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=fw4C1/6f636AotGMKq6jDPX7u75O/KWET5zgsF1bFpuqMxAkrbgX9cdtQgE8Hqf6u8+CoFb3wO/Hl6djRxSqepU9MDCGgvB2O6hiFv6q+2bY2sK/g0z+DH9Q3DMEYHQ+rknSElucflb4/AP0bP9eiOZdz2Mf27O3l4egmoAmSHw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=EIEMXVYj; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="EIEMXVYj" Received: by smtp.kernel.org (Postfix) with ESMTPS id 8DDE4C4CEF6; Sun, 15 Jun 2025 20:35:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1750019749; bh=BuGkE3E1AEr1z3MC3ft91Kq0SflMY1/y45MNOn4L5EE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=EIEMXVYj+6c9f1dyRx6B7LCIkgn0KIONCmKii9UfpKEKl1O9oy/RXuipIo2e498Dm HMCIzDq2A6Ht/kYhCCUcKH7yod+faRc5MG232n9asO8TbRG6nxbhPRquiaCnkbj8Io PZoWTGAbyM4dhYTAbPgZS3n78LqkN0mG7ucZBycqoQIuicQYe5eWE+f/7K2WBOuiBp rr9sFwLGUhXzfp2uJ+B9fCHpn44XBPVLPD7e1ZbUmAT4kIrKyVtKmpIa8scqLfjWEc IGKEcxMfGcynfjaISJBaBtHfvsK2UlZAH8ovQ1lR5rPLGIUdkdjgO/RqtQFc0WWls9 xNS0lxqkL211A== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7A4AEC71155; Sun, 15 Jun 2025 20:35:49 +0000 (UTC) From: =?utf-8?q?Andr=C3=A9_Apitzsch_via_B4_Relay?= Date: Sun, 15 Jun 2025 22:35:04 +0200 Subject: [PATCH v2 2/4] dt-bindings: arm: qcom: Add MSM8976 BQ Aquaris X5 Plus Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250615-bqx5plus-v2-2-72b45c84237d@apitzsch.eu> References: <20250615-bqx5plus-v2-0-72b45c84237d@apitzsch.eu> In-Reply-To: <20250615-bqx5plus-v2-0-72b45c84237d@apitzsch.eu> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , AngeloGioacchino Del Regno , Marijn Suijten Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , =?utf-8?q?Andr=C3=A9_Apitzsch?= X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1750019747; l=847; i=git@apitzsch.eu; s=20240325; h=from:subject:message-id; bh=dI/0IRSIfadPPMn3LJmHpD092PxglhBVPQzVyv8YEEE=; b=0VBUKn+9rVlZx6PgT7UUtdMVOT/rdaBSzSdQDw04Ik9164kVYxwT6yl1VceC7Cur6Mh5MzElF r+GLLX4dJo4CYxajtuOw0whij7NJaOh0QV9IgPQL+XvWyxnlHhTO8dQ X-Developer-Key: i=git@apitzsch.eu; a=ed25519; pk=wxovcZRfvNYBMcTw4QFFtNEP4qv39gnBfnfyImXZxiU= X-Endpoint-Received: by B4 Relay for git@apitzsch.eu/20240325 with auth_id=142 X-Original-From: =?utf-8?q?Andr=C3=A9_Apitzsch?= Reply-To: git@apitzsch.eu From: Andr=C3=A9 Apitzsch BQ Aquaris X5 Plus (Longcheer L9360) is a smartphone based on MSM8976 SoC. Signed-off-by: Andr=C3=A9 Apitzsch Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/qcom.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentatio= n/devicetree/bindings/arm/qcom.yaml index 56f78f0f3803fedcb6422efd6adec3bbc81c2e03..1ca79192590f9e55de53d7fc7fe= 51c1b9a4a77bc 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -230,6 +230,11 @@ properties: - const: qcom,msm8974pro - const: qcom,msm8974 =20 + - items: + - enum: + - longcheer,l9360 + - const: qcom,msm8976 + - items: - enum: - acer,a1-724 --=20 2.49.0 From nobody Fri Oct 10 02:44:40 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3284C27FD5A; Sun, 15 Jun 2025 20:35:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250615-bqx5plus-v2-3-72b45c84237d@apitzsch.eu> References: <20250615-bqx5plus-v2-0-72b45c84237d@apitzsch.eu> In-Reply-To: <20250615-bqx5plus-v2-0-72b45c84237d@apitzsch.eu> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , AngeloGioacchino Del Regno , Marijn Suijten Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , =?utf-8?q?Andr=C3=A9_Apitzsch?= X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1750019747; l=1549; i=git@apitzsch.eu; s=20240325; h=from:subject:message-id; bh=pHim4zTcI1zPighoZ6+v0/0r8e8R848pZckDF2/W8QA=; b=VRDWgDOraNRiBI3Pgg4AP7ksyB8wqXOeFjFram8SpHlIICeMb4/1NSzuH8hUeTw6A8h8fxneW fepDfuEXmmACDwXieh0+58U+ZMyUFiW/wgiHQf+MJjjQsN6DFwz76Ek X-Developer-Key: i=git@apitzsch.eu; a=ed25519; pk=wxovcZRfvNYBMcTw4QFFtNEP4qv39gnBfnfyImXZxiU= X-Endpoint-Received: by B4 Relay for git@apitzsch.eu/20240325 with auth_id=142 X-Original-From: =?utf-8?q?Andr=C3=A9_Apitzsch?= Reply-To: git@apitzsch.eu From: Andr=C3=A9 Apitzsch Downstream vendor code for reference: https://git.codelinaro.org/clo/la/kernel/msm-3.10/-/blob/LA.BR.1.3.7.c26/ar= ch/arm/boot/dts/qcom/msm8976-pinctrl.dtsi#L223-263 Signed-off-by: Andr=C3=A9 Apitzsch Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/msm8976.dtsi | 36 +++++++++++++++++++++++++++++++= ++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8976.dtsi b/arch/arm64/boot/dts/qc= om/msm8976.dtsi index 2a30246384700dac2ec868c6f371248cfcc643fc..f9962512f243d6c1af4931787f4= 602554c63bb39 100644 --- a/arch/arm64/boot/dts/qcom/msm8976.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8976.dtsi @@ -782,6 +782,42 @@ blsp2_i2c4_sleep: blsp2-i2c4-sleep-state { bias-disable; }; =20 + sdc2_default: sdc2-default-state { + clk-pins { + pins =3D "sdc2_clk"; + bias-disable; + drive-strength =3D <16>; + }; + cmd-pins { + pins =3D "sdc2_cmd"; + bias-pull-up; + drive-strength =3D <10>; + }; + data-pins { + pins =3D "sdc2_data"; + bias-pull-up; + drive-strength =3D <10>; + }; + }; + + sdc2_sleep: sdc2-sleep-state { + clk-pins { + pins =3D "sdc2_clk"; + bias-disable; + drive-strength =3D <2>; + }; + cmd-pins { + pins =3D "sdc2_cmd"; + bias-pull-up; + drive-strength =3D <2>; + }; + data-pins { + pins =3D "sdc2_data"; + bias-pull-up; + drive-strength =3D <2>; + }; + }; + wcss_wlan_default: wcss-wlan-default-state { wcss-wlan2-pins { pins =3D "gpio40"; --=20 2.49.0 From nobody Fri Oct 10 02:44:40 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1CF7627A461; Sun, 15 Jun 2025 20:35:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250615-bqx5plus-v2-4-72b45c84237d@apitzsch.eu> References: <20250615-bqx5plus-v2-0-72b45c84237d@apitzsch.eu> In-Reply-To: <20250615-bqx5plus-v2-0-72b45c84237d@apitzsch.eu> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , AngeloGioacchino Del Regno , Marijn Suijten Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , =?utf-8?q?Andr=C3=A9_Apitzsch?= X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1750019747; l=12211; i=git@apitzsch.eu; s=20240325; h=from:subject:message-id; bh=iCvZ4oUsF248e81pz4vKFgOXWY73sktF13U1grP1f1I=; b=EHm8qteZDocE9aDNBZvwiN9ZgeTUmPIWqtSW376RASNszZvJA6zGsk7Q/GeY7/JDDMcHTAvLo VLSeEgP42LnA2t7irXe+GxQynBYI+JzSrTPxfwuNqy1avryN9tsUuxi X-Developer-Key: i=git@apitzsch.eu; a=ed25519; pk=wxovcZRfvNYBMcTw4QFFtNEP4qv39gnBfnfyImXZxiU= X-Endpoint-Received: by B4 Relay for git@apitzsch.eu/20240325 with auth_id=142 X-Original-From: =?utf-8?q?Andr=C3=A9_Apitzsch?= Reply-To: git@apitzsch.eu From: Andr=C3=A9 Apitzsch This dts adds support for BQ Aquaris X5 Plus (Longcheer L9360) released in 2016. Add a device tree with initial support for: - GPIO keys - NFC - SDHCI - Status LED - Touchscreen Signed-off-by: Andr=C3=A9 Apitzsch --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../boot/dts/qcom/msm8976-longcheer-l9360.dts | 490 +++++++++++++++++= ++++ 2 files changed, 491 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index 669b888b27a1daa93ac15f47e8b9a302bb0922c2..80fd9a910af478558bb840f7ce5= aa52948912be0 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -77,6 +77,7 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D msm8953-xiaomi-tissot.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8953-xiaomi-vince.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8956-sony-xperia-loire-kugo.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8956-sony-xperia-loire-suzu.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D msm8976-longcheer-l9360.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8992-lg-bullhead-rev-10.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8992-lg-bullhead-rev-101.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8992-lg-h815.dtb diff --git a/arch/arm64/boot/dts/qcom/msm8976-longcheer-l9360.dts b/arch/ar= m64/boot/dts/qcom/msm8976-longcheer-l9360.dts new file mode 100644 index 0000000000000000000000000000000000000000..e524d58cf0a4b7693741036e398= 8700559a507f0 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8976-longcheer-l9360.dts @@ -0,0 +1,490 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2025, Andr=C3=A9 Apitzsch + */ + +/dts-v1/; + +#include + +#include "msm8976.dtsi" +#include "pm8004.dtsi" +#include "pm8950.dtsi" + +/ { + model =3D "BQ Aquaris X5 Plus (Longcheer L9360)"; + compatible =3D "longcheer,l9360", "qcom,msm8976"; + chassis-type =3D "handset"; + + aliases { + mmc0 =3D &sdhc_1; /* SDC1 eMMC slot */ + mmc1 =3D &sdhc_2; /* SDC2 SD card slot */ + }; + + chosen { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + framebuffer0: framebuffer@83200000 { + compatible =3D "simple-framebuffer"; + reg =3D <0x0 0x83200000 0x0 (1080 * 1920 * 3)>; + width =3D <1080>; + height =3D <1920>; + stride =3D <(1080 * 3)>; + format =3D "r8g8b8"; + + power-domains =3D <&gcc MDSS_GDSC>; + + clocks =3D <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>, + <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_BYTE0_CLK>, + <&gcc GCC_MDSS_PCLK0_CLK>, + <&gcc GCC_MDSS_ESC0_CLK>; + }; + }; + + gpio-keys { + compatible =3D "gpio-keys"; + + pinctrl-0 =3D <&hall_sensor_default>, <&volume_up_default>; + pinctrl-names =3D "default"; + + event-hall-sensor { + label =3D "Hall Effect Sensor"; + gpios =3D <&tlmm 107 GPIO_ACTIVE_HIGH>; + linux,input-type =3D ; + linux,code =3D ; + linux,can-disable; + wakeup-source; + }; + + key-volume-up { + label =3D "Volume Up"; + gpios =3D <&tlmm 113 GPIO_ACTIVE_LOW>; + linux,code =3D ; + }; + }; + + leds { + compatible =3D "gpio-leds"; + + led-0 { + gpios =3D <&tlmm 101 GPIO_ACTIVE_HIGH>; + color =3D ; + default-state =3D "off"; + function =3D LED_FUNCTION_KBD_BACKLIGHT; + + pinctrl-0 =3D <&button_backlight_default>; + pinctrl-names =3D "default"; + }; + }; + + reg_ts_vdd: regulator-vdd-ts { + compatible =3D "regulator-fixed"; + regulator-name =3D "regulator-vdd-ts"; + + gpio =3D <&tlmm 33 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reserved-memory { + framebuffer@83000000 { + reg =3D <0x0 0x83000000 0x0 0x2800000>; + no-map; + }; + }; + + vph_pwr: regulator-vph-pwr { + compatible =3D "regulator-fixed"; + regulator-name =3D "vph-pwr"; + regulator-always-on; + regulator-boot-on; + }; +}; + +&blsp1_i2c2 { + status =3D "okay"; + + led-controller@30 { + compatible =3D "kinetic,ktd2026"; + reg =3D <0x30>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + multi-led { + color =3D ; + function =3D LED_FUNCTION_STATUS; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + led@0 { + reg =3D <0>; + color =3D ; + }; + + led@1 { + reg =3D <1>; + color =3D ; + }; + + led@2 { + reg =3D <2>; + color =3D ; + }; + }; + }; +}; + +&blsp1_i2c4 { + status =3D "okay"; + + nfc@28 { + compatible =3D "nxp,pn547", "nxp,nxp-nci-i2c"; + reg =3D <0x28>; + + interrupts-extended =3D <&tlmm 140 IRQ_TYPE_EDGE_RISING>; + + enable-gpios =3D <&tlmm 122 GPIO_ACTIVE_HIGH>; + firmware-gpios =3D <&tlmm 109 GPIO_ACTIVE_HIGH>; + + pinctrl-0 =3D <&nfc_default>; + pinctrl-1 =3D <&nfc_sleep>; + pinctrl-names =3D "default", "sleep"; + }; +}; + +&blsp2_i2c2 { + status =3D "okay"; + + touchscreen@20 { + reg =3D <0x20>; + compatible =3D "syna,rmi4-i2c"; + + interrupts-extended =3D <&tlmm 65 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-0 =3D <&ts_int_default>, <&ts_reset_default>; + pinctrl-1 =3D <&ts_int_sleep>, <&ts_reset_sleep>; + pinctrl-names =3D "default", "sleep"; + + vdd-supply =3D <&pm8950_l6>; + vio-supply =3D <®_ts_vdd>; + + reset-gpios =3D <&tlmm 64 GPIO_ACTIVE_LOW>; + + syna,reset-delay-ms =3D <200>; + syna,startup-delay-ms =3D <200>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + rmi4-f01@1 { + reg =3D <0x1>; + syna,nosleep-mode =3D <1>; + }; + + rmi4-f12@12 { + reg =3D <0x12>; + syna,sensor-type =3D <1>; + }; + }; +}; + +&blsp2_uart2 { + status =3D "okay"; +}; + +&gcc { + vdd_gfx-supply =3D <&pm8004_s5>; +}; + +&pm8004_spmi_regulators { + vdd_s2-supply =3D <&vph_pwr>; + vdd_s5-supply =3D <&vph_pwr>; + + /* Cluster 1 supply */ + pm8004_s2: s2 { + /* regulator-min-microvolt =3D <500000>; */ + /* Set .95V to prevent unstabilities until CPR for this SoC is done */ + regulator-min-microvolt =3D <950000>; + regulator-max-microvolt =3D <1165000>; + regulator-name =3D "vdd_apc1"; + /* Set always on until the CPU PLL is done */ + regulator-always-on; + regulator-boot-on; + }; + + pm8004_s5: s5 { + regulator-min-microvolt =3D <950000>; + regulator-max-microvolt =3D <1165000>; + regulator-enable-ramp-delay =3D <500>; + regulator-name =3D "vdd_gfx"; + /* Hack this on until the gpu driver is ready for it */ + regulator-always-on; + }; +}; + +&pm8950_resin { + linux,code =3D ; + status =3D "okay"; +}; + +&pm8950_spmi_regulators { + vdd_s5-supply =3D <&vph_pwr>; + + /* Cluster 0 supply */ + pm8950_spmi_s5: s5 { + /* Set .95V to prevent unstabilities until CPR for this SoC is done */ + /* regulator-min-microvolt =3D <500000>; */ + regulator-min-microvolt =3D <950000>; + regulator-max-microvolt =3D <1165000>; + regulator-name =3D "vdd_apc0"; + /* Set always on until the CPU PLL is done */ + regulator-always-on; + regulator-boot-on; + }; +}; + +&rpm_requests { + pm8950_regulators: regulators { + compatible =3D "qcom,rpm-pm8950-regulators"; + + vdd_s1-supply =3D <&vph_pwr>; + vdd_s2-supply =3D <&vph_pwr>; + vdd_s3-supply =3D <&vph_pwr>; + vdd_s4-supply =3D <&vph_pwr>; + vdd_s6-supply =3D <&vph_pwr>; + vdd_l1_l19-supply =3D <&pm8950_s3>; + vdd_l2_l23-supply =3D <&pm8950_s3>; + vdd_l3-supply =3D <&pm8950_s3>; + vdd_l5_l6_l7_l16-supply =3D <&pm8950_s4>; + vdd_l8_l11_l12_l17_l22-supply =3D <&vph_pwr>; + + pm8950_s1: s1 { + regulator-min-microvolt =3D <1000000>; + regulator-max-microvolt =3D <1162500>; + }; + + pm8950_s3: s3 { + regulator-min-microvolt =3D <1325000>; + regulator-max-microvolt =3D <1325000>; + }; + + pm8950_s4: s4 { + regulator-min-microvolt =3D <2050000>; + regulator-max-microvolt =3D <2050000>; + }; + + pm8950_l1: l1 { + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + }; + + pm8950_l2: l2 { + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + }; + + pm8950_l3: l3 { + regulator-min-microvolt =3D <1000000>; + regulator-max-microvolt =3D <1100000>; + }; + + pm8950_l5: l5 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + }; + + pm8950_l6: l6 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + }; + + pm8950_l7: l7 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + }; + + pm8950_l8: l8 { + regulator-min-microvolt =3D <2900000>; + regulator-max-microvolt =3D <2900000>; + }; + + pm8950_l9: l9 { + regulator-min-microvolt =3D <3000000>; + regulator-max-microvolt =3D <3300000>; + }; + + pm8950_l10: l10 { + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + }; + + pm8950_l11: l11 { + regulator-min-microvolt =3D <2950000>; + regulator-max-microvolt =3D <2950000>; + }; + + pm8950_l12: l12 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <2950000>; + }; + + pm8950_l13: l13 { + regulator-min-microvolt =3D <3075000>; + regulator-max-microvolt =3D <3075000>; + }; + + pm8950_l14: l14 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + }; + + pm8950_l15: l15 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + }; + + pm8950_l16: l16 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + }; + + pm8950_l17: l17 { + regulator-min-microvolt =3D <2850000>; + regulator-max-microvolt =3D <2850000>; + }; + + pm8950_l19: l19 { + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1350000>; + }; + + pm8950_l22: l22 { + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + }; + + pm8950_l23: l23 { + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + }; + }; +}; + +&sdhc_1 { + bus-width =3D <8>; + non-removable; + vmmc-supply =3D <&pm8950_l8>; + vqmmc-supply =3D <&pm8950_l5>; + status =3D "okay"; +}; + +&sdhc_2 { + bus-width =3D <4>; + cd-gpios =3D <&tlmm 100 GPIO_ACTIVE_LOW>; + vmmc-supply =3D <&pm8950_l11>; + vqmmc-supply =3D <&pm8950_l12>; + + pinctrl-0 =3D <&sdc2_default>, <&sdc2_cd_default>; + pinctrl-1 =3D <&sdc2_sleep>, <&sdc2_cd_sleep>; + pinctrl-names =3D "default", "sleep"; + + status =3D "okay"; +}; + +&tlmm { + gpio-reserved-ranges =3D <0 4>; + + button_backlight_default: button-backlight-default-state { + pins =3D "gpio101"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + hall_sensor_default: hall-sensor-default-state { + pins =3D "gpio107"; + function =3D "gpio"; + drive-strength =3D <6>; + bias-pull-up; + }; + + nfc_default: nfc-default-state { + pins =3D "gpio122", "gpio140"; + function =3D "gpio"; + drive-strength =3D <6>; + bias-pull-up; + }; + + nfc_sleep: nfc-sleep-state { + int-pins { + pins =3D "gpio140"; + function =3D "gpio"; + drive-strength =3D <6>; + bias-pull-up; + }; + ven-pins { + pins =3D "gpio122"; + function =3D "gpio"; + drive-strength =3D <6>; + bias-disable; + }; + }; + + sdc2_cd_default: sdc2-cd-default-state { + pins =3D "gpio100"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + + sdc2_cd_sleep: sdc2-cd-sleep-state { + pins =3D "gpio100"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + ts_int_default: ts-int-state { + pins =3D "gpio65"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + + ts_int_sleep: ts-int-state { + pins =3D "gpio65"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + + ts_reset_default: ts-reset-state { + pins =3D "gpio64"; + function =3D "gpio"; + drive-strength =3D <8>; + bias-pull-up; + }; + + ts_reset_sleep: ts-sleep-state { + pins =3D "gpio64"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + + volume_up_default: volume-up-default-state { + pins =3D "gpio113"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; +}; + +&xo_board { + clock-frequency =3D <19200000>; +}; --=20 2.49.0