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[36.228.20.239]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-74890006059sm3565303b3a.55.2025.06.14.07.55.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 14 Jun 2025 07:56:02 -0700 (PDT) From: Wei-Lin Chang To: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org Cc: Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Wei-Lin Chang , Will Deacon , Jintack Lim , Christoffer Dall Subject: [PATCH] KVM: arm64: nv: Fix s_cpu_if->vgic_lr[] indexing in vgic_v3_put_nested() Date: Sat, 14 Jun 2025 22:57:21 +0800 Message-ID: <20250614145721.2504524-1-r09922117@csie.ntu.edu.tw> X-Mailer: git-send-email 2.49.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Gm-Spam: 0 X-Gm-Phishy: 0 Content-Type: text/plain; charset="utf-8" s_cpu_if->vgic_lr[] is filled continuously from index 0 to s_cpu_if->used_lrs - 1, but vgic_v3_put_nested() is indexing it using the positions of the set bits in shadow_if->lr_map. So correct it. Signed-off-by: Wei-Lin Chang Reported-by: Wei-Lin Chang Reviewed-by: Oliver Upton Reviewed-by: Wei-Lin Chang --- arch/arm64/kvm/vgic/vgic-v3-nested.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/arm64/kvm/vgic/vgic-v3-nested.c b/arch/arm64/kvm/vgic/vgi= c-v3-nested.c index 4f6954c30674..29741e3f077b 100644 --- a/arch/arm64/kvm/vgic/vgic-v3-nested.c +++ b/arch/arm64/kvm/vgic/vgic-v3-nested.c @@ -343,7 +343,7 @@ void vgic_v3_put_nested(struct kvm_vcpu *vcpu) struct shadow_if *shadow_if =3D get_shadow_if(); struct vgic_v3_cpu_if *s_cpu_if =3D &shadow_if->cpuif; u64 val; - int i; + int i, index =3D 0; =20 __vgic_v3_save_vmcr_aprs(s_cpu_if); __vgic_v3_deactivate_traps(s_cpu_if); @@ -368,10 +368,11 @@ void vgic_v3_put_nested(struct kvm_vcpu *vcpu) val =3D __vcpu_sys_reg(vcpu, ICH_LRN(i)); =20 val &=3D ~ICH_LR_STATE; - val |=3D s_cpu_if->vgic_lr[i] & ICH_LR_STATE; + val |=3D s_cpu_if->vgic_lr[index] & ICH_LR_STATE; =20 __vcpu_sys_reg(vcpu, ICH_LRN(i)) =3D val; - s_cpu_if->vgic_lr[i] =3D 0; + s_cpu_if->vgic_lr[index] =3D 0; + index++; } =20 shadow_if->lr_map =3D 0; --=20 2.49.0