From nobody Fri Oct 10 09:24:29 2025 Received: from mailout2.w1.samsung.com (mailout2.w1.samsung.com [210.118.77.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A6D052E7F10 for ; Sat, 14 Jun 2025 18:09:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.118.77.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749924558; cv=none; b=O6AMktOuey2JRg+hxvatOpYK7gGqr3mmx5RzUxyowswB7Ra8NAWHrAzamnDWMcLUukgMu0ou2d1UwvbwnD8BlyNvC+HK7J7Ya6CrwSglzhE8mxSAKhX4lvnUdGAC2ZM6pnWKjXrehVR5QvFvO58jPsD9DRFJtf1GyJo8iqIOin0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749924558; c=relaxed/simple; bh=sb1VR/hNYfHpyYfVBEJmn3DzQvD3Cx0gAohFnjQcuuI=; h=From:Date:Subject:MIME-Version:Message-Id:In-Reply-To:To:Cc: Content-Type:References; b=VwKoKvfuTK9AcZ/tDIhMx5EoRHamOyC7/JTkd/80TIl/RpH43xyMEJaInN7DB4cFGd58h4xViMnSKg6MJX9EEFyLpsCV/CfZxjWUITBR4ECX4iKefMlv3o1kIrBtcLYggPeBWiV0l/tsv28d/cPOor10Sd9NwMLmNTUGJ8Sbysc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com; spf=pass smtp.mailfrom=samsung.com; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b=L06zSlpO; arc=none smtp.client-ip=210.118.77.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=samsung.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="L06zSlpO" Received: from eucas1p2.samsung.com (unknown [182.198.249.207]) by mailout2.w1.samsung.com (KnoxPortal) with ESMTP id 20250614180908euoutp02d47cef721ceb3e3a4f4214132f3edb75~I_xsDqHvY0357903579euoutp02K for ; Sat, 14 Jun 2025 18:09:08 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout2.w1.samsung.com 20250614180908euoutp02d47cef721ceb3e3a4f4214132f3edb75~I_xsDqHvY0357903579euoutp02K DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1749924548; bh=es42sbD4TwJBn2FnGEDu63hM0VjueMf8OeKZlpT3Lck=; h=From:Date:Subject:In-Reply-To:To:Cc:References:From; b=L06zSlpOGQcGYRb1RD6sNAkqpSSAbcaKSl/jtPMgtBoadivsrxChgvIKR8VVMvreV vtKmDvh9KTXQTDIf0CFUP3+VYMUyQ/FAhC+d5Jkcno84YhsmaTvy9uvm80/GtsCMIh +xecwWytHkjiYtDxku4szoiaDlNxTXuGzwBFsHk0= Received: from eusmtip1.samsung.com (unknown [203.254.199.221]) by eucas1p1.samsung.com (KnoxPortal) with ESMTPA id 20250614180907eucas1p13d341c30e495fb36598b1d7c10ec7070~I_xrApfT50329603296eucas1p1O; Sat, 14 Jun 2025 18:09:07 +0000 (GMT) Received: from AMDC4942.eu.corp.samsungelectronics.net (unknown [106.210.136.40]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250614180906eusmtip10ef2265dbfca800be20fd8a02eca94e8~I_xp4kdF00306403064eusmtip1W; Sat, 14 Jun 2025 18:09:06 +0000 (GMT) From: Michal Wilczynski Date: Sat, 14 Jun 2025 20:06:07 +0200 Subject: [PATCH v4 1/8] power: sequencing: Add T-HEAD TH1520 GPU power sequencer driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Message-Id: <20250614-apr_14_for_sending-v4-1-8e3945c819cd@samsung.com> In-Reply-To: <20250614-apr_14_for_sending-v4-0-8e3945c819cd@samsung.com> To: Drew Fustini , Guo Ren , Fu Wei , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michal Wilczynski , Bartosz Golaszewski , Philipp Zabel , Frank Binns , Matt Coster , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Ulf Hansson , Marek Szyprowski Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, dri-devel@lists.freedesktop.org X-Mailer: b4 0.15-dev X-CMS-MailID: 20250614180907eucas1p13d341c30e495fb36598b1d7c10ec7070 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20250614180907eucas1p13d341c30e495fb36598b1d7c10ec7070 X-EPHeader: CA X-CMS-RootMailID: 20250614180907eucas1p13d341c30e495fb36598b1d7c10ec7070 References: <20250614-apr_14_for_sending-v4-0-8e3945c819cd@samsung.com> Introduce the pwrseq-thead-gpu driver, a power sequencer provider for the Imagination BXM-4-64 GPU on the T-HEAD TH1520 SoC. This driver is an auxiliary driver instantiated by the AON power domain driver. The TH1520 GPU requires a specific sequence to correctly initialize and power down its resources: - Enable GPU clocks (core and sys). - De-assert the GPU clock generator reset (clkgen_reset). - Introduce a short hardware-required delay. - De-assert the GPU core reset. The power-down sequence performs these steps in reverse. Implement this sequence via the pwrseq_power_on and pwrseq_power_off callbacks. Crucially, the driver's match function is called when a consumer (the Imagination GPU driver) requests the "gpu-power" target. During this match, the sequencer uses devm_clk_bulk_get() and devm_reset_control_get_exclusive() on the consumer's device to obtain handles to the GPU's "core" and "sys" clocks, and the GPU core reset. These, along with clkgen_reset obtained from parent aon node, allow it to perform the complete sequence. Reviewed-by: Ulf Hansson Signed-off-by: Michal Wilczynski --- MAINTAINERS | 1 + drivers/power/sequencing/Kconfig | 8 ++ drivers/power/sequencing/Makefile | 1 + drivers/power/sequencing/pwrseq-thead-gpu.c | 208 ++++++++++++++++++++++++= ++++ 4 files changed, 218 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 0183c028fa18c397d30ec82fd419894f1f50a448..3283ff592215249bcf702dbb4ab= 710477243477e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -21395,6 +21395,7 @@ F: drivers/mailbox/mailbox-th1520.c F: drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c F: drivers/pinctrl/pinctrl-th1520.c F: drivers/pmdomain/thead/ +F: drivers/power/sequencing/pwrseq-thead-gpu.c F: drivers/reset/reset-th1520.c F: include/dt-bindings/clock/thead,th1520-clk-ap.h F: include/dt-bindings/power/thead,th1520-power.h diff --git a/drivers/power/sequencing/Kconfig b/drivers/power/sequencing/Kc= onfig index ddcc42a984921c55667c46ac586d259625e1f1a7..7fa912c9af2479cdce909467c29= fe335788f0bd7 100644 --- a/drivers/power/sequencing/Kconfig +++ b/drivers/power/sequencing/Kconfig @@ -27,4 +27,12 @@ config POWER_SEQUENCING_QCOM_WCN this driver is needed for correct power control or else we'd risk not respecting the required delays between enabling Bluetooth and WLAN. =20 +config POWER_SEQUENCING_THEAD_GPU + tristate "T-HEAD TH1520 GPU power sequencing driver" + depends on ARCH_THEAD && AUXILIARY_BUS + help + Say Y here to enable the power sequencing driver for the TH1520 SoC + GPU. This driver handles the complex clock and reset sequence + required to power on the Imagination BXM GPU on this platform. + endif diff --git a/drivers/power/sequencing/Makefile b/drivers/power/sequencing/M= akefile index 2eec2df7912d11827f9ba914177dd2c882e44bce..647f81f4013ab825630f069d2e0= f6d22159f1f56 100644 --- a/drivers/power/sequencing/Makefile +++ b/drivers/power/sequencing/Makefile @@ -4,3 +4,4 @@ obj-$(CONFIG_POWER_SEQUENCING) +=3D pwrseq-core.o pwrseq-core-y :=3D core.o =20 obj-$(CONFIG_POWER_SEQUENCING_QCOM_WCN) +=3D pwrseq-qcom-wcn.o +obj-$(CONFIG_POWER_SEQUENCING_THEAD_GPU) +=3D pwrseq-thead-gpu.o diff --git a/drivers/power/sequencing/pwrseq-thead-gpu.c b/drivers/power/se= quencing/pwrseq-thead-gpu.c new file mode 100644 index 0000000000000000000000000000000000000000..bb77aba59a031471fe00c919fcc= 4a5f2564e0cb6 --- /dev/null +++ b/drivers/power/sequencing/pwrseq-thead-gpu.c @@ -0,0 +1,208 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * T-HEAD TH1520 GPU Power Sequencer Driver + * + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * Author: Michal Wilczynski + * + * This driver implements the power sequence for the Imagination BXM-4-64 + * GPU on the T-HEAD TH1520 SoC. The sequence requires coordinating resour= ces + * from both the sequencer's parent device node (clkgen_reset) and the GPU= 's + * device node (clocks and core reset). + * + * The `match` function is used to acquire the GPU's resources when the + * GPU driver requests the "gpu-power" sequence target. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +struct pwrseq_thead_gpu_ctx { + struct pwrseq_device *pwrseq; + struct reset_control *clkgen_reset; + struct device_node *aon_node; + + /* Consumer resources */ + struct clk_bulk_data *clks; + int num_clks; + struct reset_control *gpu_reset; +}; + +static int pwrseq_thead_gpu_power_on(struct pwrseq_device *pwrseq) +{ + struct pwrseq_thead_gpu_ctx *ctx =3D pwrseq_device_get_drvdata(pwrseq); + int ret; + + if (!ctx->clks || !ctx->gpu_reset) + return -ENODEV; + + ret =3D clk_bulk_prepare_enable(ctx->num_clks, ctx->clks); + if (ret) + return ret; + + ret =3D reset_control_deassert(ctx->clkgen_reset); + if (ret) + goto err_disable_clks; + + /* + * According to the hardware manual, a delay of at least 32 clock + * cycles is required between de-asserting the clkgen reset and + * de-asserting the GPU reset. Assuming a worst-case scenario with + * a very high GPU clock frequency, a delay of 1 microsecond is + * sufficient to ensure this requirement is met across all + * feasible GPU clock speeds. + */ + udelay(1); + + ret =3D reset_control_deassert(ctx->gpu_reset); + if (ret) + goto err_assert_clkgen; + + return 0; + +err_assert_clkgen: + reset_control_assert(ctx->clkgen_reset); +err_disable_clks: + clk_bulk_disable_unprepare(ctx->num_clks, ctx->clks); + return ret; +} + +static int pwrseq_thead_gpu_power_off(struct pwrseq_device *pwrseq) +{ + struct pwrseq_thead_gpu_ctx *ctx =3D pwrseq_device_get_drvdata(pwrseq); + + if (!ctx->clks || !ctx->gpu_reset) + return -ENODEV; + + reset_control_assert(ctx->gpu_reset); + reset_control_assert(ctx->clkgen_reset); + clk_bulk_disable_unprepare(ctx->num_clks, ctx->clks); + + return 0; +} + +static const struct pwrseq_unit_data pwrseq_thead_gpu_unit =3D { + .name =3D "gpu-power-sequence", + .enable =3D pwrseq_thead_gpu_power_on, + .disable =3D pwrseq_thead_gpu_power_off, +}; + +static const struct pwrseq_target_data pwrseq_thead_gpu_target =3D { + .name =3D "gpu-power", + .unit =3D &pwrseq_thead_gpu_unit, +}; + +static const struct pwrseq_target_data *pwrseq_thead_gpu_targets[] =3D { + &pwrseq_thead_gpu_target, + NULL +}; + +static int pwrseq_thead_gpu_match(struct pwrseq_device *pwrseq, + struct device *dev) +{ + struct pwrseq_thead_gpu_ctx *ctx =3D pwrseq_device_get_drvdata(pwrseq); + static const char *const clk_names[] =3D { "core", "sys" }; + struct of_phandle_args pwr_spec; + int i, ret; + + /* We only match the specific T-HEAD TH1520 GPU compatible */ + if (!of_device_is_compatible(dev->of_node, "thead,th1520-gpu")) + return 0; + + ret =3D of_parse_phandle_with_args(dev->of_node, "power-domains", + "#power-domain-cells", 0, &pwr_spec); + if (ret) + return 0; + + /* Additionally verify consumer device has AON as power-domain */ + if (pwr_spec.np !=3D ctx->aon_node || pwr_spec.args[0] !=3D TH1520_GPU_PD= ) { + of_node_put(pwr_spec.np); + return 0; + } + + of_node_put(pwr_spec.np); + + /* Prevent multiple consumers from attaching */ + if (ctx->gpu_reset || ctx->clks) + return -EBUSY; + + ctx->num_clks =3D ARRAY_SIZE(clk_names); + ctx->clks =3D devm_kcalloc(dev, ctx->num_clks, sizeof(*ctx->clks), + GFP_KERNEL); + if (!ctx->clks) + return -ENOMEM; + + for (i =3D 0; i < ctx->num_clks; i++) + ctx->clks[i].id =3D clk_names[i]; + + ret =3D devm_clk_bulk_get(dev, ctx->num_clks, ctx->clks); + if (ret) + return ret; + + ctx->gpu_reset =3D devm_reset_control_get_exclusive(dev, NULL); + if (IS_ERR(ctx->gpu_reset)) + return PTR_ERR(ctx->gpu_reset); + + return 1; +} + +static int pwrseq_thead_gpu_probe(struct auxiliary_device *adev, + const struct auxiliary_device_id *id) +{ + struct device *dev =3D &adev->dev; + struct device *parent_dev =3D dev->parent; + struct pwrseq_thead_gpu_ctx *ctx; + struct pwrseq_config config =3D {}; + + ctx =3D devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); + if (!ctx) + return -ENOMEM; + + ctx->aon_node =3D parent_dev->of_node; + + ctx->clkgen_reset =3D + devm_reset_control_get_exclusive(parent_dev, "gpu-clkgen"); + if (IS_ERR(ctx->clkgen_reset)) + return dev_err_probe( + dev, PTR_ERR(ctx->clkgen_reset), + "Failed to get GPU clkgen reset from parent\n"); + + config.parent =3D dev; + config.owner =3D THIS_MODULE; + config.drvdata =3D ctx; + config.match =3D pwrseq_thead_gpu_match; + config.targets =3D pwrseq_thead_gpu_targets; + + ctx->pwrseq =3D devm_pwrseq_device_register(dev, &config); + if (IS_ERR(ctx->pwrseq)) + return dev_err_probe(dev, PTR_ERR(ctx->pwrseq), + "Failed to register power sequencer\n"); + + return 0; +} + +static const struct auxiliary_device_id pwrseq_thead_gpu_id_table[] =3D { + { .name =3D "th1520_pm_domains.pwrseq-gpu" }, + {}, +}; +MODULE_DEVICE_TABLE(auxiliary, pwrseq_thead_gpu_id_table); + +static struct auxiliary_driver pwrseq_thead_gpu_driver =3D { + .driver =3D { + .name =3D "pwrseq-thead-gpu", + }, + .probe =3D pwrseq_thead_gpu_probe, + .id_table =3D pwrseq_thead_gpu_id_table, +}; +module_auxiliary_driver(pwrseq_thead_gpu_driver); + +MODULE_AUTHOR("Michal Wilczynski "); +MODULE_DESCRIPTION("T-HEAD TH1520 GPU power sequencer driver"); +MODULE_LICENSE("GPL"); --=20 2.34.1 From nobody Fri Oct 10 09:24:29 2025 Received: from mailout1.w1.samsung.com (mailout1.w1.samsung.com [210.118.77.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 480C82E7F1C for ; Sat, 14 Jun 2025 18:09:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.118.77.11 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749924559; cv=none; b=TSUTbXUZ+sWqtwoXNKYit1cBDwvwhlvLWpAevKvNfFrW8N6Cd4odV6SGTecKDcfMWUG+jnR0/PaIj6zVpu78ZhVAnIk6Nzdan3f/S9ngo1V3C9+glRF/tngALkeT2IOjB+YnXFRiA/LaVaMf6W7GGzxw1lA7sP2XUjW4yAqmWCI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749924559; c=relaxed/simple; bh=WRlTrsWOi/i85ebZasssiJ4ZtiiHBTtd9LezuNSNDfQ=; h=From:Date:Subject:MIME-Version:Message-Id:In-Reply-To:To:Cc: Content-Type:References; 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a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1749924550; bh=63b01qSumkcLmIEY0xdhZ+QcRoYutlUuGjICSf4+AW0=; h=From:Date:Subject:In-Reply-To:To:Cc:References:From; b=ClZPKjxM5OghbTcfgCIe5d+vucZN+EPvVbPxD+9Zb8WF8Mgq/SyZ56JEQNKWXESQg Bhj+omRSPKgWYxnHmqIv2bmTCOMxjrmVLUL7ue7sTJAuJSgSHHRyW/awI2V15Dci+n 3Q9smHBE/SKziJWQZhykb9AV3+c13r7QivZ2jnIc= Received: from eusmtip1.samsung.com (unknown [203.254.199.221]) by eucas1p1.samsung.com (KnoxPortal) with ESMTPA id 20250614180908eucas1p1f8e152bc86111d1fab4916e1737534e1~I_xr8DbVU2845928459eucas1p1D; Sat, 14 Jun 2025 18:09:08 +0000 (GMT) Received: from AMDC4942.eu.corp.samsungelectronics.net (unknown [106.210.136.40]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250614180907eusmtip1ff19c528fcdbe243e1c7de018a545147~I_xq78Vp31758317583eusmtip1o; Sat, 14 Jun 2025 18:09:07 +0000 (GMT) From: Michal Wilczynski Date: Sat, 14 Jun 2025 20:06:08 +0200 Subject: [PATCH v4 2/8] dt-bindings: firmware: thead,th1520: Add resets for GPU clkgen Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Message-Id: <20250614-apr_14_for_sending-v4-2-8e3945c819cd@samsung.com> In-Reply-To: <20250614-apr_14_for_sending-v4-0-8e3945c819cd@samsung.com> To: Drew Fustini , Guo Ren , Fu Wei , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michal Wilczynski , Bartosz Golaszewski , Philipp Zabel , Frank Binns , Matt Coster , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Ulf Hansson , Marek Szyprowski Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, dri-devel@lists.freedesktop.org X-Mailer: b4 0.15-dev X-CMS-MailID: 20250614180908eucas1p1f8e152bc86111d1fab4916e1737534e1 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20250614180908eucas1p1f8e152bc86111d1fab4916e1737534e1 X-EPHeader: CA X-CMS-RootMailID: 20250614180908eucas1p1f8e152bc86111d1fab4916e1737534e1 References: <20250614-apr_14_for_sending-v4-0-8e3945c819cd@samsung.com> Extend the TH1520 AON to describe the GPU clkgen reset line, required for proper GPU clock and reset sequencing. The T-HEAD TH1520 GPU requires coordinated management of two clocks (core and sys) and two resets (GPU core reset and GPU clkgen reset). Only the clkgen reset is exposed at the AON level, to support SoC specific initialization handled through a dedicated auxiliary power sequencing driver. The GPU core reset remains described in the GPU device node, as from the GPU driver's perspective, there is only a single reset line [1]. This follows upstream maintainers' recommendations [2] to abstract SoC specific details into the PM domain layer rather than exposing them to drivers directly. Link: https://lore.kernel.org/all/816db99d-7088-4c1a-af03-b9a825ac09dc@imgt= ec.com/ - [1] Link: https://lore.kernel.org/all/38d9650fc11a674c8b689d6bab937acf@kernel.o= rg/ - [2] Reviewed-by: Ulf Hansson Signed-off-by: Michal Wilczynski --- Documentation/devicetree/bindings/firmware/thead,th1520-aon.yaml | 7 +++++= ++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/firmware/thead,th1520-aon.ya= ml b/Documentation/devicetree/bindings/firmware/thead,th1520-aon.yaml index bbc183200400de7aadbb21fea21911f6f4227b09..3365124c7fd4736922717bd31ca= a13272f4a4ea6 100644 --- a/Documentation/devicetree/bindings/firmware/thead,th1520-aon.yaml +++ b/Documentation/devicetree/bindings/firmware/thead,th1520-aon.yaml @@ -32,6 +32,13 @@ properties: items: - const: aon =20 + resets: + maxItems: 1 + + reset-names: + items: + - const: gpu-clkgen + "#power-domain-cells": const: 1 =20 --=20 2.34.1 From nobody Fri Oct 10 09:24:29 2025 Received: from mailout1.w1.samsung.com (mailout1.w1.samsung.com [210.118.77.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 61CA82E7F34 for ; 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Sat, 14 Jun 2025 18:09:09 +0000 (GMT) Received: from AMDC4942.eu.corp.samsungelectronics.net (unknown [106.210.136.40]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250614180908eusmtip146d8003bdf8d8b7eef56198cf49309ea~I_xsAY2Rl2797327973eusmtip1c; Sat, 14 Jun 2025 18:09:08 +0000 (GMT) From: Michal Wilczynski Date: Sat, 14 Jun 2025 20:06:09 +0200 Subject: [PATCH v4 3/8] pmdomain: thead: Instantiate GPU power sequencer via auxiliary bus Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Message-Id: <20250614-apr_14_for_sending-v4-3-8e3945c819cd@samsung.com> In-Reply-To: <20250614-apr_14_for_sending-v4-0-8e3945c819cd@samsung.com> To: Drew Fustini , Guo Ren , Fu Wei , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michal Wilczynski , Bartosz Golaszewski , Philipp Zabel , Frank Binns , Matt Coster , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Ulf Hansson , Marek Szyprowski Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, dri-devel@lists.freedesktop.org X-Mailer: b4 0.15-dev X-CMS-MailID: 20250614180909eucas1p2a34e3242fb42f7fd25e4038c291276ff X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20250614180909eucas1p2a34e3242fb42f7fd25e4038c291276ff X-EPHeader: CA X-CMS-RootMailID: 20250614180909eucas1p2a34e3242fb42f7fd25e4038c291276ff References: <20250614-apr_14_for_sending-v4-0-8e3945c819cd@samsung.com> In order to support the complex power sequencing required by the TH1520 GPU, the AON power domain driver must be responsible for initiating the corresponding sequencer driver. This functionality is specific to platforms where the GPU power sequencing hardware is controlled by the AON block. Extend the AON power domain driver to check for the presence of the "gpu-clkgen" reset in its own device tree node. If the property is found, create and register a new auxiliary device. This device acts as a proxy that allows the dedicated `pwrseq-thead-gpu` auxiliary driver to bind and take control of the sequencing logic. Signed-off-by: Michal Wilczynski --- drivers/pmdomain/thead/Kconfig | 1 + drivers/pmdomain/thead/th1520-pm-domains.c | 53 ++++++++++++++++++++++++++= ++++ 2 files changed, 54 insertions(+) diff --git a/drivers/pmdomain/thead/Kconfig b/drivers/pmdomain/thead/Kconfig index 7d52f8374b074167d508a80fd807929c53faef12..208828e0fa0dc91256bf808b905= bea32bb84250d 100644 --- a/drivers/pmdomain/thead/Kconfig +++ b/drivers/pmdomain/thead/Kconfig @@ -4,6 +4,7 @@ config TH1520_PM_DOMAINS tristate "Support TH1520 Power Domains" depends on TH1520_AON_PROTOCOL select REGMAP_MMIO + select AUXILIARY_BUS help This driver enables power domain management for the T-HEAD TH-1520 SoC. On this SoC there are number of power domains, diff --git a/drivers/pmdomain/thead/th1520-pm-domains.c b/drivers/pmdomain/= thead/th1520-pm-domains.c index f702e20306f469aeb0ed15e54bd4f8309f28018c..9f2cd833e5f554d4a9154e276e5= fe5720fc4d50f 100644 --- a/drivers/pmdomain/thead/th1520-pm-domains.c +++ b/drivers/pmdomain/thead/th1520-pm-domains.c @@ -5,8 +5,10 @@ * Author: Michal Wilczynski */ =20 +#include #include #include +#include #include #include =20 @@ -128,6 +130,51 @@ static void th1520_pd_init_all_off(struct generic_pm_d= omain **domains, } } =20 +static void th1520_pd_pwrseq_unregister_adev(void *adev) +{ + auxiliary_device_delete(adev); + auxiliary_device_uninit(adev); +} + +static int th1520_pd_pwrseq_gpu_init(struct device *dev) +{ + struct auxiliary_device *adev; + int ret; + + /* + * Correctly check only for the property's existence in the DT node. + * We don't need to get/claim the reset here; that is the job of + * the auxiliary driver that we are about to spawn. + */ + if (of_property_match_string(dev->of_node, "reset-names", + "gpu-clkgen") < 0) + /* + * This is not an error. It simply means the optional sequencer + * is not described in the device tree. + */ + return 0; + + adev =3D devm_kzalloc(dev, sizeof(*adev), GFP_KERNEL); + if (!adev) + return -ENOMEM; + + adev->name =3D "pwrseq-gpu"; + adev->dev.parent =3D dev; + + ret =3D auxiliary_device_init(adev); + if (ret) + return ret; + + ret =3D auxiliary_device_add(adev); + if (ret) { + auxiliary_device_uninit(adev); + return ret; + } + + return devm_add_action_or_reset(dev, th1520_pd_pwrseq_unregister_adev, + adev); +} + static int th1520_pd_probe(struct platform_device *pdev) { struct generic_pm_domain **domains; @@ -186,8 +233,14 @@ static int th1520_pd_probe(struct platform_device *pde= v) if (ret) goto err_clean_genpd; =20 + ret =3D th1520_pd_pwrseq_gpu_init(dev); + if (ret) + goto err_clean_provider; + return 0; =20 +err_clean_provider: + of_genpd_del_provider(dev->of_node); err_clean_genpd: for (i--; i >=3D 0; i--) pm_genpd_remove(domains[i]); --=20 2.34.1 From nobody Fri Oct 10 09:24:29 2025 Received: from mailout1.w1.samsung.com (mailout1.w1.samsung.com [210.118.77.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 68E262E88A5 for ; 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Sat, 14 Jun 2025 18:09:11 +0000 (GMT) Received: from AMDC4942.eu.corp.samsungelectronics.net (unknown [106.210.136.40]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250614180909eusmtip19b262cb80a01cdeca9bf3f9a45e0d37a~I_xtF6JoX1758317583eusmtip1p; Sat, 14 Jun 2025 18:09:09 +0000 (GMT) From: Michal Wilczynski Date: Sat, 14 Jun 2025 20:06:10 +0200 Subject: [PATCH v4 4/8] drm/imagination: Use pwrseq for TH1520 GPU power management Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Message-Id: <20250614-apr_14_for_sending-v4-4-8e3945c819cd@samsung.com> In-Reply-To: <20250614-apr_14_for_sending-v4-0-8e3945c819cd@samsung.com> To: Drew Fustini , Guo Ren , Fu Wei , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michal Wilczynski , Bartosz Golaszewski , Philipp Zabel , Frank Binns , Matt Coster , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Ulf Hansson , Marek Szyprowski Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, dri-devel@lists.freedesktop.org X-Mailer: b4 0.15-dev X-CMS-MailID: 20250614180911eucas1p16c9fb4a8160253c253f623bec2529f70 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20250614180911eucas1p16c9fb4a8160253c253f623bec2529f70 X-EPHeader: CA X-CMS-RootMailID: 20250614180911eucas1p16c9fb4a8160253c253f623bec2529f70 References: <20250614-apr_14_for_sending-v4-0-8e3945c819cd@samsung.com> Update the Imagination PVR DRM driver to leverage the pwrseq framework for managing the power sequence of the GPU on the T-HEAD TH1520 SoC. To cleanly handle the TH1520's specific power requirements in the generic driver, this patch implements the "driver match data" pattern. A has_pwrseq flag in a new pvr_soc_data struct is now associated with thead,th1520-gpu compatible string in the of_device_id table. At probe time, the driver checks this flag. If true, it calls devm_pwrseq_get("gpu-power"), requiring a valid sequencer and deferring probe on failure. In this mode, all power and reset control is delegated to the pwrseq provider. If the flag is false, the driver skips this logic and falls back to its standard manual power management. Clock handles are still acquired directly by this driver in both cases for other purposes like devfreq. The runtime PM callbacks, pvr_power_device_resume() and pvr_power_device_suspend(), are modified to call pwrseq_power_on() and pwrseq_power_off() respectively when the sequencer is present. A helper function, pvr_power_off_sequence_manual(), is introduced to encapsulate the manual power-down logic. Reviewed-by: Ulf Hansson Signed-off-by: Michal Wilczynski --- drivers/gpu/drm/imagination/Kconfig | 1 + drivers/gpu/drm/imagination/pvr_device.c | 31 ++++++++++-- drivers/gpu/drm/imagination/pvr_device.h | 17 +++++++ drivers/gpu/drm/imagination/pvr_drv.c | 6 +++ drivers/gpu/drm/imagination/pvr_power.c | 82 +++++++++++++++++++++-------= ---- 5 files changed, 104 insertions(+), 33 deletions(-) diff --git a/drivers/gpu/drm/imagination/Kconfig b/drivers/gpu/drm/imaginat= ion/Kconfig index 3bfa2ac212dccb73c53bdc2bc259bcba636e7cfc..5f9fff43d6baadc42ebf48d9172= 9bfbf27e06caa 100644 --- a/drivers/gpu/drm/imagination/Kconfig +++ b/drivers/gpu/drm/imagination/Kconfig @@ -11,6 +11,7 @@ config DRM_POWERVR select DRM_SCHED select DRM_GPUVM select FW_LOADER + select POWER_SEQUENCING help Choose this option if you have a system that has an Imagination Technologies PowerVR (Series 6 or later) or IMG GPU. diff --git a/drivers/gpu/drm/imagination/pvr_device.c b/drivers/gpu/drm/ima= gination/pvr_device.c index 8b9ba4983c4cb5bc40342fcafc4259078bc70547..2f71c9501b157e6e14a6f3033e0= 2db40ce5c74c7 100644 --- a/drivers/gpu/drm/imagination/pvr_device.c +++ b/drivers/gpu/drm/imagination/pvr_device.c @@ -23,8 +23,10 @@ #include #include #include +#include #include #include +#include #include #include #include @@ -618,6 +620,9 @@ pvr_device_init(struct pvr_device *pvr_dev) struct device *dev =3D drm_dev->dev; int err; =20 + /* Get the platform-specific data based on the compatible string. */ + pvr_dev->soc_data =3D of_device_get_match_data(dev); + /* * Setup device parameters. We do this first in case other steps * depend on them. @@ -631,10 +636,28 @@ pvr_device_init(struct pvr_device *pvr_dev) if (err) return err; =20 - /* Get the reset line for the GPU */ - err =3D pvr_device_reset_init(pvr_dev); - if (err) - return err; + /* + * For platforms that require it, get the power sequencer. + * For all others, perform manual reset initialization. + */ + if (pvr_dev->soc_data && pvr_dev->soc_data->has_pwrseq) { + pvr_dev->pwrseq =3D devm_pwrseq_get(dev, "gpu-power"); + if (IS_ERR(pvr_dev->pwrseq)) { + /* + * This platform requires a sequencer. If we can't get + * it, we must return the error (including -EPROBE_DEFER + * to wait for the provider to appear) + */ + return dev_err_probe( + dev, PTR_ERR(pvr_dev->pwrseq), + "Failed to get required power sequencer\n"); + } + } else { + /* This platform does not use a sequencer, init reset manually. */ + err =3D pvr_device_reset_init(pvr_dev); + if (err) + return err; + } =20 /* Explicitly power the GPU so we can access control registers before the= FW is booted. */ err =3D pm_runtime_resume_and_get(dev); diff --git a/drivers/gpu/drm/imagination/pvr_device.h b/drivers/gpu/drm/ima= gination/pvr_device.h index 7cb01c38d2a9c3fc71effe789d4dfe54eddd93ee..5182f06ca7e2071777bdaa9d077= 57df5ef869fe3 100644 --- a/drivers/gpu/drm/imagination/pvr_device.h +++ b/drivers/gpu/drm/imagination/pvr_device.h @@ -37,6 +37,9 @@ struct clk; /* Forward declaration from . */ struct firmware; =20 +/* Forward declaration from #include #include +#include #include #include #include @@ -234,6 +235,19 @@ pvr_watchdog_init(struct pvr_device *pvr_dev) return 0; } =20 +static int pvr_power_off_sequence_manual(struct pvr_device *pvr_dev) +{ + int err; + + err =3D reset_control_assert(pvr_dev->reset); + + clk_disable_unprepare(pvr_dev->mem_clk); + clk_disable_unprepare(pvr_dev->sys_clk); + clk_disable_unprepare(pvr_dev->core_clk); + + return err; +} + int pvr_power_device_suspend(struct device *dev) { @@ -252,11 +266,10 @@ pvr_power_device_suspend(struct device *dev) goto err_drm_dev_exit; } =20 - clk_disable_unprepare(pvr_dev->mem_clk); - clk_disable_unprepare(pvr_dev->sys_clk); - clk_disable_unprepare(pvr_dev->core_clk); - - err =3D reset_control_assert(pvr_dev->reset); + if (pvr_dev->pwrseq) + err =3D pwrseq_power_off(pvr_dev->pwrseq); + else + err =3D pvr_power_off_sequence_manual(pvr_dev); =20 err_drm_dev_exit: drm_dev_exit(idx); @@ -276,44 +289,55 @@ pvr_power_device_resume(struct device *dev) if (!drm_dev_enter(drm_dev, &idx)) return -EIO; =20 - err =3D clk_prepare_enable(pvr_dev->core_clk); - if (err) - goto err_drm_dev_exit; + if (pvr_dev->pwrseq) { + err =3D pwrseq_power_on(pvr_dev->pwrseq); + if (err) + goto err_drm_dev_exit; + } else { + err =3D clk_prepare_enable(pvr_dev->core_clk); + if (err) + goto err_drm_dev_exit; =20 - err =3D clk_prepare_enable(pvr_dev->sys_clk); - if (err) - goto err_core_clk_disable; + err =3D clk_prepare_enable(pvr_dev->sys_clk); + if (err) + goto err_core_clk_disable; =20 - err =3D clk_prepare_enable(pvr_dev->mem_clk); - if (err) - goto err_sys_clk_disable; + err =3D clk_prepare_enable(pvr_dev->mem_clk); + if (err) + goto err_sys_clk_disable; =20 - /* - * According to the hardware manual, a delay of at least 32 clock - * cycles is required between de-asserting the clkgen reset and - * de-asserting the GPU reset. Assuming a worst-case scenario with - * a very high GPU clock frequency, a delay of 1 microsecond is - * sufficient to ensure this requirement is met across all - * feasible GPU clock speeds. - */ - udelay(1); + /* + * According to the hardware manual, a delay of at least 32 clock + * cycles is required between de-asserting the clkgen reset and + * de-asserting the GPU reset. Assuming a worst-case scenario with + * a very high GPU clock frequency, a delay of 1 microsecond is + * sufficient to ensure this requirement is met across all + * feasible GPU clock speeds. + */ + udelay(1); =20 - err =3D reset_control_deassert(pvr_dev->reset); - if (err) - goto err_mem_clk_disable; + err =3D reset_control_deassert(pvr_dev->reset); + if (err) + goto err_mem_clk_disable; + } =20 if (pvr_dev->fw_dev.booted) { err =3D pvr_power_fw_enable(pvr_dev); if (err) - goto err_reset_assert; + goto err_power_off; } =20 drm_dev_exit(idx); =20 return 0; =20 -err_reset_assert: - reset_control_assert(pvr_dev->reset); +err_power_off: + if (pvr_dev->pwrseq) + pwrseq_power_off(pvr_dev->pwrseq); + else + pvr_power_off_sequence_manual(pvr_dev); + + goto err_drm_dev_exit; =20 err_mem_clk_disable: clk_disable_unprepare(pvr_dev->mem_clk); --=20 2.34.1 From nobody Fri Oct 10 09:24:29 2025 Received: from mailout1.w1.samsung.com (mailout1.w1.samsung.com [210.118.77.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C6F2C2E88BD for ; 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Sat, 14 Jun 2025 18:09:12 +0000 (GMT) Received: from AMDC4942.eu.corp.samsungelectronics.net (unknown [106.210.136.40]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250614180911eusmtip148cda267a8f953c22a047410b87efabf~I_xuqY_Yz2797327973eusmtip1d; Sat, 14 Jun 2025 18:09:11 +0000 (GMT) From: Michal Wilczynski Date: Sat, 14 Jun 2025 20:06:11 +0200 Subject: [PATCH v4 5/8] dt-bindings: gpu: img,powervr-rogue: Add TH1520 GPU compatible Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Message-Id: <20250614-apr_14_for_sending-v4-5-8e3945c819cd@samsung.com> In-Reply-To: <20250614-apr_14_for_sending-v4-0-8e3945c819cd@samsung.com> To: Drew Fustini , Guo Ren , Fu Wei , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michal Wilczynski , Bartosz Golaszewski , Philipp Zabel , Frank Binns , Matt Coster , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Ulf Hansson , Marek Szyprowski Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, dri-devel@lists.freedesktop.org, Krzysztof Kozlowski X-Mailer: b4 0.15-dev X-CMS-MailID: 20250614180912eucas1p283681bf6a16249417e5e6d8eb25b969c X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20250614180912eucas1p283681bf6a16249417e5e6d8eb25b969c X-EPHeader: CA X-CMS-RootMailID: 20250614180912eucas1p283681bf6a16249417e5e6d8eb25b969c References: <20250614-apr_14_for_sending-v4-0-8e3945c819cd@samsung.com> Update the img,powervr-rogue.yaml to include the T-HEAD TH1520 SoC's specific GPU compatible string. The thead,th1520-gpu compatible, along with its full chain img,img-bxm-4-64, and img,img-rogue, is added to the list of recognized GPU types. The power-domains property requirement for img,img-bxm-4-64 is also ensured by adding it to the relevant allOf condition. Acked-by: Krzysztof Kozlowski Reviewed-by: Ulf Hansson Signed-off-by: Michal Wilczynski --- Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml b= /Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml index 4450e2e73b3ccf74d29f0e31e2e6687d7cbe5d65..9b241a0c1f5941dc58a1e23970f= 6d3773d427c22 100644 --- a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml +++ b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml @@ -21,6 +21,11 @@ properties: # work with newer dts. - const: img,img-axe - const: img,img-rogue + - items: + - enum: + - thead,th1520-gpu + - const: img,img-bxm-4-64 + - const: img,img-rogue - items: - enum: - ti,j721s2-gpu @@ -93,7 +98,9 @@ allOf: properties: compatible: contains: - const: img,img-axe-1-16m + enum: + - img,img-axe-1-16m + - img,img-bxm-4-64 then: properties: power-domains: --=20 2.34.1 From nobody Fri Oct 10 09:24:29 2025 Received: from mailout1.w1.samsung.com (mailout1.w1.samsung.com [210.118.77.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 991062E88B1 for ; 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Sat, 14 Jun 2025 18:09:13 +0000 (GMT) Received: from AMDC4942.eu.corp.samsungelectronics.net (unknown [106.210.136.40]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250614180912eusmtip1e08743a9bcee9b7280e90351569ae07e~I_xvwqq-J1758317583eusmtip1q; Sat, 14 Jun 2025 18:09:12 +0000 (GMT) From: Michal Wilczynski Date: Sat, 14 Jun 2025 20:06:12 +0200 Subject: [PATCH v4 6/8] riscv: dts: thead: th1520: Add GPU clkgen reset to AON node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Message-Id: <20250614-apr_14_for_sending-v4-6-8e3945c819cd@samsung.com> In-Reply-To: <20250614-apr_14_for_sending-v4-0-8e3945c819cd@samsung.com> To: Drew Fustini , Guo Ren , Fu Wei , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michal Wilczynski , Bartosz Golaszewski , Philipp Zabel , Frank Binns , Matt Coster , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Ulf Hansson , Marek Szyprowski Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, dri-devel@lists.freedesktop.org X-Mailer: b4 0.15-dev X-CMS-MailID: 20250614180913eucas1p2554c9e8d5024c534565d3c1de58f2e61 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20250614180913eucas1p2554c9e8d5024c534565d3c1de58f2e61 X-EPHeader: CA X-CMS-RootMailID: 20250614180913eucas1p2554c9e8d5024c534565d3c1de58f2e61 References: <20250614-apr_14_for_sending-v4-0-8e3945c819cd@samsung.com> Add the "gpu-clkgen" reset property to the AON device tree node. This allows the AON power domain driver to detect the capability to power sequence the GPU and spawn the necessary pwrseq-thead-gpu auxiliary driver for managing the GPU's complex power sequence. This commit also adds the prerequisite dt-bindings/reset/thead,th1520-reset.h include to make the TH1520_RESET_ID_GPU_CLKGEN available. This include was previously dropped during a conflict resolution [1]. Link: https://lore.kernel.org/all/aAvfn2mq0Ksi8DF2@x1/ [1] Reviewed-by: Ulf Hansson Signed-off-by: Michal Wilczynski --- arch/riscv/boot/dts/thead/th1520.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/th= ead/th1520.dtsi index 1db0054c4e093400e9dbebcee5fcfa5b5cae6e32..f3f5db0201ab8c0306d4d63072a= 1573431e51893 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include =20 / { compatible =3D "thead,th1520"; @@ -234,6 +235,8 @@ aon: aon { compatible =3D "thead,th1520-aon"; mboxes =3D <&mbox_910t 1>; mbox-names =3D "aon"; + resets =3D <&rst TH1520_RESET_ID_GPU_CLKGEN>; + reset-names =3D "gpu-clkgen"; #power-domain-cells =3D <1>; }; =20 --=20 2.34.1 From nobody Fri Oct 10 09:24:29 2025 Received: from mailout2.w1.samsung.com (mailout2.w1.samsung.com [210.118.77.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6F1E62E88A6 for ; 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Sat, 14 Jun 2025 18:09:14 +0000 (GMT) Received: from AMDC4942.eu.corp.samsungelectronics.net (unknown [106.210.136.40]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250614180913eusmtip19fd270f133cbb3b71892c8e99a6d357a~I_xwzuraA0306403064eusmtip1X; Sat, 14 Jun 2025 18:09:13 +0000 (GMT) From: Michal Wilczynski Date: Sat, 14 Jun 2025 20:06:13 +0200 Subject: [PATCH v4 7/8] riscv: dts: thead: th1520: Add IMG BXM-4-64 GPU node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Message-Id: <20250614-apr_14_for_sending-v4-7-8e3945c819cd@samsung.com> In-Reply-To: <20250614-apr_14_for_sending-v4-0-8e3945c819cd@samsung.com> To: Drew Fustini , Guo Ren , Fu Wei , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michal Wilczynski , Bartosz Golaszewski , Philipp Zabel , Frank Binns , Matt Coster , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Ulf Hansson , Marek Szyprowski Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, dri-devel@lists.freedesktop.org X-Mailer: b4 0.15-dev X-CMS-MailID: 20250614180914eucas1p202074745dba308cf1e18d1b75a2f3cea X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20250614180914eucas1p202074745dba308cf1e18d1b75a2f3cea X-EPHeader: CA X-CMS-RootMailID: 20250614180914eucas1p202074745dba308cf1e18d1b75a2f3cea References: <20250614-apr_14_for_sending-v4-0-8e3945c819cd@samsung.com> Add a device tree node for the IMG BXM-4-64 GPU present in the T-HEAD TH1520 SoC used by the Lichee Pi 4A board. This node enables support for the GPU using the drm/imagination driver. By adding this node, the kernel can recognize and initialize the GPU, providing graphics acceleration capabilities on the Lichee Pi 4A and other boards based on the TH1520 SoC. Add fixed clock gpu_mem_clk, as the MEM clock on the T-HEAD SoC can't be controlled programatically. Reviewed-by: Ulf Hansson Signed-off-by: Michal Wilczynski --- arch/riscv/boot/dts/thead/th1520.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/th= ead/th1520.dtsi index f3f5db0201ab8c0306d4d63072a1573431e51893..c8447eef36c3a6e92d768658b6b= 19dfeb59a47c4 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -225,6 +225,13 @@ aonsys_clk: clock-73728000 { #clock-cells =3D <0>; }; =20 + gpu_mem_clk: mem-clk { + compatible =3D "fixed-clock"; + clock-frequency =3D <0>; + clock-output-names =3D "gpu_mem_clk"; + #clock-cells =3D <0>; + }; + stmmac_axi_config: stmmac-axi-config { snps,wr_osr_lmt =3D <15>; snps,rd_osr_lmt =3D <15>; @@ -500,6 +507,21 @@ clk: clock-controller@ffef010000 { #clock-cells =3D <1>; }; =20 + gpu: gpu@ffef400000 { + compatible =3D "thead,th1520-gpu", "img,img-bxm-4-64", + "img,img-rogue"; + reg =3D <0xff 0xef400000 0x0 0x100000>; + interrupt-parent =3D <&plic>; + interrupts =3D <102 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&clk_vo CLK_GPU_CORE>, + <&gpu_mem_clk>, + <&clk_vo CLK_GPU_CFG_ACLK>; + clock-names =3D "core", "mem", "sys"; + power-domains =3D <&aon TH1520_GPU_PD>; + power-domain-names =3D "a"; + resets =3D <&rst TH1520_RESET_ID_GPU>; + }; + rst: reset-controller@ffef528000 { compatible =3D "thead,th1520-reset"; reg =3D <0xff 0xef528000 0x0 0x4f>; --=20 2.34.1 From nobody Fri Oct 10 09:24:29 2025 Received: from mailout2.w1.samsung.com (mailout2.w1.samsung.com [210.118.77.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A18E82E88BA for ; Sat, 14 Jun 2025 18:09:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.118.77.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749924563; cv=none; b=XOTy1mqW7s3U5Y2NQMTh5fFDDphR2DYduhN/BCvwVet98M+LZ8E8Ch5c9rxinYLJ4CR0GYUIpS6LH5AJSCMcp/Ds1ItdkM5l6evCOZ7vKUCBqxerPpqvmBZ2ZQobx8pvjBswOmXzlsJlE6ygMGMFXZSVpWWSELK0jcaRXG8BkL0= ARC-Message-Signature: i=1; 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Sat, 14 Jun 2025 18:09:14 +0000 (GMT) From: Michal Wilczynski Date: Sat, 14 Jun 2025 20:06:14 +0200 Subject: [PATCH v4 8/8] drm/imagination: Enable PowerVR driver for RISC-V Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Message-Id: <20250614-apr_14_for_sending-v4-8-8e3945c819cd@samsung.com> In-Reply-To: <20250614-apr_14_for_sending-v4-0-8e3945c819cd@samsung.com> To: Drew Fustini , Guo Ren , Fu Wei , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michal Wilczynski , Bartosz Golaszewski , Philipp Zabel , Frank Binns , Matt Coster , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Ulf Hansson , Marek Szyprowski Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, dri-devel@lists.freedesktop.org X-Mailer: b4 0.15-dev X-CMS-MailID: 20250614180916eucas1p1ee5f075be14d88aa828ec4e55c26bae9 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20250614180916eucas1p1ee5f075be14d88aa828ec4e55c26bae9 X-EPHeader: CA X-CMS-RootMailID: 20250614180916eucas1p1ee5f075be14d88aa828ec4e55c26bae9 References: <20250614-apr_14_for_sending-v4-0-8e3945c819cd@samsung.com> Several RISC-V boards feature Imagination GPUs that are compatible with the PowerVR driver. An example is the IMG BXM-4-64 GPU on the Lichee Pi 4A board. This commit adjusts the driver's Kconfig dependencies to allow the PowerVR driver to be compiled on the RISC-V architecture. By enabling compilation on RISC-V, we expand support for these GPUs, providing graphics acceleration capabilities and enhancing hardware compatibility on RISC-V platforms. Reviewed-by: Ulf Hansson Signed-off-by: Michal Wilczynski --- drivers/gpu/drm/imagination/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/imagination/Kconfig b/drivers/gpu/drm/imaginat= ion/Kconfig index 5f9fff43d6baadc42ebf48d91729bfbf27e06caa..d1e5a18e8e84dc57452cd4bf0fe= 89dfb90a7bb29 100644 --- a/drivers/gpu/drm/imagination/Kconfig +++ b/drivers/gpu/drm/imagination/Kconfig @@ -3,7 +3,7 @@ =20 config DRM_POWERVR tristate "Imagination Technologies PowerVR (Series 6 and later) & IMG Gra= phics" - depends on ARM64 + depends on (ARM64 || RISCV) depends on DRM depends on PM select DRM_EXEC --=20 2.34.1