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([10.239.96.51]) by orviesa009.jf.intel.com with ESMTP; 13 Jun 2025 09:19:24 -0700 From: Yi Sun To: dave.jiang@intel.com, vinicius.gomes@intel.com, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org Cc: yi.sun@intel.com, gordon.jin@intel.com, fenghuay@nvidia.com, anil.s.keshavamurthy@intel.com, philip.lantz@intel.com Subject: [PATCH 2/2] dmaengine: idxd: Add Max SGL Size Support for DSA3.0 Date: Sat, 14 Jun 2025 00:18:34 +0800 Message-ID: <20250613161834.2912353-3-yi.sun@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250613161834.2912353-1-yi.sun@intel.com> References: <20250613161834.2912353-1-yi.sun@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Certain DSA 3.0 opcodes, such as Gather copy and Gather reduce requires max SGL configured for workqueues prior to support these opcodes. Configure the maximum scatter-gather list (SGL) size for workqueues during setup on the supported HW. Application can then properly handle the SGL size without explicitly setting it. Signed-off-by: Yi Sun Co-developed-by: Anil S Keshavamurthy Signed-off-by: Anil S Keshavamurthy diff --git a/drivers/dma/idxd/device.c b/drivers/dma/idxd/device.c index 5cf419fe6b46..1c10b030bea7 100644 Reviewed-by: Dave Jiang --- a/drivers/dma/idxd/device.c +++ b/drivers/dma/idxd/device.c @@ -375,6 +375,7 @@ static void idxd_wq_disable_cleanup(struct idxd_wq *wq) memset(wq->name, 0, WQ_NAME_SIZE); wq->max_xfer_bytes =3D WQ_DEFAULT_MAX_XFER; idxd_wq_set_max_batch_size(idxd->data->type, wq, WQ_DEFAULT_MAX_BATCH); + idxd_wq_set_init_max_sgl_size(idxd, wq); if (wq->opcap_bmap) bitmap_copy(wq->opcap_bmap, idxd->opcap_bmap, IDXD_MAX_OPCAP_BITS); } @@ -974,6 +975,8 @@ static int idxd_wq_config_write(struct idxd_wq *wq) /* bytes 12-15 */ wq->wqcfg->max_xfer_shift =3D ilog2(wq->max_xfer_bytes); idxd_wqcfg_set_max_batch_shift(idxd->data->type, wq->wqcfg, ilog2(wq->max= _batch_size)); + if (idxd_sgl_supported(idxd)) + wq->wqcfg->max_sgl_shift =3D ilog2(wq->max_sgl_size); =20 /* bytes 32-63 */ if (idxd->hw.wq_cap.op_config && wq->opcap_bmap) { @@ -1152,6 +1155,8 @@ static int idxd_wq_load_config(struct idxd_wq *wq) =20 wq->max_xfer_bytes =3D 1ULL << wq->wqcfg->max_xfer_shift; idxd_wq_set_max_batch_size(idxd->data->type, wq, 1U << wq->wqcfg->max_bat= ch_shift); + if (idxd_sgl_supported(idxd)) + wq->max_sgl_size =3D 1U << wq->wqcfg->max_sgl_shift; =20 for (i =3D 0; i < WQCFG_STRIDES(idxd); i++) { wqcfg_offset =3D WQCFG_OFFSET(idxd, wq->id, i); diff --git a/drivers/dma/idxd/idxd.h b/drivers/dma/idxd/idxd.h index cc0a3fe1c957..fe5af50b58a4 100644 --- a/drivers/dma/idxd/idxd.h +++ b/drivers/dma/idxd/idxd.h @@ -227,6 +227,7 @@ struct idxd_wq { char name[WQ_NAME_SIZE + 1]; u64 max_xfer_bytes; u32 max_batch_size; + u32 max_sgl_size; =20 /* Lock to protect upasid_xa access. */ struct mutex uc_lock; @@ -348,6 +349,7 @@ struct idxd_device { =20 u64 max_xfer_bytes; u32 max_batch_size; + u32 max_sgl_size; int max_groups; int max_engines; int max_rdbufs; @@ -692,6 +694,20 @@ static inline void idxd_wq_set_max_batch_size(int idxd= _type, struct idxd_wq *wq, wq->max_batch_size =3D max_batch_size; } =20 +static bool idxd_sgl_supported(struct idxd_device *idxd) +{ + return idxd->hw.dsacap0.sgl_formats && + idxd->data->type =3D=3D IDXD_TYPE_DSA && + idxd->hw.version >=3D DEVICE_VERSION_3; +} + +static inline void idxd_wq_set_init_max_sgl_size(struct idxd_device *idxd, + struct idxd_wq *wq) +{ + if (idxd_sgl_supported(idxd)) + wq->max_sgl_size =3D 1U << idxd->hw.dsacap0.max_sgl_shift; +} + static inline void idxd_wqcfg_set_max_batch_shift(int idxd_type, union wqc= fg *wqcfg, u32 max_batch_shift) { diff --git a/drivers/dma/idxd/init.c b/drivers/dma/idxd/init.c index cc8203320d40..f37a7d7b537a 100644 --- a/drivers/dma/idxd/init.c +++ b/drivers/dma/idxd/init.c @@ -217,6 +217,7 @@ static int idxd_setup_wqs(struct idxd_device *idxd) init_completion(&wq->wq_resurrect); wq->max_xfer_bytes =3D WQ_DEFAULT_MAX_XFER; idxd_wq_set_max_batch_size(idxd->data->type, wq, WQ_DEFAULT_MAX_BATCH); + idxd_wq_set_init_max_sgl_size(idxd, wq); wq->enqcmds_retries =3D IDXD_ENQCMDS_RETRIES; wq->wqcfg =3D kzalloc_node(idxd->wqcfg_size, GFP_KERNEL, dev_to_node(dev= )); if (!wq->wqcfg) { @@ -585,6 +586,10 @@ static void idxd_read_caps(struct idxd_device *idxd) idxd->hw.dsacap0.bits =3D ioread64(idxd->reg_base + IDXD_DSACAP0_OFFSET); idxd->hw.dsacap1.bits =3D ioread64(idxd->reg_base + IDXD_DSACAP1_OFFSET); idxd->hw.dsacap2.bits =3D ioread64(idxd->reg_base + IDXD_DSACAP2_OFFSET); + if (idxd_sgl_supported(idxd)) { + idxd->max_sgl_size =3D 1U << idxd->hw.dsacap0.max_sgl_shift; + dev_dbg(dev, "max sgl size: %u\n", idxd->max_sgl_size); + } =20 /* read iaa cap */ if (idxd->data->type =3D=3D IDXD_TYPE_IAX && idxd->hw.version >=3D DEVICE= _VERSION_2) diff --git a/drivers/dma/idxd/registers.h b/drivers/dma/idxd/registers.h index 45485ecd7bb6..0401cfc95f27 100644 --- a/drivers/dma/idxd/registers.h +++ b/drivers/dma/idxd/registers.h @@ -385,7 +385,8 @@ union wqcfg { /* bytes 12-15 */ u32 max_xfer_shift:5; u32 max_batch_shift:4; - u32 rsvd4:23; + u32 max_sgl_shift:4; + u32 rsvd4:19; =20 /* bytes 16-19 */ u16 occupancy_inth; @@ -585,6 +586,15 @@ union evl_status_reg { =20 #define IDXD_DSACAP0_OFFSET 0x180 union dsacap0_reg { + struct { + u64 max_sgl_shift:4; + u64 max_gr_block_shift:4; + u64 ops_inter_domain:7; + u64 rsvd1:17; + u64 sgl_formats:16; + u64 max_sg_process:8; + u64 rsvd2:8; + }; u64 bits; }; =20 --=20 2.43.0