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([10.239.96.51]) by orviesa009.jf.intel.com with ESMTP; 13 Jun 2025 09:19:20 -0700 From: Yi Sun To: dave.jiang@intel.com, vinicius.gomes@intel.com, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org Cc: yi.sun@intel.com, gordon.jin@intel.com, fenghuay@nvidia.com, anil.s.keshavamurthy@intel.com, philip.lantz@intel.com Subject: [PATCH 1/2] dmaengine: idxd: Expose DSA3.0 capabilities through sysfs Date: Sat, 14 Jun 2025 00:18:33 +0800 Message-ID: <20250613161834.2912353-2-yi.sun@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250613161834.2912353-1-yi.sun@intel.com> References: <20250613161834.2912353-1-yi.sun@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Introduce sysfs interfaces for 3 new Data Streaming Accelerator (DSA) capability registers (dsacap0-2) to enable userspace awareness of hardware features in DSA version 3 and later devices. Userspace components (e.g. configure libraries, workload Apps) require this information to: 1. Select optimal data transfer strategies based on SGL capabilities 2. Enable hardware-specific optimizations for floating-point operations 3. Configure memory operations with proper numerical handling 4. Verify compute operation compatibility before submitting jobs The output consists of values from the three dsacap registers, concatenated in order and separated by commas. Example: cat /sys/bus/dsa/devices/dsa0/dsacap 0014000e000007aa,00fa01ff01ff03ff,000000000000f18d Signed-off-by: Yi Sun Co-developed-by: Anil S Keshavamurthy Signed-off-by: Anil S Keshavamurthy diff --git a/Documentation/ABI/stable/sysfs-driver-dma-idxd b/Documentation= /ABI/stable/sysfs-driver-dma-idxd index 4a355e6747ae..f9568ea52b2f 100644 Reviewed-by: Dave Jiang --- a/Documentation/ABI/stable/sysfs-driver-dma-idxd +++ b/Documentation/ABI/stable/sysfs-driver-dma-idxd @@ -136,6 +136,21 @@ Description: The last executed device administrative c= ommand's status/error. Also last configuration error overloaded. Writing to it will clear the status. =20 +What: /sys/bus/dsa/devices/dsa/dsacap +Date: June 1, 2025 +KernelVersion: 6.17.0 +Contact: dmaengine@vger.kernel.org +Description: The DSA3 specification introduces three new capability + registers: dsacap[0-2]. User components (e.g., configuration + libraries and workload applications) require this information + to properly utilize the DSA3 features. + This includes SGL capability support, Enabling hardware-specific + optimizations, Configuring memory, etc. + The output consists of values from the three dsacap registers, + concatenated in order and separated by commas. + This attribute should only be visible on DSA devices of version + 3 or later. + What: /sys/bus/dsa/devices/dsa/iaa_cap Date: Sept 14, 2022 KernelVersion: 6.0.0 diff --git a/drivers/dma/idxd/idxd.h b/drivers/dma/idxd/idxd.h index 74e6695881e6..cc0a3fe1c957 100644 --- a/drivers/dma/idxd/idxd.h +++ b/drivers/dma/idxd/idxd.h @@ -252,6 +252,9 @@ struct idxd_hw { struct opcap opcap; u32 cmd_cap; union iaa_cap_reg iaa_cap; + union dsacap0_reg dsacap0; + union dsacap1_reg dsacap1; + union dsacap2_reg dsacap2; }; =20 enum idxd_device_state { diff --git a/drivers/dma/idxd/init.c b/drivers/dma/idxd/init.c index 80355d03004d..cc8203320d40 100644 --- a/drivers/dma/idxd/init.c +++ b/drivers/dma/idxd/init.c @@ -582,6 +582,10 @@ static void idxd_read_caps(struct idxd_device *idxd) } multi_u64_to_bmap(idxd->opcap_bmap, &idxd->hw.opcap.bits[0], 4); =20 + idxd->hw.dsacap0.bits =3D ioread64(idxd->reg_base + IDXD_DSACAP0_OFFSET); + idxd->hw.dsacap1.bits =3D ioread64(idxd->reg_base + IDXD_DSACAP1_OFFSET); + idxd->hw.dsacap2.bits =3D ioread64(idxd->reg_base + IDXD_DSACAP2_OFFSET); + /* read iaa cap */ if (idxd->data->type =3D=3D IDXD_TYPE_IAX && idxd->hw.version >=3D DEVICE= _VERSION_2) idxd->hw.iaa_cap.bits =3D ioread64(idxd->reg_base + IDXD_IAACAP_OFFSET); diff --git a/drivers/dma/idxd/registers.h b/drivers/dma/idxd/registers.h index 006ba206ab1b..45485ecd7bb6 100644 --- a/drivers/dma/idxd/registers.h +++ b/drivers/dma/idxd/registers.h @@ -13,6 +13,7 @@ =20 #define DEVICE_VERSION_1 0x100 #define DEVICE_VERSION_2 0x200 +#define DEVICE_VERSION_3 0x300 =20 #define IDXD_MMIO_BAR 0 #define IDXD_WQ_BAR 2 @@ -582,6 +583,21 @@ union evl_status_reg { u64 bits; } __packed; =20 +#define IDXD_DSACAP0_OFFSET 0x180 +union dsacap0_reg { + u64 bits; +}; + +#define IDXD_DSACAP1_OFFSET 0x188 +union dsacap1_reg { + u64 bits; +}; + +#define IDXD_DSACAP2_OFFSET 0x190 +union dsacap2_reg { + u64 bits; +}; + #define IDXD_MAX_BATCH_IDENT 256 =20 struct __evl_entry { diff --git a/drivers/dma/idxd/sysfs.c b/drivers/dma/idxd/sysfs.c index 9f0701021af0..624b7d1b193f 100644 --- a/drivers/dma/idxd/sysfs.c +++ b/drivers/dma/idxd/sysfs.c @@ -1713,6 +1713,21 @@ static ssize_t event_log_size_store(struct device *d= ev, } static DEVICE_ATTR_RW(event_log_size); =20 +static ssize_t dsacap_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct idxd_device *idxd =3D confdev_to_idxd(dev); + + return sysfs_emit(buf, "%08x,%08x,%08x,%08x,%08x,%08x\n", + upper_32_bits(idxd->hw.dsacap0.bits), + lower_32_bits(idxd->hw.dsacap0.bits), + upper_32_bits(idxd->hw.dsacap1.bits), + lower_32_bits(idxd->hw.dsacap1.bits), + upper_32_bits(idxd->hw.dsacap2.bits), + lower_32_bits(idxd->hw.dsacap2.bits)); +} +static DEVICE_ATTR_RO(dsacap); + static bool idxd_device_attr_max_batch_size_invisible(struct attribute *at= tr, struct idxd_device *idxd) { @@ -1750,6 +1765,14 @@ static bool idxd_device_attr_event_log_size_invisibl= e(struct attribute *attr, !idxd->hw.gen_cap.evl_support); } =20 +static bool idxd_device_attr_dsacap_invisible(struct attribute *attr, + struct idxd_device *idxd) +{ + return attr =3D=3D &dev_attr_dsacap.attr && + (idxd->data->type !=3D IDXD_TYPE_DSA || + idxd->hw.version < DEVICE_VERSION_3); +} + static umode_t idxd_device_attr_visible(struct kobject *kobj, struct attribute *attr, int n) { @@ -1768,6 +1791,9 @@ static umode_t idxd_device_attr_visible(struct kobjec= t *kobj, if (idxd_device_attr_event_log_size_invisible(attr, idxd)) return 0; =20 + if (idxd_device_attr_dsacap_invisible(attr, idxd)) + return 0; + return attr->mode; } =20 @@ -1795,6 +1821,7 @@ static struct attribute *idxd_device_attributes[] =3D= { &dev_attr_cmd_status.attr, &dev_attr_iaa_cap.attr, &dev_attr_event_log_size.attr, + &dev_attr_dsacap.attr, NULL, }; =20 --=20 2.43.0 From nobody Fri Oct 10 13:31:24 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2205720F079; 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([10.239.96.51]) by orviesa009.jf.intel.com with ESMTP; 13 Jun 2025 09:19:24 -0700 From: Yi Sun To: dave.jiang@intel.com, vinicius.gomes@intel.com, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org Cc: yi.sun@intel.com, gordon.jin@intel.com, fenghuay@nvidia.com, anil.s.keshavamurthy@intel.com, philip.lantz@intel.com Subject: [PATCH 2/2] dmaengine: idxd: Add Max SGL Size Support for DSA3.0 Date: Sat, 14 Jun 2025 00:18:34 +0800 Message-ID: <20250613161834.2912353-3-yi.sun@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250613161834.2912353-1-yi.sun@intel.com> References: <20250613161834.2912353-1-yi.sun@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Certain DSA 3.0 opcodes, such as Gather copy and Gather reduce requires max SGL configured for workqueues prior to support these opcodes. Configure the maximum scatter-gather list (SGL) size for workqueues during setup on the supported HW. Application can then properly handle the SGL size without explicitly setting it. Signed-off-by: Yi Sun Co-developed-by: Anil S Keshavamurthy Signed-off-by: Anil S Keshavamurthy diff --git a/drivers/dma/idxd/device.c b/drivers/dma/idxd/device.c index 5cf419fe6b46..1c10b030bea7 100644 Reviewed-by: Dave Jiang --- a/drivers/dma/idxd/device.c +++ b/drivers/dma/idxd/device.c @@ -375,6 +375,7 @@ static void idxd_wq_disable_cleanup(struct idxd_wq *wq) memset(wq->name, 0, WQ_NAME_SIZE); wq->max_xfer_bytes =3D WQ_DEFAULT_MAX_XFER; idxd_wq_set_max_batch_size(idxd->data->type, wq, WQ_DEFAULT_MAX_BATCH); + idxd_wq_set_init_max_sgl_size(idxd, wq); if (wq->opcap_bmap) bitmap_copy(wq->opcap_bmap, idxd->opcap_bmap, IDXD_MAX_OPCAP_BITS); } @@ -974,6 +975,8 @@ static int idxd_wq_config_write(struct idxd_wq *wq) /* bytes 12-15 */ wq->wqcfg->max_xfer_shift =3D ilog2(wq->max_xfer_bytes); idxd_wqcfg_set_max_batch_shift(idxd->data->type, wq->wqcfg, ilog2(wq->max= _batch_size)); + if (idxd_sgl_supported(idxd)) + wq->wqcfg->max_sgl_shift =3D ilog2(wq->max_sgl_size); =20 /* bytes 32-63 */ if (idxd->hw.wq_cap.op_config && wq->opcap_bmap) { @@ -1152,6 +1155,8 @@ static int idxd_wq_load_config(struct idxd_wq *wq) =20 wq->max_xfer_bytes =3D 1ULL << wq->wqcfg->max_xfer_shift; idxd_wq_set_max_batch_size(idxd->data->type, wq, 1U << wq->wqcfg->max_bat= ch_shift); + if (idxd_sgl_supported(idxd)) + wq->max_sgl_size =3D 1U << wq->wqcfg->max_sgl_shift; =20 for (i =3D 0; i < WQCFG_STRIDES(idxd); i++) { wqcfg_offset =3D WQCFG_OFFSET(idxd, wq->id, i); diff --git a/drivers/dma/idxd/idxd.h b/drivers/dma/idxd/idxd.h index cc0a3fe1c957..fe5af50b58a4 100644 --- a/drivers/dma/idxd/idxd.h +++ b/drivers/dma/idxd/idxd.h @@ -227,6 +227,7 @@ struct idxd_wq { char name[WQ_NAME_SIZE + 1]; u64 max_xfer_bytes; u32 max_batch_size; + u32 max_sgl_size; =20 /* Lock to protect upasid_xa access. */ struct mutex uc_lock; @@ -348,6 +349,7 @@ struct idxd_device { =20 u64 max_xfer_bytes; u32 max_batch_size; + u32 max_sgl_size; int max_groups; int max_engines; int max_rdbufs; @@ -692,6 +694,20 @@ static inline void idxd_wq_set_max_batch_size(int idxd= _type, struct idxd_wq *wq, wq->max_batch_size =3D max_batch_size; } =20 +static bool idxd_sgl_supported(struct idxd_device *idxd) +{ + return idxd->hw.dsacap0.sgl_formats && + idxd->data->type =3D=3D IDXD_TYPE_DSA && + idxd->hw.version >=3D DEVICE_VERSION_3; +} + +static inline void idxd_wq_set_init_max_sgl_size(struct idxd_device *idxd, + struct idxd_wq *wq) +{ + if (idxd_sgl_supported(idxd)) + wq->max_sgl_size =3D 1U << idxd->hw.dsacap0.max_sgl_shift; +} + static inline void idxd_wqcfg_set_max_batch_shift(int idxd_type, union wqc= fg *wqcfg, u32 max_batch_shift) { diff --git a/drivers/dma/idxd/init.c b/drivers/dma/idxd/init.c index cc8203320d40..f37a7d7b537a 100644 --- a/drivers/dma/idxd/init.c +++ b/drivers/dma/idxd/init.c @@ -217,6 +217,7 @@ static int idxd_setup_wqs(struct idxd_device *idxd) init_completion(&wq->wq_resurrect); wq->max_xfer_bytes =3D WQ_DEFAULT_MAX_XFER; idxd_wq_set_max_batch_size(idxd->data->type, wq, WQ_DEFAULT_MAX_BATCH); + idxd_wq_set_init_max_sgl_size(idxd, wq); wq->enqcmds_retries =3D IDXD_ENQCMDS_RETRIES; wq->wqcfg =3D kzalloc_node(idxd->wqcfg_size, GFP_KERNEL, dev_to_node(dev= )); if (!wq->wqcfg) { @@ -585,6 +586,10 @@ static void idxd_read_caps(struct idxd_device *idxd) idxd->hw.dsacap0.bits =3D ioread64(idxd->reg_base + IDXD_DSACAP0_OFFSET); idxd->hw.dsacap1.bits =3D ioread64(idxd->reg_base + IDXD_DSACAP1_OFFSET); idxd->hw.dsacap2.bits =3D ioread64(idxd->reg_base + IDXD_DSACAP2_OFFSET); + if (idxd_sgl_supported(idxd)) { + idxd->max_sgl_size =3D 1U << idxd->hw.dsacap0.max_sgl_shift; + dev_dbg(dev, "max sgl size: %u\n", idxd->max_sgl_size); + } =20 /* read iaa cap */ if (idxd->data->type =3D=3D IDXD_TYPE_IAX && idxd->hw.version >=3D DEVICE= _VERSION_2) diff --git a/drivers/dma/idxd/registers.h b/drivers/dma/idxd/registers.h index 45485ecd7bb6..0401cfc95f27 100644 --- a/drivers/dma/idxd/registers.h +++ b/drivers/dma/idxd/registers.h @@ -385,7 +385,8 @@ union wqcfg { /* bytes 12-15 */ u32 max_xfer_shift:5; u32 max_batch_shift:4; - u32 rsvd4:23; + u32 max_sgl_shift:4; + u32 rsvd4:19; =20 /* bytes 16-19 */ u16 occupancy_inth; @@ -585,6 +586,15 @@ union evl_status_reg { =20 #define IDXD_DSACAP0_OFFSET 0x180 union dsacap0_reg { + struct { + u64 max_sgl_shift:4; + u64 max_gr_block_shift:4; + u64 ops_inter_domain:7; + u64 rsvd1:17; + u64 sgl_formats:16; + u64 max_sg_process:8; + u64 rsvd2:8; + }; u64 bits; }; =20 --=20 2.43.0