From nobody Fri Oct 10 13:38:14 2025 Received: from mail-io1-f73.google.com (mail-io1-f73.google.com [209.85.166.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B884020F063 for ; Fri, 13 Jun 2025 15:52:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.166.73 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749829967; cv=none; b=nnj7/nACpnPRVN6Lto+uDAo2umEQTS/iFLaojx/WoRvVNpqjBnRkDo9B0jjPV15fhYL7dbA6CqqpmP+IUg0raFMUE43RzMclUCsAUsD1MQ533PuVYLHNROqwi74BZ1WOR6gG+44dq2YPdwPL3AS8QoojT0NVGUcfBPz1dCMUOT4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749829967; c=relaxed/simple; bh=Ci1/ilbhd8VIC+oxHWhP8i2cQbOsisZvulH3qn/eMlw=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=le4WFoDOr9p7opDlk4Ribq9o+WXjiAvEEYL02pogQWW7WlCfkjaHgr9y/Dm76pHoIW5928XPSBd/SojGn5eMRj1rApVXjk9+Gfu4+Xh9z1vqyqj9AGLZLpuAz14olrbAX64eGYTx9shdoS1+2AdfHQjnvZp8vx8VotEIzdibLvQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--rananta.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=YQZ6wGNI; arc=none smtp.client-ip=209.85.166.73 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--rananta.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="YQZ6wGNI" Received: by mail-io1-f73.google.com with SMTP id ca18e2360f4ac-875bd5522e9so234036439f.2 for ; Fri, 13 Jun 2025 08:52:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1749829964; x=1750434764; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=oeEVYUZ5YyS7Po4kQ9W2WYTxXWOxgfNLZlSZcUsGw0o=; b=YQZ6wGNIXeW2/Nlanw70aG8mRTW090hfY1ouit3nTVAJfMt3n3N3bySphy1+uE2Qfw 86hnPRpSjvrrHUk/sLdFPipYminFedCVqDS/7rhcFIGJKvng1NFK+b8AO4smE7N08Qje I2VL0hiwYTYYkxnyZT8h+fF7jcbOyk46XWyXH6CcVsPsOlOkVmSZz0nlHvczuokZ9L1s 1baCS4tTqWteNwzKYQHfYyDiy9aqNFv3MegoeuWuKoopLgLzq8NNSKM+C7ez+5SUVvtG zYA0RgBFxSdB/C7kJ1mt2s3rms1CAlZVxbGCt493FKmpvH+ffmhFFokZmiLpMYFDFQUq Sw0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1749829964; x=1750434764; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=oeEVYUZ5YyS7Po4kQ9W2WYTxXWOxgfNLZlSZcUsGw0o=; b=Iuf7ILA0n5+dOBGfzPVnu3EaIkI6s8igJagLOew3W8nFiN8XFN9Nyl/rwgL/ULLxGT WREn0KdoNwcp8G7XQ/zZ6WWwE3D1AgyD0da7GChTnRcFtyIP6wUpO2l4xADbVZtQBxQQ SM0fRRm7Z6kloBns3u3lwWUhBqI0AlRe32EVnmYMUQV8OU2O10T3aLJOujIIdsMvpx3A akVHNH15WYjp+IH/g8p+YlUh6+z4OiiN3ZFwt7nQIAcRcd/EKEYcS7oofY64Uqeo0NzF 4WW72o7o33uKXRl4Q0K4svs8eb8VeXDp/skRTFT8qXpMNtRDn5/vtqe1zdN+QWPiL71K HEwA== X-Forwarded-Encrypted: i=1; AJvYcCWX28ymNrQedpvh43ojR0dJ2UoO1GMgOu4EuI3+A3WCrGS6PZO5zc4X/KmSkBCnXb2kkgP707dv3/7otQY=@vger.kernel.org X-Gm-Message-State: AOJu0YzT7ncM/Rg2g65zm8+3AAwA2Qdayg0FZQe2ggogFu+MQp8QyKXr aTKHxy2zARz4TPZrkTcGguhsScwDgHh5QnuD3aNgf4M3/bGOuqUbHpKNkCviCkMaU18qwDytSBz te8GV4dmq7g== X-Google-Smtp-Source: AGHT+IFunbFJhKmi5ZFShXe5exfB3EJuEIksn0wi7XdmxJ1Imwtlw1UTfq/1Z4OxBS2uV1KpJFLBY6hAS3Gk X-Received: from iobel14.prod.google.com ([2002:a05:6602:3e8e:b0:86c:fede:130b]) (user=rananta job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6602:7504:b0:873:f22:92fb with SMTP id ca18e2360f4ac-875d3bf0780mr439553039f.1.1749829963955; Fri, 13 Jun 2025 08:52:43 -0700 (PDT) Date: Fri, 13 Jun 2025 15:52:35 +0000 In-Reply-To: <20250613155239.2029059-1-rananta@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250613155239.2029059-1-rananta@google.com> X-Mailer: git-send-email 2.50.0.rc2.692.g299adb8693-goog Message-ID: <20250613155239.2029059-2-rananta@google.com> Subject: [PATCH v3 1/4] KVM: arm64: Disambiguate support for vSGIs v. vLPIs From: Raghavendra Rao Ananta To: Oliver Upton , Marc Zyngier Cc: Raghavendra Rao Anata , Mingwei Zhang , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Oliver Upton vgic_supports_direct_msis() is a bit of a misnomer, as it returns true if either vSGIs or vLPIs are supported. Pick it apart into a few predicates and replace some open-coded checks for vSGIs. Signed-off-by: Oliver Upton --- arch/arm64/kvm/vgic/vgic-init.c | 4 ++-- arch/arm64/kvm/vgic/vgic-mmio-v3.c | 16 ++++++++++------ arch/arm64/kvm/vgic/vgic-v4.c | 4 ++-- arch/arm64/kvm/vgic/vgic.c | 4 ++-- arch/arm64/kvm/vgic/vgic.h | 7 +++++++ 5 files changed, 23 insertions(+), 12 deletions(-) diff --git a/arch/arm64/kvm/vgic/vgic-init.c b/arch/arm64/kvm/vgic/vgic-ini= t.c index eb1205654ac8..5e0e4559004b 100644 --- a/arch/arm64/kvm/vgic/vgic-init.c +++ b/arch/arm64/kvm/vgic/vgic-init.c @@ -395,7 +395,7 @@ int vgic_init(struct kvm *kvm) * v4 support so that we get HW-accelerated vSGIs. Otherwise, only * enable it if we present a virtual ITS to the guest. */ - if (vgic_supports_direct_msis(kvm)) { + if (vgic_supports_direct_irqs(kvm)) { ret =3D vgic_v4_init(kvm); if (ret) goto out; @@ -443,7 +443,7 @@ static void kvm_vgic_dist_destroy(struct kvm *kvm) dist->vgic_cpu_base =3D VGIC_ADDR_UNDEF; } =20 - if (vgic_supports_direct_msis(kvm)) + if (vgic_supports_direct_irqs(kvm)) vgic_v4_teardown(kvm); =20 xa_destroy(&dist->lpi_xa); diff --git a/arch/arm64/kvm/vgic/vgic-mmio-v3.c b/arch/arm64/kvm/vgic/vgic-= mmio-v3.c index ae4c0593d114..1a9c5b4418b2 100644 --- a/arch/arm64/kvm/vgic/vgic-mmio-v3.c +++ b/arch/arm64/kvm/vgic/vgic-mmio-v3.c @@ -50,8 +50,12 @@ bool vgic_has_its(struct kvm *kvm) =20 bool vgic_supports_direct_msis(struct kvm *kvm) { - return (kvm_vgic_global_state.has_gicv4_1 || - (kvm_vgic_global_state.has_gicv4 && vgic_has_its(kvm))); + return kvm_vgic_global_state.has_gicv4 && vgic_has_its(kvm); +} + +bool vgic_supports_direct_sgis(struct kvm *kvm) +{ + return kvm_vgic_global_state.has_gicv4_1 && gic_cpuif_has_vsgi(); } =20 /* @@ -86,7 +90,7 @@ static unsigned long vgic_mmio_read_v3_misc(struct kvm_vc= pu *vcpu, } break; case GICD_TYPER2: - if (kvm_vgic_global_state.has_gicv4_1 && gic_cpuif_has_vsgi()) + if (vgic_supports_direct_sgis(vcpu->kvm)) value =3D GICD_TYPER2_nASSGIcap; break; case GICD_IIDR: @@ -119,7 +123,7 @@ static void vgic_mmio_write_v3_misc(struct kvm_vcpu *vc= pu, dist->enabled =3D val & GICD_CTLR_ENABLE_SS_G1; =20 /* Not a GICv4.1? No HW SGIs */ - if (!kvm_vgic_global_state.has_gicv4_1 || !gic_cpuif_has_vsgi()) + if (!vgic_supports_direct_sgis(vcpu->kvm)) val &=3D ~GICD_CTLR_nASSGIreq; =20 /* Dist stays enabled? nASSGIreq is RO */ @@ -133,7 +137,7 @@ static void vgic_mmio_write_v3_misc(struct kvm_vcpu *vc= pu, if (is_hwsgi !=3D dist->nassgireq) vgic_v4_configure_vsgis(vcpu->kvm); =20 - if (kvm_vgic_global_state.has_gicv4_1 && + if (vgic_supports_direct_sgis(vcpu->kvm) && was_enabled !=3D dist->enabled) kvm_make_all_cpus_request(vcpu->kvm, KVM_REQ_RELOAD_GICv4); else if (!was_enabled && dist->enabled) @@ -178,7 +182,7 @@ static int vgic_mmio_uaccess_write_v3_misc(struct kvm_v= cpu *vcpu, } case GICD_CTLR: /* Not a GICv4.1? No HW SGIs */ - if (!kvm_vgic_global_state.has_gicv4_1) + if (vgic_supports_direct_sgis(vcpu->kvm)) val &=3D ~GICD_CTLR_nASSGIreq; =20 dist->enabled =3D val & GICD_CTLR_ENABLE_SS_G1; diff --git a/arch/arm64/kvm/vgic/vgic-v4.c b/arch/arm64/kvm/vgic/vgic-v4.c index 193946108192..e7e284d47a77 100644 --- a/arch/arm64/kvm/vgic/vgic-v4.c +++ b/arch/arm64/kvm/vgic/vgic-v4.c @@ -356,7 +356,7 @@ int vgic_v4_put(struct kvm_vcpu *vcpu) { struct its_vpe *vpe =3D &vcpu->arch.vgic_cpu.vgic_v3.its_vpe; =20 - if (!vgic_supports_direct_msis(vcpu->kvm) || !vpe->resident) + if (!vgic_supports_direct_irqs(vcpu->kvm) || !vpe->resident) return 0; =20 return its_make_vpe_non_resident(vpe, vgic_v4_want_doorbell(vcpu)); @@ -367,7 +367,7 @@ int vgic_v4_load(struct kvm_vcpu *vcpu) struct its_vpe *vpe =3D &vcpu->arch.vgic_cpu.vgic_v3.its_vpe; int err; =20 - if (!vgic_supports_direct_msis(vcpu->kvm) || vpe->resident) + if (!vgic_supports_direct_irqs(vcpu->kvm) || vpe->resident) return 0; =20 if (vcpu_get_flag(vcpu, IN_WFI)) diff --git a/arch/arm64/kvm/vgic/vgic.c b/arch/arm64/kvm/vgic/vgic.c index 8f8096d48925..f5148b38120a 100644 --- a/arch/arm64/kvm/vgic/vgic.c +++ b/arch/arm64/kvm/vgic/vgic.c @@ -951,7 +951,7 @@ void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu) * can be directly injected (GICv4). */ if (list_empty(&vcpu->arch.vgic_cpu.ap_list_head) && - !vgic_supports_direct_msis(vcpu->kvm)) + !vgic_supports_direct_irqs(vcpu->kvm)) return; =20 DEBUG_SPINLOCK_BUG_ON(!irqs_disabled()); @@ -965,7 +965,7 @@ void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu) if (can_access_vgic_from_kernel()) vgic_restore_state(vcpu); =20 - if (vgic_supports_direct_msis(vcpu->kvm)) + if (vgic_supports_direct_irqs(vcpu->kvm)) vgic_v4_commit(vcpu); } =20 diff --git a/arch/arm64/kvm/vgic/vgic.h b/arch/arm64/kvm/vgic/vgic.h index 4349084cb9a6..ebf9ed6adeac 100644 --- a/arch/arm64/kvm/vgic/vgic.h +++ b/arch/arm64/kvm/vgic/vgic.h @@ -370,6 +370,13 @@ int vgic_its_inv_lpi(struct kvm *kvm, struct vgic_irq = *irq); int vgic_its_invall(struct kvm_vcpu *vcpu); =20 bool vgic_supports_direct_msis(struct kvm *kvm); +bool vgic_supports_direct_sgis(struct kvm *kvm); + +static inline bool vgic_supports_direct_irqs(struct kvm *kvm) +{ + return vgic_supports_direct_msis(kvm) || vgic_supports_direct_sgis(kvm); +} + int vgic_v4_init(struct kvm *kvm); void vgic_v4_teardown(struct kvm *kvm); void vgic_v4_configure_vsgis(struct kvm *kvm); --=20 2.50.0.rc2.692.g299adb8693-goog From nobody Fri Oct 10 13:38:14 2025 Received: from mail-io1-f73.google.com (mail-io1-f73.google.com [209.85.166.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5FBD41F8690 for ; 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Fri, 13 Jun 2025 08:52:44 -0700 (PDT) Date: Fri, 13 Jun 2025 15:52:36 +0000 In-Reply-To: <20250613155239.2029059-1-rananta@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250613155239.2029059-1-rananta@google.com> X-Mailer: git-send-email 2.50.0.rc2.692.g299adb8693-goog Message-ID: <20250613155239.2029059-3-rananta@google.com> Subject: [PATCH v3 2/4] KVM: arm64: vgic-v3: Consolidate MAINT_IRQ handling From: Raghavendra Rao Ananta To: Oliver Upton , Marc Zyngier Cc: Raghavendra Rao Anata , Mingwei Zhang , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Oliver Upton Consolidate the duplicated handling of the VGICv3 maintenance IRQ attribute as a regular GICv3 attribute, as it is neither a register nor a common attribute. Signed-off-by: Oliver Upton --- arch/arm64/kvm/vgic/vgic-kvm-device.c | 51 +++++++++++++-------------- 1 file changed, 25 insertions(+), 26 deletions(-) diff --git a/arch/arm64/kvm/vgic/vgic-kvm-device.c b/arch/arm64/kvm/vgic/vg= ic-kvm-device.c index f9ae790163fb..e28cf68a49c3 100644 --- a/arch/arm64/kvm/vgic/vgic-kvm-device.c +++ b/arch/arm64/kvm/vgic/vgic-kvm-device.c @@ -303,12 +303,6 @@ static int vgic_get_common_attr(struct kvm_device *dev, VGIC_NR_PRIVATE_IRQS, uaddr); break; } - case KVM_DEV_ARM_VGIC_GRP_MAINT_IRQ: { - u32 __user *uaddr =3D (u32 __user *)(long)attr->addr; - - r =3D put_user(dev->kvm->arch.vgic.mi_intid, uaddr); - break; - } } =20 return r; @@ -523,7 +517,7 @@ static int vgic_v3_attr_regs_access(struct kvm_device *= dev, struct vgic_reg_attr reg_attr; gpa_t addr; struct kvm_vcpu *vcpu; - bool uaccess, post_init =3D true; + bool uaccess; u32 val; int ret; =20 @@ -539,9 +533,6 @@ static int vgic_v3_attr_regs_access(struct kvm_device *= dev, /* Sysregs uaccess is performed by the sysreg handling code */ uaccess =3D false; break; - case KVM_DEV_ARM_VGIC_GRP_MAINT_IRQ: - post_init =3D false; - fallthrough; default: uaccess =3D true; } @@ -561,7 +552,7 @@ static int vgic_v3_attr_regs_access(struct kvm_device *= dev, =20 mutex_lock(&dev->kvm->arch.config_lock); =20 - if (post_init !=3D vgic_initialized(dev->kvm)) { + if (!vgic_initialized(dev->kvm)) { ret =3D -EBUSY; goto out; } @@ -591,19 +582,6 @@ static int vgic_v3_attr_regs_access(struct kvm_device = *dev, } break; } - case KVM_DEV_ARM_VGIC_GRP_MAINT_IRQ: - if (!is_write) { - val =3D dev->kvm->arch.vgic.mi_intid; - ret =3D 0; - break; - } - - ret =3D -EINVAL; - if ((val < VGIC_NR_PRIVATE_IRQS) && (val >=3D VGIC_NR_SGIS)) { - dev->kvm->arch.vgic.mi_intid =3D val; - ret =3D 0; - } - break; default: ret =3D -EINVAL; break; @@ -630,8 +608,24 @@ static int vgic_v3_set_attr(struct kvm_device *dev, case KVM_DEV_ARM_VGIC_GRP_REDIST_REGS: case KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS: case KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO: - case KVM_DEV_ARM_VGIC_GRP_MAINT_IRQ: return vgic_v3_attr_regs_access(dev, attr, true); + case KVM_DEV_ARM_VGIC_GRP_MAINT_IRQ: { + u32 __user *uaddr =3D (u32 __user *)attr->addr; + u32 val; + + if (get_user(val, uaddr)) + return -EFAULT; + + guard(mutex)(&dev->kvm->arch.config_lock); + if (vgic_initialized(dev->kvm)) + return -EBUSY; + + if ((val < VGIC_NR_SGIS) || (val >=3D VGIC_NR_PRIVATE_IRQS)) + return -EINVAL; + + dev->kvm->arch.vgic.mi_intid =3D val; + return 0; + } default: return vgic_set_common_attr(dev, attr); } @@ -645,8 +639,13 @@ static int vgic_v3_get_attr(struct kvm_device *dev, case KVM_DEV_ARM_VGIC_GRP_REDIST_REGS: case KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS: case KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO: - case KVM_DEV_ARM_VGIC_GRP_MAINT_IRQ: return vgic_v3_attr_regs_access(dev, attr, false); + case KVM_DEV_ARM_VGIC_GRP_MAINT_IRQ: { + u32 __user *uaddr =3D (u32 __user *)(long)attr->addr; + + guard(mutex)(&dev->kvm->arch.config_lock); + return put_user(dev->kvm->arch.vgic.mi_intid, uaddr); + } default: return vgic_get_common_attr(dev, attr); } --=20 2.50.0.rc2.692.g299adb8693-goog From nobody Fri Oct 10 13:38:14 2025 Received: from mail-io1-f73.google.com (mail-io1-f73.google.com [209.85.166.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 976C321421C for ; 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Fri, 13 Jun 2025 08:52:45 -0700 (PDT) Date: Fri, 13 Jun 2025 15:52:37 +0000 In-Reply-To: <20250613155239.2029059-1-rananta@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250613155239.2029059-1-rananta@google.com> X-Mailer: git-send-email 2.50.0.rc2.692.g299adb8693-goog Message-ID: <20250613155239.2029059-4-rananta@google.com> Subject: [PATCH v3 3/4] KVM: arm64: Introduce attribute to control GICD_TYPER2.nASSGIcap From: Raghavendra Rao Ananta To: Oliver Upton , Marc Zyngier Cc: Raghavendra Rao Anata , Mingwei Zhang , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" KVM unconditionally advertises GICD_TYPER2.nASSGIcap (which internally implies vSGIs) on GICv4.1 systems. Allow userspace to change whether a VM supports the feature. Only allow changes prior to VGIC initialization as at that point vPEs need to be allocated for the VM. For convenience, bundle support for vLPIs and vSGIs behind this feature, allowing userspace to control vPE allocation for VMs in environments that may be constrained on vPE IDs. Signed-off-by: Raghavendra Rao Ananta Signed-off-by: Oliver Upton --- .../virt/kvm/devices/arm-vgic-v3.rst | 29 +++++++++++++++ arch/arm64/include/uapi/asm/kvm.h | 3 ++ arch/arm64/kvm/vgic/vgic-init.c | 3 ++ arch/arm64/kvm/vgic/vgic-kvm-device.c | 37 +++++++++++++++++++ arch/arm64/kvm/vgic/vgic-mmio-v3.c | 10 ++++- arch/arm64/kvm/vgic/vgic-v3.c | 5 ++- arch/arm64/kvm/vgic/vgic-v4.c | 2 +- include/kvm/arm_vgic.h | 3 ++ 8 files changed, 88 insertions(+), 4 deletions(-) diff --git a/Documentation/virt/kvm/devices/arm-vgic-v3.rst b/Documentation= /virt/kvm/devices/arm-vgic-v3.rst index e860498b1e35..049d77eae591 100644 --- a/Documentation/virt/kvm/devices/arm-vgic-v3.rst +++ b/Documentation/virt/kvm/devices/arm-vgic-v3.rst @@ -306,3 +306,32 @@ Groups: =20 The vINTID specifies which interrupt is generated when the vGIC must generate a maintenance interrupt. This must be a PPI. + + KVM_DEV_ARM_VGIC_GRP_FEATURES + Attributes: + + KVM_DEV_ARM_VGIC_FEATURE_nASSGIcap + Control whether support for SGIs without an active state is exposed + to the VM. attr->addr points to a __u8 value which indicates whether + he feature is enabled / disabled. + + A value of 0 indicates that the feature is disabled. A nonzero value + indicates that the feature is enabled. + + This attribute can only be set prior to initializing the VGIC (i.e. + KVM_DEV_ARM_VGIC_CTRL_INIT). + + Support for SGIs without an active state depends on hardware support. + Userspace can discover support for the feature by reading the + attribute after creating a VGICv3. It is possible that + KVM_DEV_ARM_VGIC_CTRL_INIT can later fail if this feature is enabled + and KVM is unable to allocate GIC vPEs for the VM. + + Errors: + + =3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + -ENXIO Invalid attribute in attr->attr + -EFAULT Invalid user address in attr->addr + -EBUSY The VGIC has already been initialized + -EINVAL KVM doesn't support the requested feature setting + =3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D diff --git a/arch/arm64/include/uapi/asm/kvm.h b/arch/arm64/include/uapi/as= m/kvm.h index ed5f3892674c..41e9ce412afd 100644 --- a/arch/arm64/include/uapi/asm/kvm.h +++ b/arch/arm64/include/uapi/asm/kvm.h @@ -417,6 +417,7 @@ enum { #define KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO 7 #define KVM_DEV_ARM_VGIC_GRP_ITS_REGS 8 #define KVM_DEV_ARM_VGIC_GRP_MAINT_IRQ 9 +#define KVM_DEV_ARM_VGIC_GRP_FEATURES 10 #define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT 10 #define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK \ (0x3fffffULL << KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT) @@ -429,6 +430,8 @@ enum { #define KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES 3 #define KVM_DEV_ARM_ITS_CTRL_RESET 4 =20 +#define KVM_DEV_ARM_VGIC_FEATURE_nASSGIcap 0 + /* Device Control API on vcpu fd */ #define KVM_ARM_VCPU_PMU_V3_CTRL 0 #define KVM_ARM_VCPU_PMU_V3_IRQ 0 diff --git a/arch/arm64/kvm/vgic/vgic-init.c b/arch/arm64/kvm/vgic/vgic-ini= t.c index 5e0e4559004b..944e24750ac4 100644 --- a/arch/arm64/kvm/vgic/vgic-init.c +++ b/arch/arm64/kvm/vgic/vgic-init.c @@ -157,6 +157,9 @@ int kvm_vgic_create(struct kvm *kvm, u32 type) =20 kvm->arch.vgic.in_kernel =3D true; kvm->arch.vgic.vgic_model =3D type; + if (type =3D=3D KVM_DEV_TYPE_ARM_VGIC_V3) + kvm->arch.vgic.nassgicap =3D kvm_vgic_global_state.has_gicv4_1 && + gic_cpuif_has_vsgi(); =20 kvm->arch.vgic.vgic_dist_base =3D VGIC_ADDR_UNDEF; =20 diff --git a/arch/arm64/kvm/vgic/vgic-kvm-device.c b/arch/arm64/kvm/vgic/vg= ic-kvm-device.c index e28cf68a49c3..629f56063a13 100644 --- a/arch/arm64/kvm/vgic/vgic-kvm-device.c +++ b/arch/arm64/kvm/vgic/vgic-kvm-device.c @@ -626,6 +626,26 @@ static int vgic_v3_set_attr(struct kvm_device *dev, dev->kvm->arch.vgic.mi_intid =3D val; return 0; } + case KVM_DEV_ARM_VGIC_GRP_FEATURES: { + u8 __user *uaddr =3D (u8 __user *)attr->addr; + u8 val; + + if (attr->attr !=3D KVM_DEV_ARM_VGIC_FEATURE_nASSGIcap) + return -ENXIO; + + if (get_user(val, uaddr)) + return -EFAULT; + + guard(mutex)(&dev->kvm->arch.config_lock); + if (vgic_initialized(dev->kvm)) + return -EBUSY; + + if (!(kvm_vgic_global_state.has_gicv4_1 && gic_cpuif_has_vsgi()) && val) + return -EINVAL; + + dev->kvm->arch.vgic.nassgicap =3D val; + return 0; + } default: return vgic_set_common_attr(dev, attr); } @@ -646,6 +666,17 @@ static int vgic_v3_get_attr(struct kvm_device *dev, guard(mutex)(&dev->kvm->arch.config_lock); return put_user(dev->kvm->arch.vgic.mi_intid, uaddr); } + case KVM_DEV_ARM_VGIC_GRP_FEATURES: { + u8 __user *uaddr =3D (u8 __user *)attr->addr; + u8 val; + + if (attr->attr !=3D KVM_DEV_ARM_VGIC_FEATURE_nASSGIcap) + return -ENXIO; + + guard(mutex)(&dev->kvm->arch.config_lock); + val =3D dev->kvm->arch.vgic.nassgicap; + return put_user(val, uaddr); + } default: return vgic_get_common_attr(dev, attr); } @@ -683,8 +714,14 @@ static int vgic_v3_has_attr(struct kvm_device *dev, return 0; case KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES: return 0; + default: + return -ENXIO; } + case KVM_DEV_ARM_VGIC_GRP_FEATURES: + return attr->attr !=3D KVM_DEV_ARM_VGIC_FEATURE_nASSGIcap ? + -ENXIO : 0; } + return -ENXIO; } =20 diff --git a/arch/arm64/kvm/vgic/vgic-mmio-v3.c b/arch/arm64/kvm/vgic/vgic-= mmio-v3.c index 1a9c5b4418b2..43f59e70e1a2 100644 --- a/arch/arm64/kvm/vgic/vgic-mmio-v3.c +++ b/arch/arm64/kvm/vgic/vgic-mmio-v3.c @@ -50,12 +50,20 @@ bool vgic_has_its(struct kvm *kvm) =20 bool vgic_supports_direct_msis(struct kvm *kvm) { + /* + * Deliberately conflate vLPI and vSGI support on GICv4.1 hardware, + * indirectly allowing userspace to control whether or not vPEs are + * allocated for the VM. + */ + if (kvm_vgic_global_state.has_gicv4_1 && !vgic_supports_direct_sgis(kvm)) + return false; + return kvm_vgic_global_state.has_gicv4 && vgic_has_its(kvm); } =20 bool vgic_supports_direct_sgis(struct kvm *kvm) { - return kvm_vgic_global_state.has_gicv4_1 && gic_cpuif_has_vsgi(); + return kvm->arch.vgic.nassgicap; } =20 /* diff --git a/arch/arm64/kvm/vgic/vgic-v3.c b/arch/arm64/kvm/vgic/vgic-v3.c index b9ad7c42c5b0..cb6bda9b3c6c 100644 --- a/arch/arm64/kvm/vgic/vgic-v3.c +++ b/arch/arm64/kvm/vgic/vgic-v3.c @@ -404,7 +404,8 @@ int vgic_v3_save_pending_tables(struct kvm *kvm) * The above vgic initialized check also ensures that the allocation * and enabling of the doorbells have already been done. */ - if (kvm_vgic_global_state.has_gicv4_1) { + if (kvm_vgic_global_state.has_gicv4_1 && + vgic_supports_direct_irqs(kvm)) { unmap_all_vpes(kvm); vlpi_avail =3D true; } @@ -581,7 +582,7 @@ int vgic_v3_map_resources(struct kvm *kvm) return -EBUSY; } =20 - if (kvm_vgic_global_state.has_gicv4_1) + if (vgic_supports_direct_sgis(kvm)) vgic_v4_configure_vsgis(kvm); =20 return 0; diff --git a/arch/arm64/kvm/vgic/vgic-v4.c b/arch/arm64/kvm/vgic/vgic-v4.c index e7e284d47a77..25e9da9e7a2d 100644 --- a/arch/arm64/kvm/vgic/vgic-v4.c +++ b/arch/arm64/kvm/vgic/vgic-v4.c @@ -245,7 +245,7 @@ int vgic_v4_init(struct kvm *kvm) =20 lockdep_assert_held(&kvm->arch.config_lock); =20 - if (!kvm_vgic_global_state.has_gicv4) + if (!vgic_supports_direct_irqs(kvm)) return 0; /* Nothing to see here... move along. */ =20 if (dist->its_vm.vpes) diff --git a/include/kvm/arm_vgic.h b/include/kvm/arm_vgic.h index 4a34f7f0a864..1b4886f3fb20 100644 --- a/include/kvm/arm_vgic.h +++ b/include/kvm/arm_vgic.h @@ -264,6 +264,9 @@ struct vgic_dist { /* distributor enabled */ bool enabled; =20 + /* Supports SGIs without active state */ + bool nassgicap; + /* Wants SGIs without active state */ bool nassgireq; =20 --=20 2.50.0.rc2.692.g299adb8693-goog From nobody Fri Oct 10 13:38:14 2025 Received: from mail-ot1-f74.google.com (mail-ot1-f74.google.com [209.85.210.74]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 80E4A21421C for ; Fri, 13 Jun 2025 15:52:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.74 ARC-Seal: i=1; a=rsa-sha256; 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Fri, 13 Jun 2025 08:52:46 -0700 (PDT) Date: Fri, 13 Jun 2025 15:52:38 +0000 In-Reply-To: <20250613155239.2029059-1-rananta@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250613155239.2029059-1-rananta@google.com> X-Mailer: git-send-email 2.50.0.rc2.692.g299adb8693-goog Message-ID: <20250613155239.2029059-5-rananta@google.com> Subject: [PATCH v3 4/4] KVM: arm64: selftests: Add test for nASSGIcap attribute From: Raghavendra Rao Ananta To: Oliver Upton , Marc Zyngier Cc: Raghavendra Rao Anata , Mingwei Zhang , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Extend vgic_init to test the nASSGIcap attribute, asserting that it is configurable (within reason) prior to initializing the VGIC. Additionally, check that userspace cannot set the attribute after the VGIC has been initialized. Signed-off-by: Raghavendra Rao Ananta Signed-off-by: Oliver Upton --- tools/testing/selftests/kvm/arm64/vgic_init.c | 41 +++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/tools/testing/selftests/kvm/arm64/vgic_init.c b/tools/testing/= selftests/kvm/arm64/vgic_init.c index b3b5fb0ff0a9..aaecba432dbc 100644 --- a/tools/testing/selftests/kvm/arm64/vgic_init.c +++ b/tools/testing/selftests/kvm/arm64/vgic_init.c @@ -675,6 +675,46 @@ static void test_v3_its_region(void) vm_gic_destroy(&v); } =20 +static void test_v3_nassgicap(void) +{ + struct kvm_vcpu *vcpus[NR_VCPUS]; + struct vm_gic vm; + __u8 nassgicap; + int ret; + + vm =3D vm_gic_create_with_vcpus(KVM_DEV_TYPE_ARM_VGIC_V3, NR_VCPUS, vcpus= ); + TEST_REQUIRE(!__kvm_has_device_attr(vm.gic_fd, KVM_DEV_ARM_VGIC_GRP_FEATU= RES, + KVM_DEV_ARM_VGIC_FEATURE_nASSGIcap)); + + kvm_device_attr_get(vm.gic_fd, KVM_DEV_ARM_VGIC_GRP_FEATURES, + KVM_DEV_ARM_VGIC_FEATURE_nASSGIcap, &nassgicap); + if (!nassgicap) { + nassgicap =3D true; + ret =3D __kvm_device_attr_set(vm.gic_fd, KVM_DEV_ARM_VGIC_GRP_FEATURES, + KVM_DEV_ARM_VGIC_FEATURE_nASSGIcap, &nassgicap); + TEST_ASSERT(ret && errno =3D=3D EINVAL, + "Enabled nASSGIcap even though it's unavailable"); + } else { + nassgicap =3D false; + kvm_device_attr_set(vm.gic_fd, KVM_DEV_ARM_VGIC_GRP_FEATURES, + KVM_DEV_ARM_VGIC_FEATURE_nASSGIcap, &nassgicap); + + nassgicap =3D true; + kvm_device_attr_set(vm.gic_fd, KVM_DEV_ARM_VGIC_GRP_FEATURES, + KVM_DEV_ARM_VGIC_FEATURE_nASSGIcap, &nassgicap); + } + + kvm_device_attr_set(vm.gic_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, + KVM_DEV_ARM_VGIC_CTRL_INIT, NULL); + + ret =3D __kvm_device_attr_set(vm.gic_fd, KVM_DEV_ARM_VGIC_GRP_FEATURES, + KVM_DEV_ARM_VGIC_FEATURE_nASSGIcap, &nassgicap); + TEST_ASSERT(ret && errno =3D=3D EBUSY, + "Configured nASSGIcap after initializing the VGIC"); + + vm_gic_destroy(&vm); +} + /* * Returns 0 if it's possible to create GIC device of a given type (V2 or = V3). */ @@ -730,6 +770,7 @@ void run_tests(uint32_t gic_dev_type) test_v3_last_bit_single_rdist(); test_v3_redist_ipa_range_check_at_vcpu_run(); test_v3_its_region(); + test_v3_nassgicap(); } } =20 --=20 2.50.0.rc2.692.g299adb8693-goog