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Fri, 13 Jun 2025 06:56:40 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH 1/3] arm64: dts: renesas: r9a09g077: Remove GIC_CPU_MASK_SIMPLE() from timer node Date: Fri, 13 Jun 2025 14:56:12 +0100 Message-ID: <20250613135614.154100-2-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250613135614.154100-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250613135614.154100-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar The RZ/T2H SoC uses GICv3, which does not require a CPU mask in the `interrupts-extended` property of the ARMv8 timer node. The CPU mask macro `GIC_CPU_MASK_SIMPLE()` is only applicable to pre-GICv3 systems. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g077.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi b/arch/arm64/boot/d= ts/renesas/r9a09g077.dtsi index b531e393d8c4..c756a7c3cda2 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi @@ -274,9 +274,9 @@ sdhi1_vqmmc: vqmmc-regulator { =20 timer { compatible =3D "arm,armv8-timer"; - interrupts-extended =3D <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_T= YPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + interrupts-extended =3D <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; }; }; --=20 2.49.0