From nobody Fri Oct 10 13:44:22 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 6773976410 for ; Fri, 13 Jun 2025 13:04:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749819855; cv=none; b=bNnyW1QdWxN4BLmV4D5IdaQQOKKpjX45RhhC67VeGQMat8/40ElCsXHhPDESGG8M9+dFtNTFo7hQsVh90qDLvkN22/T312/VmTLLRqmOUIemvn1fnaKc2Ga+MuF6Ai6sPaHXchszkqXMXS5yO+Tjhrn7RJ25fs8x4IZDpBiqdTU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749819855; c=relaxed/simple; bh=lwkFMbUDRfq7zvVSJJ0Y/V6V8MeJmvET1EKCFo9+p8A=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ryDBg1kXUCeZMJpFs7dvf/F8U+dci1OYM2FtOfq/apssK+gBPTqulStp1SEoUhgJo1jy0BnH18d/e6SxJ4vNO6i7WplhH+3EMm0NWsdhn4sq+feCZTLvNlV19ng64FSPUaJsWfYASMuW8K6UuRsLrKuRbhfvV7sQ26Bg0PMa370= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 197161CDD; Fri, 13 Jun 2025 06:03:52 -0700 (PDT) Received: from merodach.members.linode.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D47B93F59E; Fri, 13 Jun 2025 06:04:10 -0700 (PDT) From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Greg Kroah-Hartman , "Rafael J . Wysocki" , sudeep.holla@arm.com, Rob Herring , Ben Horgan , James Morse Subject: [PATCH 1/5] cacheinfo: Set cache 'id' based on DT data Date: Fri, 13 Jun 2025 13:03:52 +0000 Message-Id: <20250613130356.8080-2-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20250613130356.8080-1-james.morse@arm.com> References: <20250613130356.8080-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Rob Herring Use the minimum CPU h/w id of the CPUs associated with the cache for the cache 'id'. This will provide a stable id value for a given system. As we need to check all possible CPUs, we can't use the shared_cpu_map which is just online CPUs. As there's not a cache to CPUs mapping in DT, we have to walk all CPU nodes and then walk cache levels. The cache_id exposed to user-space has historically been 32 bits, and is too late to change. Give up on assigning cache-id's if a CPU h/w id greater than 32 bits is found. Cc: Greg Kroah-Hartman Cc: "Rafael J. Wysocki" Signed-off-by: Rob Herring [ ben: converted to use the __free cleanup idiom ] Signed-off-by: Ben Horgan [ morse: Add checks to give up if a value larger than 32 bits is seen. ] Signed-off-by: James Morse --- Use as a 32bit value has been seen in DPDK patches here: http://inbox.dpdk.org/dev/20241021015246.304431-2-wathsala.vithanage@arm.co= m/ --- drivers/base/cacheinfo.c | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/drivers/base/cacheinfo.c b/drivers/base/cacheinfo.c index cf0d455209d7..9888d87840a2 100644 --- a/drivers/base/cacheinfo.c +++ b/drivers/base/cacheinfo.c @@ -8,6 +8,7 @@ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt =20 #include +#include #include #include #include @@ -183,6 +184,37 @@ static bool cache_node_is_unified(struct cacheinfo *th= is_leaf, return of_property_read_bool(np, "cache-unified"); } =20 +static void cache_of_set_id(struct cacheinfo *this_leaf, struct device_nod= e *np) +{ + struct device_node *cpu; + u32 min_id =3D ~0; + + for_each_of_cpu_node(cpu) { + struct device_node *cache_node __free(device_node) =3D of_find_next_cach= e_node(cpu); + u64 id =3D of_get_cpu_hwid(cpu, 0); + + if (FIELD_GET(GENMASK_ULL(63, 32), id)) { + of_node_put(cpu); + return; + } + while (1) { + if (!cache_node) + break; + if (cache_node =3D=3D np && id < min_id) { + min_id =3D id; + break; + } + struct device_node *prev __free(device_node) =3D cache_node; + cache_node =3D of_find_next_cache_node(cache_node); + } + } + + if (min_id !=3D ~0) { + this_leaf->id =3D min_id; + this_leaf->attributes |=3D CACHE_ID; + } +} + static void cache_of_set_props(struct cacheinfo *this_leaf, struct device_node *np) { @@ -198,6 +230,7 @@ static void cache_of_set_props(struct cacheinfo *this_l= eaf, cache_get_line_size(this_leaf, np); cache_nr_sets(this_leaf, np); cache_associativity(this_leaf); + cache_of_set_id(this_leaf, np); } =20 static int cache_setup_of_node(unsigned int cpu) --=20 2.39.5 From nobody Fri Oct 10 13:44:22 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 63AA2149C51 for ; Fri, 13 Jun 2025 13:04:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749819857; cv=none; b=bXfAEr0+a1NCImRAeuY3qIcZ5kUjKCNR4CJbVhkKCUj9/uiFVs/0ayxcCOQUXnquDuDl4zux+pTDd2I8/O4mMwkEOUMQyWLKcbH85fDRWQ41cnIbDtPQwJ9BgoSCEvoOfhf4c3A3ZuqZyfPfqAKhYTRV70ofRiiyRHLO1WFFOHI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749819857; c=relaxed/simple; bh=V1199vLhEPBr+wTi5hbKlQugLCws1t1lxOMUm2rIYOg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=RVUwaMaR9SqrQ/LRHgh6JQ3xowquXCr54IDrAzNh/tjR/J+SoX7p7hWpRRZzEG0CA8Wf2+uPjuq13SA2a7VGvhIinmy/b/NJw0/7OXOQRdPCtEFzGv1HMlWCGXdfW8Xgn2wpOVhVfcXufmzF+3jsfNrZ4H6LK7C0opsTIIbOTKU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5A3181C0A; Fri, 13 Jun 2025 06:03:54 -0700 (PDT) Received: from merodach.members.linode.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 3BA293F59E; Fri, 13 Jun 2025 06:04:13 -0700 (PDT) From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Greg Kroah-Hartman , "Rafael J . Wysocki" , sudeep.holla@arm.com, Rob Herring , Ben Horgan , James Morse Subject: [PATCH 2/5] cacheinfo: Add arch hook to compress CPU h/w id into 32 bits for cache-id Date: Fri, 13 Jun 2025 13:03:53 +0000 Message-Id: <20250613130356.8080-3-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20250613130356.8080-1-james.morse@arm.com> References: <20250613130356.8080-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Filesystems like resctrl use the cache-id exposed via sysfs to identify groups of CPUs. The value is also used for PCIe cache steering tags. On DT platforms cache-id is not something that is described in the device-tree, but instead generated from the smallest CPU h/w id of the CPUs associated with that cache. CPU h/w ids may be larger than 32 bits. Add a hook to allow architectures to compress the value from the devicetree into 32 bits. Returning the same value is always safe as cache_of_set_id() will stop if a value larger than 32 bits is seen. For example, on arm64 the value is the MPIDR affinity register, which only has 32 bits of affinity data, but spread across the 64 bit field. An arch-specific bit swizzle gives a 32 bit value. Signed-off-by: James Morse Reviewed-by: Jonathan Cameron --- drivers/base/cacheinfo.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/base/cacheinfo.c b/drivers/base/cacheinfo.c index 9888d87840a2..d8e5b4c7156c 100644 --- a/drivers/base/cacheinfo.c +++ b/drivers/base/cacheinfo.c @@ -184,6 +184,10 @@ static bool cache_node_is_unified(struct cacheinfo *th= is_leaf, return of_property_read_bool(np, "cache-unified"); } =20 +#ifndef arch_compact_of_hwid +#define arch_compact_of_hwid(_x) (_x) +#endif + static void cache_of_set_id(struct cacheinfo *this_leaf, struct device_nod= e *np) { struct device_node *cpu; @@ -193,6 +197,7 @@ static void cache_of_set_id(struct cacheinfo *this_leaf= , struct device_node *np) struct device_node *cache_node __free(device_node) =3D of_find_next_cach= e_node(cpu); u64 id =3D of_get_cpu_hwid(cpu, 0); =20 + id =3D arch_compact_of_hwid(id); if (FIELD_GET(GENMASK_ULL(63, 32), id)) { of_node_put(cpu); return; --=20 2.39.5 From nobody Fri Oct 10 13:44:22 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 1BB8615687D for ; Fri, 13 Jun 2025 13:04:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749819858; cv=none; b=ZaWEWQmJXe5ryQw9hQo7bx2QlE3+mr8zfWh6qHywRN6Z4Na/KPg+oZJAPVPDk19mrklL646xeqG8dkRc9gdDFrgmi6QfCxldQHqfNdrC1e3EZ9XQgAu0e6K0+rJg3y+HQpv+twhHcSILnxKbTeNoejsIPP5pp0z6uz8b4TM+M/o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749819858; c=relaxed/simple; bh=xBHd7ftCSlID8/BsGphSCMIzrEgTd5ElG/eUHO1W7xk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=IZHmT9gWxr0V8BMX01hHhbRLbUz0JbQe6bjyirHypK0vVOJbGihw/HsnLwQpwMrw0M2kKl+oqnJH2Ckblpdrl8QZcX2mPTZJQge1LO6v/pwGNv87v6QPg1BB/8HLGlvJqWBrqPp+VOWVUDpCfPjzK2V0Yz+Hbg22MI9a/RM4LXE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1F8A41CDD; Fri, 13 Jun 2025 06:03:56 -0700 (PDT) Received: from merodach.members.linode.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 609623F59E; Fri, 13 Jun 2025 06:04:15 -0700 (PDT) From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Greg Kroah-Hartman , "Rafael J . Wysocki" , sudeep.holla@arm.com, Rob Herring , Ben Horgan , James Morse Subject: [PATCH 3/5] arm64: cacheinfo: Provide helper to compress MPIDR value into u32 Date: Fri, 13 Jun 2025 13:03:54 +0000 Message-Id: <20250613130356.8080-4-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20250613130356.8080-1-james.morse@arm.com> References: <20250613130356.8080-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Filesystems like resctrl use the cache-id exposed via sysfs to identify groups of CPUs. The value is also used for PCIe cache steering tags. On DT platforms cache-id is not something that is described in the device-tree, but instead generated from the smallest MPIDR of the CPUs associated with that cache. The cache-id exposed to user-space has historically been 32 bits. MPIDR values may be larger than 32 bits. MPIDR only has 32 bits worth of affinity data, but the aff3 field lives above 32bits. The corresponding lower bits are masked out by MPIDR_HWID_BITMASK and contain an SMT flag and Uni-Processor flag. Swizzzle the aff3 field into the bottom 32 bits and using that. In case more affinity fields are added in the future, the upper RES0 area should be checked. Returning a value greater than 32 bits from this helper will cause the caller to give up on allocating cache-ids. Signed-off-by: James Morse Reviewed-by: Jonathan Cameron --- arch/arm64/include/asm/cache.h | 14 ++++++++++++++ arch/arm64/kernel/sleep.S | 1 + 2 files changed, 15 insertions(+) diff --git a/arch/arm64/include/asm/cache.h b/arch/arm64/include/asm/cache.h index 99cd6546e72e..f8798dc96364 100644 --- a/arch/arm64/include/asm/cache.h +++ b/arch/arm64/include/asm/cache.h @@ -42,6 +42,7 @@ =20 #include #include +#include #include =20 #ifdef CONFIG_KASAN_SW_TAGS @@ -87,6 +88,19 @@ int cache_line_size(void); =20 #define dma_get_cache_alignment cache_line_size =20 +/* Compress a u64 MPIDR value into 32 bits. */ +static inline u64 arch_compact_of_hwid(u64 id) +{ + u64 aff3 =3D MPIDR_AFFINITY_LEVEL(id, 3); + + /* These bits are expected to be RES0 */ + if (FIELD_GET(GENMASK_ULL(63, 40), id)) + return id; + + return (aff3 << 24) | FIELD_GET(GENMASK_ULL(23, 0), id); +} +#define arch_compact_of_hwid arch_compact_of_hwid + /* * Read the effective value of CTR_EL0. * diff --git a/arch/arm64/kernel/sleep.S b/arch/arm64/kernel/sleep.S index f093cdf71be1..ebc23304d430 100644 --- a/arch/arm64/kernel/sleep.S +++ b/arch/arm64/kernel/sleep.S @@ -50,6 +50,7 @@ lsr \mask ,\mask, \rs3 orr \dst, \dst, \mask // dst|=3D(aff3>>rs3) .endm + /* * Save CPU state in the provided sleep_stack_data area, and publish its * location for cpu_resume()'s use in sleep_save_stash. --=20 2.39.5 From nobody Fri Oct 10 13:44:22 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id BF89C17A2F2 for ; Fri, 13 Jun 2025 13:04:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749819860; cv=none; b=hNysGjJ3jBK+WRfiweYUlYb9HSwbyWuRbXKuG2cFrFjScPzMyBvupHp+QkDwxtoYT1o5tVVQyloQHLba5GUpxcEz+HxpzA5gLKejjmcbZVWicgTrP5kx1OfUhUZokTa4UNZWXOyV1GMVCFy3C90AMd3IqoOaME1nF9gH6sJvcdk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749819860; c=relaxed/simple; bh=yKI9595118wd9wD0+4O8i9hh8Y/Rq0qQ0WNLjJa/MlM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=C9yIRd9OroELquTPV71D6dIYS5iwH+cs9rz0yeawp6YpOMc57FMPXtZK1l1oaArWji2i1u4bwBykiZGLohOYxHwBux6Sq0VdP/rdxyqvyPLvfUjLQAGipOveqoTVfzxvTUnTi0BTi/gFnWjYq2UWSFAUNqTnApp0aYN0MiJ6MQI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D93551C0A; Fri, 13 Jun 2025 06:03:57 -0700 (PDT) Received: from merodach.members.linode.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 260943F59E; Fri, 13 Jun 2025 06:04:17 -0700 (PDT) From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Greg Kroah-Hartman , "Rafael J . Wysocki" , sudeep.holla@arm.com, Rob Herring , Ben Horgan , James Morse Subject: [PATCH 4/5] cacheinfo: Expose the code to generate a cache-id from a device_node Date: Fri, 13 Jun 2025 13:03:55 +0000 Message-Id: <20250613130356.8080-5-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20250613130356.8080-1-james.morse@arm.com> References: <20250613130356.8080-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The MPAM driver identifies caches by id for use with resctrl. It needs to know the cache-id when probe-ing, but the value isn't set in cacheinfo until the corresponding CPU comes online. Expose the code that generates the cache-id. This allows the MPAM driver to determine the properties of the caches without waiting for all CPUs to come online. Signed-off-by: James Morse --- drivers/base/cacheinfo.c | 15 +++++++++++---- include/linux/cacheinfo.h | 1 + 2 files changed, 12 insertions(+), 4 deletions(-) diff --git a/drivers/base/cacheinfo.c b/drivers/base/cacheinfo.c index d8e5b4c7156c..6316d80abab8 100644 --- a/drivers/base/cacheinfo.c +++ b/drivers/base/cacheinfo.c @@ -188,7 +188,7 @@ static bool cache_node_is_unified(struct cacheinfo *thi= s_leaf, #define arch_compact_of_hwid(_x) (_x) #endif =20 -static void cache_of_set_id(struct cacheinfo *this_leaf, struct device_nod= e *np) +unsigned long cache_of_get_id(struct device_node *np) { struct device_node *cpu; u32 min_id =3D ~0; @@ -200,7 +200,7 @@ static void cache_of_set_id(struct cacheinfo *this_leaf= , struct device_node *np) id =3D arch_compact_of_hwid(id); if (FIELD_GET(GENMASK_ULL(63, 32), id)) { of_node_put(cpu); - return; + return ~0UL; } while (1) { if (!cache_node) @@ -214,8 +214,15 @@ static void cache_of_set_id(struct cacheinfo *this_lea= f, struct device_node *np) } } =20 - if (min_id !=3D ~0) { - this_leaf->id =3D min_id; + return min_id; +} + +static void cache_of_set_id(struct cacheinfo *this_leaf, struct device_nod= e *np) +{ + unsigned long id =3D cache_of_get_id(np); + + if (id !=3D ~0UL) { + this_leaf->id =3D id; this_leaf->attributes |=3D CACHE_ID; } } diff --git a/include/linux/cacheinfo.h b/include/linux/cacheinfo.h index c8f4f0a0b874..9c959caf8af8 100644 --- a/include/linux/cacheinfo.h +++ b/include/linux/cacheinfo.h @@ -112,6 +112,7 @@ int acpi_get_cache_info(unsigned int cpu, #endif =20 const struct attribute_group *cache_get_priv_group(struct cacheinfo *this_= leaf); +unsigned long cache_of_get_id(struct device_node *np); =20 /* * Get the cacheinfo structure for the cache associated with @cpu at --=20 2.39.5 From nobody Fri Oct 10 13:44:22 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 8466518E377 for ; Fri, 13 Jun 2025 13:04:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749819861; cv=none; b=KzV5wC+BKxrIbvYMMdv503j7eIAedLDiEuSXzqlV2w1eLjcVmklqYHmlYh4xVkK5Lvs0TvXUrCtHupsh3cKsoa0z0HWevxoAiCNSNxro12F9GQMziEzPcYGjuhuwxQOTCk+g5eimYk8A79sl/NiT9pbjJFZi01xqVvdWUsvCCqs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749819861; c=relaxed/simple; bh=ksM2r+Oto/NBE+GrS0KZDyWMch35QCoQT8Du9Fc4exU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=EZcDaehH4omySQBiRSJrZZq8++YkMJ1aWMVs7P8mDcLdcDnBMouVL7dOzg6Ydn2HLwR3bac2X01ZZ9PasE6l+AjoTsLB+TelvWStmyfr3G5nxLlxoAD9YsXOJ61CpkrEo40kZK+PMq1BLyX8nePYnUuSGZjMJqyYH9MxI9l9LYw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9450B1CDD; Fri, 13 Jun 2025 06:03:59 -0700 (PDT) Received: from merodach.members.linode.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D2FF13F59E; Fri, 13 Jun 2025 06:04:18 -0700 (PDT) From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Greg Kroah-Hartman , "Rafael J . Wysocki" , sudeep.holla@arm.com, Rob Herring , Ben Horgan , James Morse Subject: [PATCH 5/5] cacheinfo: Add helper to find the cache size from cpu+level Date: Fri, 13 Jun 2025 13:03:56 +0000 Message-Id: <20250613130356.8080-6-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20250613130356.8080-1-james.morse@arm.com> References: <20250613130356.8080-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The MPAM driver needs to know the size of a cache associated with a particular CPU. The DT/ACPI agnostic way of doing this is to ask cacheinfo. Add a helper to do this. Signed-off-by: James Morse --- include/linux/cacheinfo.h | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/include/linux/cacheinfo.h b/include/linux/cacheinfo.h index 9c959caf8af8..3f1b6b2e25b5 100644 --- a/include/linux/cacheinfo.h +++ b/include/linux/cacheinfo.h @@ -148,6 +148,26 @@ static inline int get_cpu_cacheinfo_id(int cpu, int le= vel) return ci ? ci->id : -1; } =20 +/* + * Get the size of the cache associated with @cpu at level @level. + * cpuhp lock must be held. + */ +static inline unsigned int get_cpu_cacheinfo_size(int cpu, int level) +{ + struct cpu_cacheinfo *ci =3D get_cpu_cacheinfo(cpu); + int i; + + if (!ci->info_list) + return 0; + + for (i =3D 0; i < ci->num_leaves; i++) { + if (ci->info_list[i].level =3D=3D level) + return ci->info_list[i].size; + } + + return 0; +} + #if defined(CONFIG_ARM64) || defined(CONFIG_ARM) #define use_arch_cache_info() (true) #else --=20 2.39.5