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Fri, 13 Jun 2025 00:46:25 -0700 (PDT) Received: from localhost ([121.250.214.124]) by smtp.gmail.com with UTF8SMTPSA id d9443c01a7336-2365dea88d2sm8545225ad.148.2025.06.13.00.46.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Jun 2025 00:46:24 -0700 (PDT) From: Inochi Amaoto To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen Wang , Inochi Amaoto , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti Cc: devicetree@vger.kernel.org, sophgo@lists.linux.dev, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Yixun Lan , Longbin Li Subject: [PATCH] riscv: dts: sophgo: sg2044: Add missing riscv,cbop-block-size property Date: Fri, 13 Jun 2025 15:45:12 +0800 Message-ID: <20250613074513.1683624-1-inochiama@gmail.com> X-Mailer: git-send-email 2.49.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The kernel complains no "riscv,cbop-block-size" and disables the Zicbop extension. Add the missing property to keep it functional. Fixes: ae5bac370ed4 ("riscv: dts: sophgo: Add initial device tree of Sophgo= SRD3-10") Signed-off-by: Inochi Amaoto --- arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi | 64 +++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi b/arch/riscv/boot/= dts/sophgo/sg2044-cpus.dtsi index 2a4267078ce6..6a35ed8f253c 100644 --- a/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi @@ -38,6 +38,7 @@ cpu0: cpu@0 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; riscv,cboz-block-size =3D <64>; =20 cpu0_intc: interrupt-controller { @@ -73,6 +74,7 @@ cpu1: cpu@1 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; riscv,cboz-block-size =3D <64>; =20 cpu1_intc: interrupt-controller { @@ -108,6 +110,7 @@ cpu2: cpu@2 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; riscv,cboz-block-size =3D <64>; =20 cpu2_intc: interrupt-controller { @@ -143,6 +146,7 @@ cpu3: cpu@3 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; riscv,cboz-block-size =3D <64>; =20 cpu3_intc: interrupt-controller { @@ -178,6 +182,7 @@ cpu4: cpu@4 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; riscv,cboz-block-size =3D <64>; =20 cpu4_intc: interrupt-controller { @@ -213,6 +218,7 @@ cpu5: cpu@5 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; riscv,cboz-block-size =3D <64>; =20 cpu5_intc: interrupt-controller { @@ -248,6 +254,7 @@ cpu6: cpu@6 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; riscv,cboz-block-size =3D <64>; =20 cpu6_intc: interrupt-controller { @@ -283,6 +290,7 @@ cpu7: cpu@7 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; riscv,cboz-block-size =3D <64>; =20 cpu7_intc: interrupt-controller { @@ -318,6 +326,7 @@ cpu8: cpu@8 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; riscv,cboz-block-size =3D <64>; =20 cpu8_intc: interrupt-controller { @@ -353,6 +362,7 @@ cpu9: cpu@9 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; riscv,cboz-block-size =3D <64>; =20 cpu9_intc: interrupt-controller { @@ -388,6 +398,7 @@ cpu10: cpu@10 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; riscv,cboz-block-size =3D <64>; =20 cpu10_intc: interrupt-controller { @@ -423,6 +434,7 @@ cpu11: cpu@11 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; riscv,cboz-block-size =3D <64>; =20 cpu11_intc: interrupt-controller { @@ -458,6 +470,7 @@ cpu12: cpu@12 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; riscv,cboz-block-size =3D <64>; =20 cpu12_intc: interrupt-controller { @@ -493,6 +506,7 @@ cpu13: cpu@13 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; riscv,cboz-block-size =3D <64>; =20 cpu13_intc: interrupt-controller { @@ -528,6 +542,7 @@ cpu14: cpu@14 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; riscv,cboz-block-size =3D <64>; =20 cpu14_intc: interrupt-controller { @@ -563,6 +578,7 @@ cpu15: cpu@15 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; riscv,cboz-block-size =3D <64>; =20 cpu15_intc: interrupt-controller { @@ -598,6 +614,7 @@ cpu16: cpu@16 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; riscv,cboz-block-size =3D <64>; =20 cpu16_intc: interrupt-controller { @@ -633,6 +650,7 @@ cpu17: cpu@17 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; riscv,cboz-block-size =3D <64>; =20 cpu17_intc: interrupt-controller { @@ -668,6 +686,7 @@ cpu18: cpu@18 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; riscv,cboz-block-size =3D <64>; =20 cpu18_intc: interrupt-controller { @@ -703,6 +722,7 @@ cpu19: cpu@19 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; riscv,cboz-block-size =3D <64>; =20 cpu19_intc: interrupt-controller { @@ -738,6 +758,7 @@ cpu20: cpu@20 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; riscv,cboz-block-size =3D <64>; =20 cpu20_intc: interrupt-controller { @@ -773,6 +794,7 @@ cpu21: cpu@21 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; riscv,cboz-block-size =3D <64>; =20 cpu21_intc: interrupt-controller { @@ -808,6 +830,7 @@ cpu22: cpu@22 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; riscv,cboz-block-size =3D <64>; =20 cpu22_intc: interrupt-controller { @@ -843,6 +866,7 @@ cpu23: cpu@23 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; riscv,cboz-block-size =3D <64>; =20 cpu23_intc: interrupt-controller { @@ -878,6 +902,7 @@ cpu24: cpu@24 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; riscv,cboz-block-size =3D <64>; =20 cpu24_intc: interrupt-controller { @@ -913,6 +938,7 @@ cpu25: cpu@25 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; riscv,cboz-block-size =3D <64>; =20 cpu25_intc: interrupt-controller { @@ -948,6 +974,7 @@ cpu26: cpu@26 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; riscv,cboz-block-size =3D <64>; =20 cpu26_intc: interrupt-controller { @@ -983,6 +1010,7 @@ cpu27: cpu@27 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; riscv,cboz-block-size =3D <64>; =20 cpu27_intc: interrupt-controller { @@ -1018,6 +1046,7 @@ cpu28: cpu@28 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; riscv,cboz-block-size =3D <64>; =20 cpu28_intc: interrupt-controller { @@ -1053,6 +1082,7 @@ cpu29: cpu@29 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; riscv,cboz-block-size =3D <64>; =20 cpu29_intc: interrupt-controller { @@ -1088,6 +1118,7 @@ cpu30: cpu@30 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; riscv,cboz-block-size =3D <64>; =20 cpu30_intc: interrupt-controller { @@ -1123,6 +1154,7 @@ cpu31: cpu@31 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; riscv,cboz-block-size =3D <64>; =20 cpu31_intc: interrupt-controller { @@ -1158,6 +1190,7 @@ cpu32: cpu@32 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; riscv,cboz-block-size =3D <64>; =20 cpu32_intc: interrupt-controller { @@ -1193,6 +1226,7 @@ cpu33: cpu@33 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; riscv,cboz-block-size =3D <64>; =20 cpu33_intc: interrupt-controller { @@ -1228,6 +1262,7 @@ cpu34: cpu@34 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; riscv,cboz-block-size =3D <64>; =20 cpu34_intc: interrupt-controller { @@ -1263,6 +1298,7 @@ cpu35: cpu@35 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; riscv,cboz-block-size =3D <64>; =20 cpu35_intc: interrupt-controller { @@ -1298,6 +1334,7 @@ cpu36: cpu@36 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; riscv,cboz-block-size =3D <64>; =20 cpu36_intc: interrupt-controller { @@ -1333,6 +1370,7 @@ cpu37: cpu@37 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; riscv,cboz-block-size =3D <64>; =20 cpu37_intc: interrupt-controller { @@ -1368,6 +1406,7 @@ cpu38: cpu@38 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; riscv,cboz-block-size =3D <64>; =20 cpu38_intc: interrupt-controller { @@ -1403,6 +1442,7 @@ cpu39: cpu@39 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; riscv,cboz-block-size =3D <64>; =20 cpu39_intc: interrupt-controller { @@ -1438,6 +1478,7 @@ cpu40: cpu@40 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; riscv,cboz-block-size =3D <64>; =20 cpu40_intc: interrupt-controller { @@ -1473,6 +1514,7 @@ cpu41: cpu@41 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; riscv,cboz-block-size =3D <64>; =20 cpu41_intc: interrupt-controller { @@ -1508,6 +1550,7 @@ cpu42: cpu@42 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; riscv,cboz-block-size =3D <64>; =20 cpu42_intc: interrupt-controller { @@ -1543,6 +1586,7 @@ cpu43: cpu@43 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; riscv,cboz-block-size =3D <64>; =20 cpu43_intc: interrupt-controller { @@ -1578,6 +1622,7 @@ cpu44: cpu@44 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; riscv,cboz-block-size =3D <64>; =20 cpu44_intc: interrupt-controller { @@ -1613,6 +1658,7 @@ cpu45: cpu@45 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; riscv,cboz-block-size =3D <64>; =20 cpu45_intc: interrupt-controller { @@ -1648,6 +1694,7 @@ cpu46: cpu@46 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; riscv,cboz-block-size =3D <64>; =20 cpu46_intc: interrupt-controller { @@ -1683,6 +1730,7 @@ cpu47: cpu@47 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; riscv,cboz-block-size =3D <64>; =20 cpu47_intc: interrupt-controller { @@ -1718,6 +1766,7 @@ cpu48: cpu@48 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; riscv,cboz-block-size =3D <64>; =20 cpu48_intc: interrupt-controller { @@ -1753,6 +1802,7 @@ cpu49: cpu@49 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; riscv,cboz-block-size =3D <64>; =20 cpu49_intc: interrupt-controller { @@ -1788,6 +1838,7 @@ cpu50: cpu@50 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; riscv,cboz-block-size =3D <64>; =20 cpu50_intc: interrupt-controller { @@ -1823,6 +1874,7 @@ cpu51: cpu@51 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; riscv,cboz-block-size =3D <64>; =20 cpu51_intc: interrupt-controller { @@ -1858,6 +1910,7 @@ cpu52: cpu@52 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; riscv,cboz-block-size =3D <64>; =20 cpu52_intc: interrupt-controller { @@ -1893,6 +1946,7 @@ cpu53: cpu@53 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; riscv,cboz-block-size =3D <64>; =20 cpu53_intc: interrupt-controller { @@ -1928,6 +1982,7 @@ cpu54: cpu@54 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; riscv,cboz-block-size =3D <64>; =20 cpu54_intc: interrupt-controller { @@ -1963,6 +2018,7 @@ cpu55: cpu@55 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; riscv,cboz-block-size =3D <64>; =20 cpu55_intc: interrupt-controller { @@ -1998,6 +2054,7 @@ cpu56: cpu@56 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; riscv,cboz-block-size =3D <64>; =20 cpu56_intc: interrupt-controller { @@ -2033,6 +2090,7 @@ cpu57: cpu@57 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; riscv,cboz-block-size =3D <64>; =20 cpu57_intc: interrupt-controller { @@ -2068,6 +2126,7 @@ cpu58: cpu@58 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; riscv,cboz-block-size =3D <64>; =20 cpu58_intc: interrupt-controller { @@ -2103,6 +2162,7 @@ cpu59: cpu@59 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; riscv,cboz-block-size =3D <64>; =20 cpu59_intc: interrupt-controller { @@ -2138,6 +2198,7 @@ cpu60: cpu@60 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; riscv,cboz-block-size =3D <64>; =20 cpu60_intc: interrupt-controller { @@ -2173,6 +2234,7 @@ cpu61: cpu@61 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; riscv,cboz-block-size =3D <64>; =20 cpu61_intc: interrupt-controller { @@ -2208,6 +2270,7 @@ cpu62: cpu@62 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; riscv,cboz-block-size =3D <64>; =20 cpu62_intc: interrupt-controller { @@ -2243,6 +2306,7 @@ cpu63: cpu@63 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; riscv,cboz-block-size =3D <64>; =20 cpu63_intc: interrupt-controller { --=20 2.49.0