From nobody Fri Oct 10 20:14:45 2025 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6673A255F25; Fri, 13 Jun 2025 03:30:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749785416; cv=none; b=SSu+V5mxN+fjdAl9CTMrshTdg3t4IZxmIQiA61UiLjUX8rBWpfRwapD11rE6S3metrV5tJGMMH4AbLDbZ+lpuWphNU/SgUV5m23ntd41HdTE7gdIed/sYSpWp8ilyCXaoE8969+nSt3yRptRq/p4RJ2lWLXoooRXYXJBVvrJaXE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749785416; c=relaxed/simple; bh=tj5v2lTPpscT5QvibXqoywrHijTUIfaRegJvQYlhuNE=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=r6xmnfoLUdH0H44i1HYBgy3YdFuonStNPU58ETm7L3y25N/F4PCJMF+R3yP10zaz8afTl/YCovwUxgOVWELVuvPCDUuTQ/fnziuY7LOZS/A+lE6U6uko8L+N+nkIhCSVUTwhncUTo4w+DwFB1096gSOoUk5cKQQBOsjNzdxgcx8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Fri, 13 Jun 2025 11:30:02 +0800 Received: from mail.aspeedtech.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Fri, 13 Jun 2025 11:30:02 +0800 From: Jacky Chou To: , , , , , , , , , , , , , , , , , , , , CC: , , , , , Subject: [PATCH 4/7] ARM: dts: aspeed-g6: Add AST2600 PCIe RC PERST ctrl pin Date: Fri, 13 Jun 2025 11:29:58 +0800 Message-ID: <20250613033001.3153637-5-jacky_chou@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250613033001.3153637-1-jacky_chou@aspeedtech.com> References: <20250613033001.3153637-1-jacky_chou@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add pinctrl support for PCIe RC PERST pin. Signed-off-by: Jacky Chou --- arch/arm/boot/dts/aspeed/aspeed-g6-pinctrl.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-g6-pinctrl.dtsi b/arch/arm/boo= t/dts/aspeed/aspeed-g6-pinctrl.dtsi index 289668f051eb..a93e15c64a4b 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-g6-pinctrl.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-g6-pinctrl.dtsi @@ -2,6 +2,11 @@ // Copyright 2019 IBM Corp. =20 &pinctrl { + pinctrl_pcierc1_default: pcierc1_default { + function =3D "PCIERC1"; + groups =3D "PCIERC1"; + }; + pinctrl_adc0_default: adc0_default { function =3D "ADC0"; groups =3D "ADC0"; --=20 2.43.0