From nobody Fri Oct 10 19:51:00 2025 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 60B8D251792; Fri, 13 Jun 2025 03:30:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749785412; cv=none; b=fyWYmbX8c32n2SB6TcKfhaqhRd5DNovPClSueqGIDA5e/s0gmN6377++os8gfOp5qsy/CbNDCcGw5RE/e2rkHzGQdXGCTjd8vdAtDW+xCol0JWAv4T+svW1ej3vAn1l3BzLCBkbJNfyOMaQBS+dzlBen5Rw8sAyg6RBU1S9DRe4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749785412; c=relaxed/simple; bh=d4btG4/k2vUxuIehd/xlp45TXlb0ZP12PJdL4Ab+MAg=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=qwpa46t85E4dl3i1ZyLxsP9DLXz/ZXPDpG4aFhl7pgCjFcQa1gaByHXQ8L2gDzEiqJ+aiKN+nZgBvUqkkcQ9v5VBGdH47ggIkPaFtUX2IQxxeh4FGFD8Ep8NlglquHBXUuUPiGsRVZjy5uxq8mVXh1s3e4FVnPKmJqePkw6taUc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Fri, 13 Jun 2025 11:30:02 +0800 Received: from mail.aspeedtech.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Fri, 13 Jun 2025 11:30:02 +0800 From: Jacky Chou To: , , , , , , , , , , , , , , , , , , , , CC: , , , , , Subject: [PATCH 2/7] dt-bindings: pci: Add document for ASPEED PCIe Config Date: Fri, 13 Jun 2025 11:29:56 +0800 Message-ID: <20250613033001.3153637-3-jacky_chou@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250613033001.3153637-1-jacky_chou@aspeedtech.com> References: <20250613033001.3153637-1-jacky_chou@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add device tree binding documentation for the ASPEED AST2600/AST2700 PCIe configuration syscon block. This shared register space is used by multiple PCIe-related devices to coordinate and manage common PCIe settings. The binding describes the required compatible strings and register space for the configuration node. Signed-off-by: Jacky Chou --- .../bindings/pci/aspeed-pcie-cfg.yaml | 41 +++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/aspeed-pcie-cfg.y= aml diff --git a/Documentation/devicetree/bindings/pci/aspeed-pcie-cfg.yaml b/D= ocumentation/devicetree/bindings/pci/aspeed-pcie-cfg.yaml new file mode 100644 index 000000000000..6b51eedf4c47 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/aspeed-pcie-cfg.yaml @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/aspeed-pcie-cfg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ASPEED PCIe Configuration + +maintainers: + - Jacky Chou + +description: | + The ASPEED PCIe configuration syscon block provides a set of registers s= hared + by multiple PCIe-related devices within the SoC. This node represents the + common configuration space that allows these devices to coordinate and m= anage + shared PCIe settings, including address mapping, control, and status + registers. The syscon interface enables Linux drivers for various PCIe d= evices + to access and modify these shared registers in a consistent and central= ized + manner. + +properties: + compatible: + enum: + - aspeed,ast2600-pcie-cfg + - aspeed,ast2700-pcie-cfg + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + pcie-cfg@1e770000 { + compatible =3D "aspeed,ast2600-pcie-cfg"; + reg =3D <0x1e770000 0x80>; + }; --=20 2.43.0