From nobody Fri Oct 10 13:31:24 2025 Received: from sender4-op-o15.zoho.com (sender4-op-o15.zoho.com [136.143.188.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A8A43279DA2; Fri, 13 Jun 2025 08:51:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.15 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749804709; cv=pass; b=S3DCbKqM7pmsmEd/0o79COdYCwl77QpRRI9/dQIi5tmJ4JuyUM8AQNOJPNRBKOLGAAt3ZV59JlWImPRs78IpOks5qt69xFvUzrbVltt6gjAgutkcte+MqyKU5NecOI6zOgdvbrxNqnzu+7GfZqsjdPvO3ZAQ1hQyvTt6CHHmdAk= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749804709; c=relaxed/simple; bh=ODVCmynnJQ0c6rF92R6nLjsQtfRSNDqvQd+5DSy8y4U=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=A5SBWtRsFseXlfy/nvzcsJNLQFdmeUjRY/KS7hzi/SAN1Y+mcPSn9HcjJ0mYTTf2LnoiaqPXzXIgXPFR3sgQ0nvTnVnbAxYuTE71DBBK0mUDKxYCxbJtVil2sVnIkX3Mwp7fsI+43MUmaKLplxIWxC44MkEBAqd/I9ESmxlPYiI= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pigmoral.tech; spf=pass smtp.mailfrom=pigmoral.tech; dkim=pass (1024-bit key) header.d=pigmoral.tech header.i=junhui.liu@pigmoral.tech header.b=UhV1sAif; arc=pass smtp.client-ip=136.143.188.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pigmoral.tech Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pigmoral.tech Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=pigmoral.tech header.i=junhui.liu@pigmoral.tech header.b="UhV1sAif" ARC-Seal: i=1; a=rsa-sha256; t=1749804691; cv=none; d=zohomail.com; s=zohoarc; b=IRyADsCjocsmxO32MUEufnQW6uSqsOtsl2G2AYpwRcHeLS1C/gUSWL+mS+bgygM5G4IoKdWvMBgvMuJamSvVZcQS9AJBxlbaVX0oIAIYvZXyeKGmh5Gem06kFrX1pH/5AUXUM3VvSh/bMBcInA8uz3/g+x5vpXqKAb2I+k2D6WE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1749804691; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=RwMP1KKbEuTPv9DVxFj/JYtXhUf6m5oOAVvM8JZb6Ck=; b=Bb2c7NSEbIlrFQryQlt4zD6HHfGJFd7mWBAzu70UvqZAgUmy3RHK0xmywJN2dK3FeDBl2Hw0Cu+9aVx1At75SvD2eCYglstJqw4EK2ZQgcFuZRjrJNUnwabJkB4IKXUHomSVwdII5PwDLNofsi9CWMQ8cRrj0TCvkKdJCZAZ1BI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=pigmoral.tech; spf=pass smtp.mailfrom=junhui.liu@pigmoral.tech; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1749804691; s=zmail; d=pigmoral.tech; i=junhui.liu@pigmoral.tech; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=RwMP1KKbEuTPv9DVxFj/JYtXhUf6m5oOAVvM8JZb6Ck=; b=UhV1sAifH4NajvibGh1Lpa1lnF448iUa14VHkyaAxbcxhEdIC21ZvErxnoaUbKrx 2nQdI4A+JwZozxaCdqnd9tNmMkyzk5vzIbgWgHAvtxOMi6TsUkggcFXEp3sDnXxZZ5s NgQ6fLhb71zCQ7IBOeI26FsCUYcZAW8R0yAjuJvQ= Received: by mx.zohomail.com with SMTPS id 1749804689622264.10032570352325; Fri, 13 Jun 2025 01:51:29 -0700 (PDT) From: Junhui Liu Date: Fri, 13 Jun 2025 16:49:23 +0800 Subject: [PATCH v4 1/2] dt-bindings: reset: add support for canaan,k230-rst Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250613-k230-reset-v4-1-e5266d2be440@pigmoral.tech> References: <20250613-k230-reset-v4-0-e5266d2be440@pigmoral.tech> In-Reply-To: <20250613-k230-reset-v4-0-e5266d2be440@pigmoral.tech> To: Philipp Zabel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Junhui Liu Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Conor Dooley , Chen Wang X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1749804649; l=4335; i=junhui.liu@pigmoral.tech; s=20250507; h=from:subject:message-id; bh=ODVCmynnJQ0c6rF92R6nLjsQtfRSNDqvQd+5DSy8y4U=; b=dJYRjQodSJIOtUGkSfqJ5/mpHV7+dR+mhp9SwSmqknZQneUWRjqLiTxLBl/7gNdiluWOK7BJV QZeXAaD75jrB6x061OLdhx1r9IXRfbsPypb+MTb+g6eLJvZpYOLj/oa X-Developer-Key: i=junhui.liu@pigmoral.tech; a=ed25519; pk=d3i4H2mg9LUn4SQemoLAjLRQy0nTcyknIv6zgKMwiBA= X-ZohoMailClient: External Introduces a reset controller driver for the Kendryte K230 SoC, resposible for managing the reset functionality of the CPUs and various sub-modules. Reviewed-by: Conor Dooley Reviewed-by: Chen Wang Signed-off-by: Junhui Liu --- .../devicetree/bindings/reset/canaan,k230-rst.yaml | 39 ++++++++++ include/dt-bindings/reset/canaan,k230-rst.h | 90 ++++++++++++++++++= ++++ 2 files changed, 129 insertions(+) diff --git a/Documentation/devicetree/bindings/reset/canaan,k230-rst.yaml b= /Documentation/devicetree/bindings/reset/canaan,k230-rst.yaml new file mode 100644 index 0000000000000000000000000000000000000000..d352d0e12d8106a232bb5e6d7e1= 38697d2106937 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/canaan,k230-rst.yaml @@ -0,0 +1,39 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/canaan,k230-rst.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Canaan Kendryte K230 Reset Controller + +maintainers: + - Junhui Liu + +description: + The Canaan Kendryte K230 reset controller is part of the SoC's system + controller and controls the reset registers for CPUs and various periphe= rals. + +properties: + compatible: + const: canaan,k230-rst + + reg: + maxItems: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + - '#reset-cells' + +additionalProperties: false + +examples: + - | + reset-controller@91101000 { + compatible =3D "canaan,k230-rst"; + reg =3D <0x91101000 0x1000>; + #reset-cells =3D <1>; + }; diff --git a/include/dt-bindings/reset/canaan,k230-rst.h b/include/dt-bindi= ngs/reset/canaan,k230-rst.h new file mode 100644 index 0000000000000000000000000000000000000000..e4f6612607fea2faf2bcaa80add= 0b291c3371e4b --- /dev/null +++ b/include/dt-bindings/reset/canaan,k230-rst.h @@ -0,0 +1,90 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2023-2024 Canaan Bright Sight Co., Ltd + * Copyright (C) 2024-2025 Junhui Liu + */ +#ifndef _DT_BINDINGS_CANAAN_K230_RST_H_ +#define _DT_BINDINGS_CANAAN_K230_RST_H_ + +#define RST_CPU0 0 +#define RST_CPU1 1 +#define RST_CPU0_FLUSH 2 +#define RST_CPU1_FLUSH 3 +#define RST_AI 4 +#define RST_VPU 5 +#define RST_HISYS 6 +#define RST_HISYS_AHB 7 +#define RST_SDIO0 8 +#define RST_SDIO1 9 +#define RST_SDIO_AXI 10 +#define RST_USB0 11 +#define RST_USB1 12 +#define RST_USB0_AHB 13 +#define RST_USB1_AHB 14 +#define RST_SPI0 15 +#define RST_SPI1 16 +#define RST_SPI2 17 +#define RST_SEC 18 +#define RST_PDMA 19 +#define RST_SDMA 20 +#define RST_DECOMPRESS 21 +#define RST_SRAM 22 +#define RST_SHRM_AXIM 23 +#define RST_SHRM_AXIS 24 +#define RST_NONAI2D 25 +#define RST_MCTL 26 +#define RST_ISP 27 +#define RST_ISP_DW 28 +#define RST_DPU 29 +#define RST_DISP 30 +#define RST_GPU 31 +#define RST_AUDIO 32 +#define RST_TIMER0 33 +#define RST_TIMER1 34 +#define RST_TIMER2 35 +#define RST_TIMER3 36 +#define RST_TIMER4 37 +#define RST_TIMER5 38 +#define RST_TIMER_APB 39 +#define RST_HDI 40 +#define RST_WDT0 41 +#define RST_WDT1 42 +#define RST_WDT0_APB 43 +#define RST_WDT1_APB 44 +#define RST_TS_APB 45 +#define RST_MAILBOX 46 +#define RST_STC 47 +#define RST_PMU 48 +#define RST_LOSYS_APB 49 +#define RST_UART0 50 +#define RST_UART1 51 +#define RST_UART2 52 +#define RST_UART3 53 +#define RST_UART4 54 +#define RST_I2C0 55 +#define RST_I2C1 56 +#define RST_I2C2 57 +#define RST_I2C3 58 +#define RST_I2C4 59 +#define RST_JAMLINK0_APB 60 +#define RST_JAMLINK1_APB 61 +#define RST_JAMLINK2_APB 62 +#define RST_JAMLINK3_APB 63 +#define RST_CODEC_APB 64 +#define RST_GPIO_DB 65 +#define RST_GPIO_APB 66 +#define RST_ADC 67 +#define RST_ADC_APB 68 +#define RST_PWM_APB 69 +#define RST_SHRM_APB 70 +#define RST_CSI0 71 +#define RST_CSI1 72 +#define RST_CSI2 73 +#define RST_CSI_DPHY 74 +#define RST_ISP_AHB 75 +#define RST_M0 76 +#define RST_M1 77 +#define RST_M2 78 +#define RST_SPI2AXI 79 + +#endif --=20 2.49.0 From nobody Fri Oct 10 13:31:24 2025 Received: from sender4-op-o15.zoho.com (sender4-op-o15.zoho.com [136.143.188.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E40C5279DB0; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250613-k230-reset-v4-2-e5266d2be440@pigmoral.tech> References: <20250613-k230-reset-v4-0-e5266d2be440@pigmoral.tech> In-Reply-To: <20250613-k230-reset-v4-0-e5266d2be440@pigmoral.tech> To: Philipp Zabel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Junhui Liu Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Chen Wang X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1749804649; l=15871; i=junhui.liu@pigmoral.tech; s=20250507; h=from:subject:message-id; bh=9W9APXg3+vhtmfMS0vgZtYO+hg6WerAmIGcJdJ1Z5pQ=; b=9fL9MrLBWj54BWJIqSy206/zqHq7LsqeVzG7EZo4wwxbG50TvCFwjpq/CXb+D3hBA/8Y2D1dt boyjUuvyt/PCfOTh6hqAfh026ZowEsaIAS1yckSxkYgSa38oj6F6x66 X-Developer-Key: i=junhui.liu@pigmoral.tech; a=ed25519; pk=d3i4H2mg9LUn4SQemoLAjLRQy0nTcyknIv6zgKMwiBA= X-ZohoMailClient: External Add support for the resets on Canaan Kendryte K230 SoC. The driver support CPU0, CPU1, L2 cache flush, hardware auto clear and software clear resets. Tested-by: Chen Wang Reviewed-by: Philipp Zabel Signed-off-by: Junhui Liu --- drivers/reset/Kconfig | 9 ++ drivers/reset/Makefile | 1 + drivers/reset/reset-k230.c | 371 +++++++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 381 insertions(+) diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index d85be5899da6aba92f89c25b00dacc6618bc2255..4649c72e9b6e81eb5fc8905915e= faf5c6863a4a0 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -140,6 +140,15 @@ config RESET_K210 Say Y if you want to control reset signals provided by this controller. =20 +config RESET_K230 + tristate "Reset controller driver for Canaan Kendryte K230 SoC" + depends on ARCH_CANAAN || COMPILE_TEST + depends on OF + help + Support for the Canaan Kendryte K230 RISC-V SoC reset controller. + Say Y if you want to control reset signals provided by this + controller. + config RESET_LANTIQ bool "Lantiq XWAY Reset Driver" if COMPILE_TEST default SOC_TYPE_XWAY diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 91e6348e33511bce1a25a19c718e9221d873154b..82488dac0f35eca7f874319f992= 882d59a40fc71 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -20,6 +20,7 @@ obj-$(CONFIG_RESET_IMX7) +=3D reset-imx7.o obj-$(CONFIG_RESET_IMX8MP_AUDIOMIX) +=3D reset-imx8mp-audiomix.o obj-$(CONFIG_RESET_INTEL_GW) +=3D reset-intel-gw.o obj-$(CONFIG_RESET_K210) +=3D reset-k210.o +obj-$(CONFIG_RESET_K230) +=3D reset-k230.o obj-$(CONFIG_RESET_LANTIQ) +=3D reset-lantiq.o obj-$(CONFIG_RESET_LPC18XX) +=3D reset-lpc18xx.o obj-$(CONFIG_RESET_MCHP_SPARX5) +=3D reset-microchip-sparx5.o diff --git a/drivers/reset/reset-k230.c b/drivers/reset/reset-k230.c new file mode 100644 index 0000000000000000000000000000000000000000..c81045bb4a142af7eb5ab648f04= d04cc95919255 --- /dev/null +++ b/drivers/reset/reset-k230.c @@ -0,0 +1,371 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2022-2024 Canaan Bright Sight Co., Ltd + * Copyright (C) 2024-2025 Junhui Liu + * + * The reset management module in the K230 SoC provides reset time control + * registers. For RST_TYPE_CPU0, RST_TYPE_CPU1 and RST_TYPE_SW_DONE, the p= eriod + * during which reset is applied or removed while the clock is stopped can= be + * set up to 15 * 0.25 =3D 3.75 =C2=B5s. For RST_TYPE_HW_DONE, that period= can be set + * up to 255 * 0.25 =3D 63.75 =C2=B5s. For RST_TYPE_FLUSH, the reset bit is + * automatically cleared by hardware when flush completes. + * + * Although this driver does not configure the reset time registers, delay= s have + * been added to the assert, deassert, and reset operations to cover the m= aximum + * reset time. Some reset types include done bits whose toggle does not + * unambiguously signal whether hardware reset removal or clock-stop period + * expiration occurred first. Delays are therefore retained for types with= done + * bits to ensure safe timing. + * + * Reference: K230 Technical Reference Manual V0.3.1 + * https://kendryte-download.canaan-creative.com/developer/k230/HDK/K230%E= 7%A1%AC%E4%BB%B6%E6%96%87%E6%A1%A3/K230_Technical_Reference_Manual_V0.3.1_2= 0241118.pdf + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +/** + * enum k230_rst_type - K230 reset types + * @RST_TYPE_CPU0: Reset type for CPU0 + * Automatically clears, has write enable and done bit, active high + * @RST_TYPE_CPU1: Reset type for CPU1 + * Manually clears, has write enable and done bit, active high + * @RST_TYPE_FLUSH: Reset type for CPU L2 cache flush + * Automatically clears, has write enable, no done bit, active high + * @RST_TYPE_HW_DONE: Reset type for hardware auto clear + * Automatically clears, no write enable, has done bit, active high + * @RST_TYPE_SW_DONE: Reset type for software manual clear + * Manually clears, no write enable and done bit, + * active high if ID is RST_SPI2AXI, otherwise active low + */ +enum k230_rst_type { + RST_TYPE_CPU0, + RST_TYPE_CPU1, + RST_TYPE_FLUSH, + RST_TYPE_HW_DONE, + RST_TYPE_SW_DONE, +}; + +struct k230_rst_map { + u32 offset; + enum k230_rst_type type; + u32 done; + u32 reset; +}; + +struct k230_rst { + struct reset_controller_dev rcdev; + void __iomem *base; + /* protect register read-modify-write */ + spinlock_t lock; +}; + +static const struct k230_rst_map k230_resets[] =3D { + [RST_CPU0] =3D { 0x4, RST_TYPE_CPU0, BIT(12), BIT(0) }, + [RST_CPU1] =3D { 0xc, RST_TYPE_CPU1, BIT(12), BIT(0) }, + [RST_CPU0_FLUSH] =3D { 0x4, RST_TYPE_FLUSH, 0, BIT(4) }, + [RST_CPU1_FLUSH] =3D { 0xc, RST_TYPE_FLUSH, 0, BIT(4) }, + [RST_AI] =3D { 0x14, RST_TYPE_HW_DONE, BIT(31), BIT(0) }, + [RST_VPU] =3D { 0x1c, RST_TYPE_HW_DONE, BIT(31), BIT(0) }, + [RST_HISYS] =3D { 0x2c, RST_TYPE_HW_DONE, BIT(4), BIT(0) }, + [RST_HISYS_AHB] =3D { 0x2c, RST_TYPE_HW_DONE, BIT(5), BIT(1) }, + [RST_SDIO0] =3D { 0x34, RST_TYPE_HW_DONE, BIT(28), BIT(0) }, + [RST_SDIO1] =3D { 0x34, RST_TYPE_HW_DONE, BIT(29), BIT(1) }, + [RST_SDIO_AXI] =3D { 0x34, RST_TYPE_HW_DONE, BIT(30), BIT(2) }, + [RST_USB0] =3D { 0x3c, RST_TYPE_HW_DONE, BIT(28), BIT(0) }, + [RST_USB1] =3D { 0x3c, RST_TYPE_HW_DONE, BIT(29), BIT(1) }, + [RST_USB0_AHB] =3D { 0x3c, RST_TYPE_HW_DONE, BIT(30), BIT(0) }, + [RST_USB1_AHB] =3D { 0x3c, RST_TYPE_HW_DONE, BIT(31), BIT(1) }, + [RST_SPI0] =3D { 0x44, RST_TYPE_HW_DONE, BIT(28), BIT(0) }, + [RST_SPI1] =3D { 0x44, RST_TYPE_HW_DONE, BIT(29), BIT(1) }, + [RST_SPI2] =3D { 0x44, RST_TYPE_HW_DONE, BIT(30), BIT(2) }, + [RST_SEC] =3D { 0x4c, RST_TYPE_HW_DONE, BIT(31), BIT(0) }, + [RST_PDMA] =3D { 0x54, RST_TYPE_HW_DONE, BIT(28), BIT(0) }, + [RST_SDMA] =3D { 0x54, RST_TYPE_HW_DONE, BIT(29), BIT(1) }, + [RST_DECOMPRESS] =3D { 0x5c, RST_TYPE_HW_DONE, BIT(31), BIT(0) }, + [RST_SRAM] =3D { 0x64, RST_TYPE_HW_DONE, BIT(28), BIT(0) }, + [RST_SHRM_AXIM] =3D { 0x64, RST_TYPE_HW_DONE, BIT(30), BIT(2) }, + [RST_SHRM_AXIS] =3D { 0x64, RST_TYPE_HW_DONE, BIT(31), BIT(3) }, + [RST_NONAI2D] =3D { 0x6c, RST_TYPE_HW_DONE, BIT(31), BIT(0) }, + [RST_MCTL] =3D { 0x74, RST_TYPE_HW_DONE, BIT(31), BIT(0) }, + [RST_ISP] =3D { 0x80, RST_TYPE_HW_DONE, BIT(29), BIT(6) }, + [RST_ISP_DW] =3D { 0x80, RST_TYPE_HW_DONE, BIT(28), BIT(5) }, + [RST_DPU] =3D { 0x88, RST_TYPE_HW_DONE, BIT(31), BIT(0) }, + [RST_DISP] =3D { 0x90, RST_TYPE_HW_DONE, BIT(31), BIT(0) }, + [RST_GPU] =3D { 0x98, RST_TYPE_HW_DONE, BIT(31), BIT(0) }, + [RST_AUDIO] =3D { 0xa4, RST_TYPE_HW_DONE, BIT(31), BIT(0) }, + [RST_TIMER0] =3D { 0x20, RST_TYPE_SW_DONE, 0, BIT(0) }, + [RST_TIMER1] =3D { 0x20, RST_TYPE_SW_DONE, 0, BIT(1) }, + [RST_TIMER2] =3D { 0x20, RST_TYPE_SW_DONE, 0, BIT(2) }, + [RST_TIMER3] =3D { 0x20, RST_TYPE_SW_DONE, 0, BIT(3) }, + [RST_TIMER4] =3D { 0x20, RST_TYPE_SW_DONE, 0, BIT(4) }, + [RST_TIMER5] =3D { 0x20, RST_TYPE_SW_DONE, 0, BIT(5) }, + [RST_TIMER_APB] =3D { 0x20, RST_TYPE_SW_DONE, 0, BIT(6) }, + [RST_HDI] =3D { 0x20, RST_TYPE_SW_DONE, 0, BIT(7) }, + [RST_WDT0] =3D { 0x20, RST_TYPE_SW_DONE, 0, BIT(12) }, + [RST_WDT1] =3D { 0x20, RST_TYPE_SW_DONE, 0, BIT(13) }, + [RST_WDT0_APB] =3D { 0x20, RST_TYPE_SW_DONE, 0, BIT(14) }, + [RST_WDT1_APB] =3D { 0x20, RST_TYPE_SW_DONE, 0, BIT(15) }, + [RST_TS_APB] =3D { 0x20, RST_TYPE_SW_DONE, 0, BIT(16) }, + [RST_MAILBOX] =3D { 0x20, RST_TYPE_SW_DONE, 0, BIT(17) }, + [RST_STC] =3D { 0x20, RST_TYPE_SW_DONE, 0, BIT(18) }, + [RST_PMU] =3D { 0x20, RST_TYPE_SW_DONE, 0, BIT(19) }, + [RST_LOSYS_APB] =3D { 0x24, RST_TYPE_SW_DONE, 0, BIT(0) }, + [RST_UART0] =3D { 0x24, RST_TYPE_SW_DONE, 0, BIT(1) }, + [RST_UART1] =3D { 0x24, RST_TYPE_SW_DONE, 0, BIT(2) }, + [RST_UART2] =3D { 0x24, RST_TYPE_SW_DONE, 0, BIT(3) }, + [RST_UART3] =3D { 0x24, RST_TYPE_SW_DONE, 0, BIT(4) }, + [RST_UART4] =3D { 0x24, RST_TYPE_SW_DONE, 0, BIT(5) }, + [RST_I2C0] =3D { 0x24, RST_TYPE_SW_DONE, 0, BIT(6) }, + [RST_I2C1] =3D { 0x24, RST_TYPE_SW_DONE, 0, BIT(7) }, + [RST_I2C2] =3D { 0x24, RST_TYPE_SW_DONE, 0, BIT(8) }, + [RST_I2C3] =3D { 0x24, RST_TYPE_SW_DONE, 0, BIT(9) }, + [RST_I2C4] =3D { 0x24, RST_TYPE_SW_DONE, 0, BIT(10) }, + [RST_JAMLINK0_APB] =3D { 0x24, RST_TYPE_SW_DONE, 0, BIT(11) }, + [RST_JAMLINK1_APB] =3D { 0x24, RST_TYPE_SW_DONE, 0, BIT(12) }, + [RST_JAMLINK2_APB] =3D { 0x24, RST_TYPE_SW_DONE, 0, BIT(13) }, + [RST_JAMLINK3_APB] =3D { 0x24, RST_TYPE_SW_DONE, 0, BIT(14) }, + [RST_CODEC_APB] =3D { 0x24, RST_TYPE_SW_DONE, 0, BIT(17) }, + [RST_GPIO_DB] =3D { 0x24, RST_TYPE_SW_DONE, 0, BIT(18) }, + [RST_GPIO_APB] =3D { 0x24, RST_TYPE_SW_DONE, 0, BIT(19) }, + [RST_ADC] =3D { 0x24, RST_TYPE_SW_DONE, 0, BIT(20) }, + [RST_ADC_APB] =3D { 0x24, RST_TYPE_SW_DONE, 0, BIT(21) }, + [RST_PWM_APB] =3D { 0x24, RST_TYPE_SW_DONE, 0, BIT(22) }, + [RST_SHRM_APB] =3D { 0x64, RST_TYPE_SW_DONE, 0, BIT(1) }, + [RST_CSI0] =3D { 0x80, RST_TYPE_SW_DONE, 0, BIT(0) }, + [RST_CSI1] =3D { 0x80, RST_TYPE_SW_DONE, 0, BIT(1) }, + [RST_CSI2] =3D { 0x80, RST_TYPE_SW_DONE, 0, BIT(2) }, + [RST_CSI_DPHY] =3D { 0x80, RST_TYPE_SW_DONE, 0, BIT(3) }, + [RST_ISP_AHB] =3D { 0x80, RST_TYPE_SW_DONE, 0, BIT(4) }, + [RST_M0] =3D { 0x80, RST_TYPE_SW_DONE, 0, BIT(7) }, + [RST_M1] =3D { 0x80, RST_TYPE_SW_DONE, 0, BIT(8) }, + [RST_M2] =3D { 0x80, RST_TYPE_SW_DONE, 0, BIT(9) }, + [RST_SPI2AXI] =3D { 0xa8, RST_TYPE_SW_DONE, 0, BIT(0) } +}; + +static inline struct k230_rst *to_k230_rst(struct reset_controller_dev *rc= dev) +{ + return container_of(rcdev, struct k230_rst, rcdev); +} + +static void k230_rst_clear_done(struct k230_rst *rstc, unsigned long id, + bool write_en) +{ + const struct k230_rst_map *rmap =3D &k230_resets[id]; + u32 reg; + + guard(spinlock_irqsave)(&rstc->lock); + + reg =3D readl(rstc->base + rmap->offset); + reg |=3D rmap->done; /* write 1 to clear */ + if (write_en) + reg |=3D rmap->done << 16; + writel(reg, rstc->base + rmap->offset); +} + +static int k230_rst_wait_and_clear_done(struct k230_rst *rstc, unsigned lo= ng id, + bool write_en) +{ + const struct k230_rst_map *rmap =3D &k230_resets[id]; + u32 reg; + int ret; + + ret =3D readl_poll_timeout(rstc->base + rmap->offset, reg, + reg & rmap->done, 10, 1000); + if (ret) { + dev_err(rstc->rcdev.dev, "Wait for reset done timeout\n"); + return ret; + } + + k230_rst_clear_done(rstc, id, write_en); + + return 0; +} + +static void k230_rst_update(struct k230_rst *rstc, unsigned long id, + bool assert, bool write_en, bool active_low) +{ + const struct k230_rst_map *rmap =3D &k230_resets[id]; + u32 reg; + + guard(spinlock_irqsave)(&rstc->lock); + + reg =3D readl(rstc->base + rmap->offset); + if (assert ^ active_low) + reg |=3D rmap->reset; + else + reg &=3D ~rmap->reset; + if (write_en) + reg |=3D rmap->reset << 16; + writel(reg, rstc->base + rmap->offset); +} + +static int k230_rst_assert(struct reset_controller_dev *rcdev, unsigned lo= ng id) +{ + struct k230_rst *rstc =3D to_k230_rst(rcdev); + + switch (k230_resets[id].type) { + case RST_TYPE_CPU1: + k230_rst_update(rstc, id, true, true, false); + break; + case RST_TYPE_SW_DONE: + k230_rst_update(rstc, id, true, false, + id =3D=3D RST_SPI2AXI ? false : true); + break; + case RST_TYPE_CPU0: + case RST_TYPE_FLUSH: + case RST_TYPE_HW_DONE: + return -EOPNOTSUPP; + } + + /* + * The time period when reset is applied but the clock is stopped for + * RST_TYPE_CPU1 and RST_TYPE_SW_DONE can be set up to 3.75us. Delay + * 10us to ensure proper reset timing. + */ + udelay(10); + + return 0; +} + +static int k230_rst_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct k230_rst *rstc =3D to_k230_rst(rcdev); + int ret =3D 0; + + switch (k230_resets[id].type) { + case RST_TYPE_CPU1: + k230_rst_update(rstc, id, false, true, false); + ret =3D k230_rst_wait_and_clear_done(rstc, id, true); + break; + case RST_TYPE_SW_DONE: + k230_rst_update(rstc, id, false, false, + id =3D=3D RST_SPI2AXI ? false : true); + break; + case RST_TYPE_CPU0: + case RST_TYPE_FLUSH: + case RST_TYPE_HW_DONE: + return -EOPNOTSUPP; + } + + /* + * The time period when reset is removed but the clock is stopped for + * RST_TYPE_CPU1 and RST_TYPE_SW_DONE can be set up to 3.75us. Delay + * 10us to ensure proper reset timing. + */ + udelay(10); + + return ret; +} + +static int k230_rst_reset(struct reset_controller_dev *rcdev, unsigned lon= g id) +{ + struct k230_rst *rstc =3D to_k230_rst(rcdev); + const struct k230_rst_map *rmap =3D &k230_resets[id]; + u32 reg; + int ret =3D 0; + + switch (rmap->type) { + case RST_TYPE_CPU0: + k230_rst_clear_done(rstc, id, true); + k230_rst_update(rstc, id, true, true, false); + ret =3D k230_rst_wait_and_clear_done(rstc, id, true); + + /* + * The time period when reset is applied and removed but the + * clock is stopped for RST_TYPE_CPU0 can be set up to 7.5us. + * Delay 10us to ensure proper reset timing. + */ + udelay(10); + + break; + case RST_TYPE_FLUSH: + k230_rst_update(rstc, id, true, true, false); + + /* Wait flush request bit auto cleared by hardware */ + ret =3D readl_poll_timeout(rstc->base + rmap->offset, reg, + !(reg & rmap->reset), 10, 1000); + if (ret) + dev_err(rcdev->dev, "Wait for flush done timeout\n"); + + break; + case RST_TYPE_HW_DONE: + k230_rst_clear_done(rstc, id, false); + k230_rst_update(rstc, id, true, false, false); + ret =3D k230_rst_wait_and_clear_done(rstc, id, false); + + /* + * The time period when reset is applied and removed but the + * clock is stopped for RST_TYPE_HW_DONE can be set up to + * 127.5us. Delay 200us to ensure proper reset timing. + */ + fsleep(200); + + break; + case RST_TYPE_CPU1: + case RST_TYPE_SW_DONE: + k230_rst_assert(rcdev, id); + ret =3D k230_rst_deassert(rcdev, id); + break; + } + + return ret; +} + +static const struct reset_control_ops k230_rst_ops =3D { + .reset =3D k230_rst_reset, + .assert =3D k230_rst_assert, + .deassert =3D k230_rst_deassert, +}; + +static int k230_rst_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct k230_rst *rstc; + + rstc =3D devm_kzalloc(dev, sizeof(*rstc), GFP_KERNEL); + if (!rstc) + return -ENOMEM; + + rstc->base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(rstc->base)) + return PTR_ERR(rstc->base); + + spin_lock_init(&rstc->lock); + + rstc->rcdev.dev =3D dev; + rstc->rcdev.owner =3D THIS_MODULE; + rstc->rcdev.ops =3D &k230_rst_ops; + rstc->rcdev.nr_resets =3D ARRAY_SIZE(k230_resets); + rstc->rcdev.of_node =3D dev->of_node; + + return devm_reset_controller_register(dev, &rstc->rcdev); +} + +static const struct of_device_id k230_rst_match[] =3D { + { .compatible =3D "canaan,k230-rst", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, k230_rst_match); + +static struct platform_driver k230_rst_driver =3D { + .probe =3D k230_rst_probe, + .driver =3D { + .name =3D "k230-rst", + .of_match_table =3D k230_rst_match, + } +}; +module_platform_driver(k230_rst_driver); + +MODULE_AUTHOR("Junhui Liu "); +MODULE_DESCRIPTION("Canaan K230 reset driver"); +MODULE_LICENSE("GPL"); --=20 2.49.0